From c69852c0cc0aececddadb8dc0ad1120576f384a9 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 23 Mar 2023 16:57:10 +0100 Subject: [PATCH] ClockDomainResetGeneratorIf introduction --- src/main/scala/vexriscv/VexRiscvBmbGenerator.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala index 2754d39..4af0e08 100644 --- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala +++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala @@ -45,7 +45,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener withRiscvDebug.load(false) } - def enableJtag(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd.rework{ + def enableJtag(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{ this.debugClockDomain.load(debugCd.outputClockDomain) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() @@ -53,7 +53,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) } - def enableJtagInstructionCtrl(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd.rework{ + def enableJtagInstructionCtrl(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{ this.debugClockDomain.load(debugCd.outputClockDomain) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() @@ -61,7 +61,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) } - def enableDebugBus(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd.rework{ + def enableDebugBus(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{ this.debugClockDomain.load(debugCd.outputClockDomain) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() @@ -69,7 +69,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) } - def enableRiscvDebug(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGenerator) : Unit = debugCd.on{ + def enableRiscvDebug(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.on{ this.debugClockDomain.load(debugCd) debugAskReset.loadNothing() withRiscvDebug.load(true) @@ -85,7 +85,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener val debugBmbAccessSource = Handle[BmbAccessCapabilities] val debugBmbAccessRequirements = Handle[BmbAccessParameter] - def enableDebugBmb(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.on{ + def enableDebugBmb(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGeneratorIf, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.on{ this.debugClockDomain.load(debugCd) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing()