diff --git a/src/main/scala/vexriscv/Riscv.scala b/src/main/scala/vexriscv/Riscv.scala
index 91cf876..7874e02 100644
--- a/src/main/scala/vexriscv/Riscv.scala
+++ b/src/main/scala/vexriscv/Riscv.scala
@@ -159,5 +159,7 @@ object Riscv{
 
     def UCYCLE    = 0xC00 // UR Machine ucycle counter.
     def UCYCLEH   = 0xC80
+    def UINSTRET  = 0xC02 // UR Machine instructions-retired counter.
+    def UINSTRETH = 0xC82 // UR Upper 32 bits of minstret, RV32I only.
   }
 }
diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala
index 2bf5947..dd794a6 100644
--- a/src/main/scala/vexriscv/demo/Briey.scala
+++ b/src/main/scala/vexriscv/demo/Briey.scala
@@ -147,7 +147,8 @@ object BrieyConfig{
             minstretAccess = CsrAccess.NONE,
             ecallGen       = false,
             wfiGenAsWait         = false,
-            ucycleAccess   = CsrAccess.NONE
+            ucycleAccess   = CsrAccess.NONE,
+            uinstretAccess = CsrAccess.NONE
           )
         ),
         new YamlPlugin("cpu0.yaml")
diff --git a/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala
index 593d399..49f51ae 100644
--- a/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala
+++ b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala
@@ -126,7 +126,8 @@ object VexRiscvAhbLite3{
               minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
               wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE
+              ucycleAccess   = CsrAccess.NONE,
+              uinstretAccess = CsrAccess.NONE
             )
           ),
           new YamlPlugin("cpu0.yaml")
diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
index 4245cd1..b2c3f69 100644
--- a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
+++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
@@ -124,7 +124,8 @@ object VexRiscvAvalonForSim{
               minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
               wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE
+              ucycleAccess   = CsrAccess.NONE,
+              uinstretAccess = CsrAccess.NONE
             )
           ),
           new YamlPlugin("cpu0.yaml")
diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
index bba065e..063d945 100644
--- a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
+++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
@@ -121,7 +121,8 @@ object VexRiscvAvalonWithIntegratedJtag{
               minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
               wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE
+              ucycleAccess   = CsrAccess.NONE,
+              uinstretAccess = CsrAccess.NONE
             )
           ),
           new YamlPlugin("cpu0.yaml")
diff --git a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
index b002c06..67556e9 100644
--- a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
+++ b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
@@ -122,7 +122,8 @@ object VexRiscvAxi4WithIntegratedJtag{
               minstretAccess = CsrAccess.NONE,
               ecallGen       = false,
               wfiGenAsWait         = false,
-              ucycleAccess   = CsrAccess.NONE
+              ucycleAccess   = CsrAccess.NONE,
+              uinstretAccess = CsrAccess.NONE
             )
           ),
           new YamlPlugin("cpu0.yaml")
diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index 0cdc896..539e534 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -49,6 +49,7 @@ case class CsrPluginConfig(
                             mcycleAccess        : CsrAccess,
                             minstretAccess      : CsrAccess,
                             ucycleAccess        : CsrAccess,
+                            uinstretAccess      : CsrAccess,
                             wfiGenAsWait        : Boolean,
                             ecallGen            : Boolean,
                             xtvecModeGen        : Boolean = false,
@@ -100,6 +101,7 @@ object CsrPluginConfig{
     mcycleAccess        = CsrAccess.NONE,
     minstretAccess      = CsrAccess.NONE,
     ucycleAccess        = CsrAccess.NONE,
+    uinstretAccess      = CsrAccess.NONE,
     wfiGenAsWait        = true,
     ecallGen            = true,
     xtvecModeGen        = false,
@@ -140,6 +142,7 @@ object CsrPluginConfig{
     mcycleAccess        = CsrAccess.READ_WRITE,
     minstretAccess      = CsrAccess.READ_WRITE,
     ucycleAccess        = CsrAccess.READ_ONLY,
+    uinstretAccess      = CsrAccess.READ_ONLY,
     wfiGenAsWait        = true,
     ecallGen            = true,
     xtvecModeGen        = false,
@@ -180,7 +183,8 @@ object CsrPluginConfig{
     minstretAccess     = CsrAccess.READ_WRITE,
     ecallGen           = true,
     wfiGenAsWait       = true,
-    ucycleAccess       = CsrAccess.READ_ONLY
+    ucycleAccess       = CsrAccess.READ_ONLY,
+    uinstretAccess     = CsrAccess.READ_ONLY
   )
 
   def all2(mtvecInit : BigInt) : CsrPluginConfig = CsrPluginConfig(
@@ -202,6 +206,7 @@ object CsrPluginConfig{
     ecallGen       = true,
     wfiGenAsWait         = true,
     ucycleAccess   = CsrAccess.READ_ONLY,
+    uinstretAccess = CsrAccess.READ_ONLY,
     supervisorGen  = true,
     sscratchGen    = true,
     stvecAccess    = CsrAccess.READ_WRITE,
@@ -233,7 +238,8 @@ object CsrPluginConfig{
     minstretAccess = CsrAccess.NONE,
     ecallGen       = false,
     wfiGenAsWait         = false,
-    ucycleAccess   = CsrAccess.NONE
+    ucycleAccess   = CsrAccess.NONE,
+    uinstretAccess = CsrAccess.NONE
   )
 
   def smallest(mtvecInit : BigInt)  = CsrPluginConfig(
@@ -254,7 +260,8 @@ object CsrPluginConfig{
     minstretAccess = CsrAccess.NONE,
     ecallGen       = false,
     wfiGenAsWait         = false,
-    ucycleAccess   = CsrAccess.NONE
+    ucycleAccess   = CsrAccess.NONE,
+    uinstretAccess = CsrAccess.NONE
   )
 
 }
@@ -586,6 +593,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
       //User CSR
       ucycleAccess(CSR.UCYCLE, mcycle(31 downto 0))
       ucycleAccess(CSR.UCYCLEH, mcycle(63 downto 32))
+      uinstretAccess(CSR.UINSTRET, minstret(31 downto 0))
+      uinstretAccess(CSR.UINSTRETH, minstret(63 downto 32))
 
       pipeline(MPP) := mstatus.MPP
     }
@@ -1148,4 +1157,4 @@ class UserInterruptPlugin(interruptName : String, code : Int, privilege : Int =
     csr.rw(csrAddress = CSR.MIE, bitOffset = code, interruptEnable)
   }
   override def build(pipeline: VexRiscv): Unit = {}
-}
\ No newline at end of file
+}