From c8016e90a4987a30b6fde5e435626760ddf4b322 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sun, 23 Feb 2020 20:25:31 +0100 Subject: [PATCH] MulPlugin now add KEEP attribute on RS1 and RS2 to force Vivado to not retime it with the DSP --- src/main/scala/vexriscv/plugin/MulPlugin.scala | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/main/scala/vexriscv/plugin/MulPlugin.scala b/src/main/scala/vexriscv/plugin/MulPlugin.scala index 96db3e9..efe3ba0 100644 --- a/src/main/scala/vexriscv/plugin/MulPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulPlugin.scala @@ -2,6 +2,7 @@ package vexriscv.plugin import vexriscv._ import vexriscv.VexRiscv import spinal.core._ +import spinal.lib.KeepAttribute //Input buffer generaly avoid the FPGA synthesis to duplicate reg inside the DSP cell, which could stress timings quite much. class MulPlugin(inputBuffer : Boolean = false) extends Plugin[VexRiscv]{ @@ -94,6 +95,12 @@ class MulPlugin(inputBuffer : Boolean = false) extends Plugin[VexRiscv]{ insert(MUL_LH) := aSLow * bHigh insert(MUL_HL) := aHigh * bSLow insert(MUL_HH) := aHigh * bHigh + + Component.current.afterElaboration{ + //Avoid synthesis tools to retime RS1 RS2 from execute stage to decode stage leading to bad timings (ex : Vivado, even if retiming is disabled) + KeepAttribute(input(RS1).getDrivingReg) + KeepAttribute(input(RS2).getDrivingReg) + } } //First aggregation of partial multiplication