diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala
index 0749b2c..8220c44 100644
--- a/src/main/scala/vexriscv/TestsWorkspace.scala
+++ b/src/main/scala/vexriscv/TestsWorkspace.scala
@@ -40,6 +40,7 @@ object TestsWorkspace {
 //            compressedGen = true
 //          ),
           new IBusCachedPlugin(
+            resetVector = 0x80000000l,
             config = InstructionCacheConfig(
               cacheSize = 1024*16,
               bytePerLine = 32,
diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala
index 7bc4cd0..4cea558 100644
--- a/src/main/scala/vexriscv/plugin/Fetcher.scala
+++ b/src/main/scala/vexriscv/plugin/Fetcher.scala
@@ -17,7 +17,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
                                val injectorReadyCutGen : Boolean,
                                val relaxedPcCalculation : Boolean,
                                val prediction : BranchPrediction,
-                               val catchAddressMisaligned : Boolean,
+                               val catchAddressMisaligned : Boolean, //Catch broken prediction ?
                                val injectorStage : Boolean) extends Plugin[VexRiscv] with JumpService with IBusFetcher{
   var prefetchExceptionPort : Flow[ExceptionCause] = null
 
diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
index 6212234..8b03ddb 100644
--- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
@@ -9,17 +9,24 @@ import spinal.lib._
 //  var iBus  : InstructionCacheMemBus = null
 //  override def build(pipeline: VexRiscv): Unit = ???
 //}
-class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConfig : Any = null)  extends IBusFetcherImpl(
+class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
+                       relaxedPcCalculation : Boolean = false,
+                       prediction : BranchPrediction = NONE,
+                       compressedGen : Boolean = false,
+                       keepPcPlus4 : Boolean = false,
+                       catchAddressMisaligned : Boolean = false,
+                       config : InstructionCacheConfig,
+                       memoryTranslatorPortConfig : Any = null)  extends IBusFetcherImpl(
   catchAccessFault = config.catchAccessFault,
-  resetVector = BigInt(0x80000000l),
-  keepPcPlus4 = false,
-  decodePcGen = true,
-  compressedGen = true,
+  resetVector = resetVector,
+  keepPcPlus4 = keepPcPlus4,
+  decodePcGen = compressedGen,
+  compressedGen = compressedGen,
   cmdToRspStageCount = (if(config.twoCycleCache) 2 else 1),
   injectorReadyCutGen = false,
-  relaxedPcCalculation = false,
-  prediction = NONE,
-  catchAddressMisaligned = false,
+  relaxedPcCalculation = relaxedPcCalculation,
+  prediction = prediction,
+  catchAddressMisaligned = catchAddressMisaligned,
   injectorStage = !config.twoCycleCache){
   import config._
 
diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
index 24a146e..7a6045a 100644
--- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
@@ -104,10 +104,10 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste
 
 
 class IBusSimplePlugin(resetVector : BigInt,
-                       relaxedPcCalculation : Boolean,
-                       prediction : BranchPrediction,
-                       catchAccessFault : Boolean,
-                       catchAddressMisaligned : Boolean,
+                       catchAccessFault : Boolean = false,
+                       catchAddressMisaligned : Boolean = false,
+                       relaxedPcCalculation : Boolean = false,
+                       prediction : BranchPrediction = NONE,
                        keepPcPlus4 : Boolean = false,
                        compressedGen : Boolean = false,
                        busLatencyMin : Int = 1,