From cabf602efcf77ca1b3b8fc2aeb307aa1caf93dbb Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Fri, 19 May 2017 17:13:33 +0200
Subject: [PATCH] Update README.md

---
 README.md | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index d5c30ea..0a01dbc 100644
--- a/README.md
+++ b/README.md
@@ -6,6 +6,8 @@ This repository host an RISC-V implementation written in SpinalHDL. There is som
 - 1.17 DMIPS/Mhz with all extension
 - Optimized for FPGA
 - Optional MUL/DIV/REM extension
+- Optional instruction and data caches
+- Optional MMU
 - Two implementation of shift instructions, Single cycle / shiftNumber cycle
 - Each stage could have bypass or interlock hazard logic
 - FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV
@@ -135,4 +137,4 @@ class AluPlugin() extends Plugin[VexRiscv]{
     }
   }
 }
-```
\ No newline at end of file
+```