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VexRiscv
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Update README.md

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Dolu1990 2017-05-19 17:13:33 +02:00 committed by GitHub
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@ -6,6 +6,8 @@ This repository host an RISC-V implementation written in SpinalHDL. There is som
- 1.17 DMIPS/Mhz with all extension - 1.17 DMIPS/Mhz with all extension
- Optimized for FPGA - Optimized for FPGA
- Optional MUL/DIV/REM extension - Optional MUL/DIV/REM extension
- Optional instruction and data caches
- Optional MMU
- Two implementation of shift instructions, Single cycle / shiftNumber cycle - Two implementation of shift instructions, Single cycle / shiftNumber cycle
- Each stage could have bypass or interlock hazard logic - Each stage could have bypass or interlock hazard logic
- FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV - FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV
@ -135,4 +137,4 @@ class AluPlugin() extends Plugin[VexRiscv]{
} }
} }
} }
``` ```