diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala
index a0590ad..b507881 100644
--- a/src/main/scala/vexriscv/demo/Murax.scala
+++ b/src/main/scala/vexriscv/demo/Murax.scala
@@ -483,3 +483,13 @@ object Murax_arty{
     SpinalVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB, onChipRamHexFile = hex)))
   }
 }
+
+
+object MuraxAsicBlackBox{
+  def main(args: Array[String]) {
+    println("Warning this soc do not has any rom to boot on.")
+    val config = SpinalConfig()
+    config.addStandardMemBlackboxing(blackboxAll)
+    config.generateVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB)))
+  }
+}
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