From caf1bde49b643939cb2c717dbcae450a4f1ca58b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 4 Mar 2021 10:16:45 +0100 Subject: [PATCH] Add MuraxAsicBlackBox example --- src/main/scala/vexriscv/demo/Murax.scala | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index a0590ad..b507881 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -483,3 +483,13 @@ object Murax_arty{ SpinalVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB, onChipRamHexFile = hex))) } } + + +object MuraxAsicBlackBox{ + def main(args: Array[String]) { + println("Warning this soc do not has any rom to boot on.") + val config = SpinalConfig() + config.addStandardMemBlackboxing(blackboxAll) + config.generateVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB))) + } +} \ No newline at end of file