From d2e5755df4f7aa0566eeffb4e243027c4de5f811 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 31 Jan 2018 18:29:30 +0100 Subject: [PATCH] revert removed code by mistake --- src/main/scala/vexriscv/demo/GenCustomCsr.scala | 2 +- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 15 ++++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/main/scala/vexriscv/demo/GenCustomCsr.scala b/src/main/scala/vexriscv/demo/GenCustomCsr.scala index 5357f5d..8978efa 100644 --- a/src/main/scala/vexriscv/demo/GenCustomCsr.scala +++ b/src/main/scala/vexriscv/demo/GenCustomCsr.scala @@ -8,7 +8,7 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin} * Created by spinalvm on 15.06.17. */ -//make clean run DBUS=SIMPLE IBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no +//make clean run DBUS=SIMPLE IBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no CUSTOM_CSR=yes object GenCustomCsr extends App{ def cpu() = new VexRiscv( config = VexRiscvConfig( diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index b64effe..05c5379 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -129,11 +129,6 @@ case class CsrMapping() extends CsrInterface{ } -trait IContextSwitching{ - def isContextSwitching : Bool -} - - trait CsrInterface{ def r(csrAddress : Int, bitOffset : Int, that : Data): Unit def w(csrAddress : Int, bitOffset : Int, that : Data): Unit @@ -149,6 +144,10 @@ trait CsrInterface{ } +trait IContextSwitching{ + def isContextSwitching : Bool +} + class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{ import config._ import CsrAccess._ @@ -463,9 +462,11 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio execute plug new Area { import execute._ - val illegalAccess = True + val illegalAccess = arbitration.isValid && input(IS_CSR) if(catchIllegalAccess) { - selfException.valid := arbitration.isValid && input(IS_CSR) && illegalAccess + val illegalInstruction = arbitration.isValid && privilege === 0 && (input(ENV_CTRL) === EnvCtrlEnum.EBREAK || input(ENV_CTRL) === EnvCtrlEnum.MRET) + + selfException.valid := illegalAccess || illegalInstruction selfException.code := 2 selfException.badAddr.assignDontCare() }