From d6777ae8ec7ac212c070f73324b58d1a706d12c8 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 9 Nov 2017 20:10:56 +0100 Subject: [PATCH] usetRegIfNoAssign upgrade --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 4c3c310..47996aa 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -337,7 +337,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{ val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min val exceptionValids = Vec(Bool,stages.length) - val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length) + val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length).unsetRegIfNoAssignement val exceptionContext = Reg(ExceptionCause()) val pipelineHasException = exceptionValids.orR //TODO FMAX maybe could be partialy pipelined