From d6e8a5ef22042ddb962cfbf627efe909bb23da95 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Sat, 23 Jan 2021 20:16:58 +0100
Subject: [PATCH] VexRiscvSmpLitex options refractoring

---
 .../scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala     | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
index 585a1a0..4098f9e 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
@@ -92,8 +92,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
     opt[String]("netlist-directory") action { (v, c) => netlistDirectory = v }
     opt[String]("netlist-name") action { (v, c) => netlistName = v }
     opt[String]("aes-instruction") action { (v, c) => aesInstruction = v.toBoolean }
-    opt[Unit]("in-order-decoder") action { (v, c) => outOfOrderDecoder = false }
-    opt[Unit]("wishbone-memory") action { (v, c) => wishboneMemory = true }
+    opt[String]("out-of-order-decoder") action { (v, c) => outOfOrderDecoder = v.toBoolean  }
+    opt[String]("wishbone-memory" ) action { (v, c) => wishboneMemory = v.toBoolean  }
   }.parse(args))
 
   val coherency = coherentDma || cpuCount > 1