From d95793494942e334f9c643d2b61f231218714cc7 Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Mon, 19 Feb 2018 22:44:46 +0100
Subject: [PATCH] Fix ICache exception priority over miss reload

---
 .../scala/vexriscv/ip/InstructionCache.scala  | 20 +++++++++----------
 .../vexriscv/plugin/IBusCachedPlugin.scala    |  2 +-
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala
index ab09dae..fe57dc1 100644
--- a/src/main/scala/vexriscv/ip/InstructionCache.scala
+++ b/src/main/scala/vexriscv/ip/InstructionCache.scala
@@ -77,15 +77,15 @@ case class InstructionCacheCpuDecode(p : InstructionCacheConfig) extends Bundle
   val isUser  = Bool
   val isStuck  = Bool
   val pc = UInt(p.addressWidth bits)
-  val redo  = Bool
+  val cacheMiss  = Bool
   val data  =  ifGen(p.dataOnDecode) (Bits(p.cpuDataWidth bits))
-  val error   = if(p.catchAccessFault) Bool else null
-  val mmuMiss   = if(p.catchMemoryTranslationMiss) Bool else null
-  val illegalAccess = if(p.catchIllegalAccess) Bool else null
+  val error   =  Bool
+  val mmuMiss   =  Bool
+  val illegalAccess =Bool
 
   override def asMaster(): Unit = {
     out(isValid, isUser, isStuck, pc)
-    in(redo)
+    in(cacheMiss)
     inWithNull(error,mmuMiss,illegalAccess,data)
   }
 }
@@ -334,16 +334,16 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
       }
     }
 
-    io.cpu.decode.redo := io.cpu.decode.isValid && !hit.valid
-    when(io.cpu.decode.redo){
+    io.cpu.decode.cacheMiss := !hit.valid
+    when( io.cpu.decode.isValid && io.cpu.decode.cacheMiss){
       io.cpu.prefetch.haltIt := True
       lineLoader.valid := True
       lineLoader.address := mmuRsp.physicalAddress //Could be optimise if mmu not used
     }
 
-    if(catchAccessFault) io.cpu.decode.error := hit.error
-    if(catchMemoryTranslationMiss) io.cpu.decode.mmuMiss := mmuRsp.miss
-    if(catchIllegalAccess) io.cpu.decode.illegalAccess := !mmuRsp.allowExecute || (io.cpu.decode.isUser && !mmuRsp.allowUser)
+    io.cpu.decode.error := hit.error
+    io.cpu.decode.mmuMiss := mmuRsp.miss
+    io.cpu.decode.illegalAccess := !mmuRsp.allowExecute || (io.cpu.decode.isUser && !mmuRsp.allowUser)
   }
 }
 
diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
index 1c5999e..797a293 100644
--- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
@@ -112,7 +112,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig, askMemoryTranslation : B
     cache.io.cpu.decode.isUser  := (if(privilegeService != null) privilegeService.isUser(decode) else False)
 //    cache.io.cpu.decode.pc  := decode.input(PC)
 
-    redoBranch.valid := cache.io.cpu.decode.redo
+    redoBranch.valid := decode.arbitration.isValid && ownDecode && cache.io.cpu.decode.cacheMiss && !cache.io.cpu.decode.mmuMiss && !cache.io.cpu.decode.illegalAccess
     redoBranch.payload := decode.input(PC)
     when(redoBranch.valid){
       decode.arbitration.redoIt := True