From 050b4d8c62319715a47f950ca89278cbf0bd2187 Mon Sep 17 00:00:00 2001 From: AdDraw Date: Thu, 15 Jun 2023 22:57:20 +0200 Subject: [PATCH 1/2] Add halfPipe function to DBusSimpleBus --- src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index dbf6609..7053dcc 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -103,6 +103,13 @@ case class DBusSimpleBus(bigEndian : Boolean = false) extends Bundle with IMaste s } + def cmdHalfPipe() : DBusSimpleBus = { + val s = DBusSimpleBus(bigEndian) + s.cmd << this.cmd.halfPipe() + s.rsp <> this.rsp + s + } + def genMask(cmd : DBusSimpleCmd) = { if(bigEndian) cmd.size.mux( @@ -245,7 +252,7 @@ case class DBusSimpleBus(bigEndian : Boolean = false) extends Bundle with IMaste } bus } - + def toBmb() : Bmb = { val pipelinedMemoryBusConfig = DBusSimpleBus.getBmbParameter() val bus = Bmb(pipelinedMemoryBusConfig) From 7f647f9d8dffa3ac132f4a25036cc9f421d36726 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 16 Jun 2023 08:47:18 +0200 Subject: [PATCH 2/2] Update DBusSimplePlugin.scala --- src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 7053dcc..1dfa41f 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -106,7 +106,7 @@ case class DBusSimpleBus(bigEndian : Boolean = false) extends Bundle with IMaste def cmdHalfPipe() : DBusSimpleBus = { val s = DBusSimpleBus(bigEndian) s.cmd << this.cmd.halfPipe() - s.rsp <> this.rsp + s.rsp >> this.rsp s }