From da53de360f2ee9ca64375c2773b9cc2cb1fe8b28 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 10 Jan 2022 14:21:20 +0100 Subject: [PATCH] Fix lrsc from last commit --- src/main/scala/vexriscv/ip/DataCache.scala | 5 +++-- src/test/cpp/regression/main.cpp | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index 43bb919..02d3e9a 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -864,8 +864,9 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam val lrSc = withInternalLrSc generate new Area{ val reserved = RegInit(False) - when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.wr){ - reserved := False + when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck){ + reserved setWhen(request.isLrsc) + reserved clearWhen(request.wr) } } diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 82cc4d3..b5df2ef 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -898,6 +898,7 @@ public: status.fs = 3; pcWrite(pc + 4); } + lrscReserved = false; } break; #endif case 0x37:rfWrite(rd32, i & 0xFFFFF000);pcWrite(pc + 4);break; // LUI @@ -949,6 +950,7 @@ public: dWrite(pAddr, size, (uint8_t*)&i32_rs2); pcWrite(pc + 4); } + lrscReserved = false; }break; case 0x13: //ALUi switch ((i >> 12) & 0x7) { @@ -1107,9 +1109,7 @@ public: int32_t src = i32_rs2; int32_t readValue; - #ifdef DBUS_EXCLUSIVE lrscReserved = false; - #endif uint32_t pAddr; if(v2p(addr, &pAddr, READ_WRITE)){ trap(0, 15, addr); return; }