From d1691e94789950d583e2bb75ee7f26da16a128fa Mon Sep 17 00:00:00 2001 From: banahogg Date: Sat, 14 Nov 2020 17:31:50 -0800 Subject: [PATCH] Update GCC prebuild instructions for sifive.com reorg --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 57372fc..5d9c15e 100644 --- a/README.md +++ b/README.md @@ -412,7 +412,7 @@ Note that VexRiscv can run Linux on both cache full and cache less design. A prebuild GCC toolsuite can be found here: -- https://www.sifive.com/products/tools/ => SiFive GNU Embedded Toolchain +- https://www.sifive.com/software/ => Prebuilt RISC‑V GCC Toolchain and Emulator The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/riscv/__contentOfThisPreBuild__