From db3403359372289bd2387e1f92baa31abde5a952 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 8 Apr 2022 11:09:07 +0200 Subject: [PATCH] #240 Code generation now warn against cpu generation without illegal instruction catch and ebreak being disabled, as it may make crash some software, ex : rust --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 ++++ src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala | 3 +++ 2 files changed, 7 insertions(+) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index bd48928..5ba1523 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -532,6 +532,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep override def setup(pipeline: VexRiscv): Unit = { import pipeline.config._ + if(!config.ebreakGen) { + SpinalWarning("This VexRiscv configuration is set without software ebreak instruction support. Some software may rely on it (ex: Rust). (This isn't related to JTAG ebreak)") + } + csrMapping = new CsrMapping() inWfi = False.addTag(Verilator.public) diff --git a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala index a2ab111..a525b77 100644 --- a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala @@ -79,6 +79,9 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, override def setup(pipeline: VexRiscv): Unit = { + if(!catchIllegalInstruction) { + SpinalWarning("This VexRiscv configuration is set without illegal instruction catch support. Some software may rely on it (ex: Rust)") + } if(catchIllegalInstruction) { val exceptionService = pipeline.plugins.filter(_.isInstanceOf[ExceptionService]).head.asInstanceOf[ExceptionService] decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode).setName("decodeExceptionPort")