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#240 Code generation now warn against cpu generation without illegal instruction catch and ebreak being disabled, as it may make crash some software, ex : rust

This commit is contained in:
Dolu1990 2022-04-08 11:09:07 +02:00
parent e6c21996a4
commit db34033593
2 changed files with 7 additions and 0 deletions
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4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -532,6 +532,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
override def setup(pipeline: VexRiscv): Unit = { override def setup(pipeline: VexRiscv): Unit = {
import pipeline.config._ import pipeline.config._
if(!config.ebreakGen) {
SpinalWarning("This VexRiscv configuration is set without software ebreak instruction support. Some software may rely on it (ex: Rust). (This isn't related to JTAG ebreak)")
}
csrMapping = new CsrMapping() csrMapping = new CsrMapping()
inWfi = False.addTag(Verilator.public) inWfi = False.addTag(Verilator.public)

3
src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
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@ -79,6 +79,9 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false,
override def setup(pipeline: VexRiscv): Unit = { override def setup(pipeline: VexRiscv): Unit = {
if(!catchIllegalInstruction) {
SpinalWarning("This VexRiscv configuration is set without illegal instruction catch support. Some software may rely on it (ex: Rust)")
}
if(catchIllegalInstruction) { if(catchIllegalInstruction) {
val exceptionService = pipeline.plugins.filter(_.isInstanceOf[ExceptionService]).head.asInstanceOf[ExceptionService] val exceptionService = pipeline.plugins.filter(_.isInstanceOf[ExceptionService]).head.asInstanceOf[ExceptionService]
decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode).setName("decodeExceptionPort") decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode).setName("decodeExceptionPort")