From 25c0a0ff6fc4980e8ec8b5148fe213c24a245a56 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 13 Oct 2018 09:57:13 +0200 Subject: [PATCH 1/3] Add RVC into the readme Forgot to add RVC (compressed) support information into the readme --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index c4196b1..e9dae43 100644 --- a/README.md +++ b/README.md @@ -26,7 +26,7 @@ This repository hosts a RISC-V implementation written in SpinalHDL. Here are some specs : -- RV32I[M] instruction set +- RV32I[M][C] instruction set - Pipelined with 5 stages (Fetch, Decode, Execute, Memory, WriteBack) - 1.44 DMIPS/Mhz when all features are enabled - Optimized for FPGA, fully portable From 6334f430fe1bed302733c6ea6c44f8b514f3e2c6 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 4 Dec 2018 19:07:51 +0100 Subject: [PATCH 2/3] Update README.md Fix #44 --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index b67b0e3..430d162 100644 --- a/README.md +++ b/README.md @@ -159,7 +159,7 @@ You can find two example CPU instances in: - src/main/scala/vexriscv/GenFull.scala - src/main/scala/vexriscv/GenSmallest.scala -To generate the corresponding RTL as a VexRiscv.v file, run: +To generate the corresponding RTL as a VexRiscv.v file, run the following commands in the root directory of this repository: ```sh sbt "run-main vexriscv.demo.GenFull" From 961abb3cf10bab123e62445d7c0ab5d13470eff7 Mon Sep 17 00:00:00 2001 From: Brett Foster Date: Sat, 22 Dec 2018 07:58:59 -0800 Subject: [PATCH 3/3] Avalon: Debug Clock Domain for JTAG This change ensures that the clock domain for the JTAG interface uses the debug plugin's domain. Otherwise, resetting the processor will put the jtag debugger in to reset as well. See SpinalHDL/VexRiscv#48 --- .../scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala | 2 +- .../scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala index e4793d2..8908cad 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala @@ -162,7 +162,7 @@ object VexRiscvAvalonWithIntegratedJtag{ .setName("dBusAvalon") .addTag(ClockDomainTag(ClockDomain.current)) } - case plugin: DebugPlugin => { + case plugin: DebugPlugin => plugin.debugClockDomain { plugin.io.bus.setAsDirectionLess() val jtag = slave(new Jtag()) .setName("jtag") diff --git a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala index 9f339fb..8947636 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala @@ -163,7 +163,7 @@ object VexRiscvAxi4WithIntegratedJtag{ .setName("dBusAxi") .addTag(ClockDomainTag(ClockDomain.current)) } - case plugin: DebugPlugin => { + case plugin: DebugPlugin => plugin.debugClockDomain { plugin.io.bus.setAsDirectionLess() val jtag = slave(new Jtag()) .setName("jtag")