From dda5372a6c00b2e05590fed514dcde7ae1cf3282 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 14 Dec 2017 01:05:06 +0100 Subject: [PATCH] Fix typo --- src/test/scala/vexriscv/MuraxSim.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala index 6e9c242..27a771c 100644 --- a/src/test/scala/vexriscv/MuraxSim.scala +++ b/src/test/scala/vexriscv/MuraxSim.scala @@ -16,7 +16,7 @@ import scala.concurrent.ExecutionContext.Implicits.global object MuraxSim { def main(args: Array[String]): Unit = { // val config = MuraxConfig.default.copy(onChipRamSize = 256 kB) - val config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex") + val config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex") SimConfig(new Murax(config)).doManagedSim{dut => val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong