From de33128e01eb43dafc910f5c2ac5d40e4d6bd049 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sun, 30 Jul 2017 02:42:14 +0200 Subject: [PATCH] Add Murax 0.55 DMIPS/Mhz --- README.md | 12 ++++++----- src/main/scala/vexriscv/demo/Murax.scala | 26 ++++++++++++++++-------- 2 files changed, 24 insertions(+), 14 deletions(-) diff --git a/README.md b/README.md index a9030c7..bab4086 100644 --- a/README.md +++ b/README.md @@ -222,16 +222,18 @@ There is some measurements of Briey SoC timings and area : ## Murax SoC Murax is a very light SoC (fit in ICE40 FPGA) which could work without any external component. - -- ICE40-hx8k + icestorm => 53 Mhz, 2142 LC -- 0.37 DMIPS/Mhz -- 8 kB of on-chip ram +- VexRiscv RV32I[M] - JTAG debugger (eclipse/GDB/openocd ready) +- 8 kB of on-chip ram - Interrupt support - APB bus for peripherals - 32 GPIO pin - one 16 bits prescaler, two 16 bits timers +Depending the CPU configuration, on the ICE40-hx8k FPGA with icestorm for synthesis, the full SoC will get following area/performance : +- RV32I interlocked stages => 53 Mhz, 2142 LC 0.37 DMIPS/Mhz +- RV32I bypassed stages => 53 Mhz, 2463 LC 0.55 DMIPS/Mhz + You can find its implementation there : src/main/scala/vexriscv/demo/Murax.scala @@ -253,7 +255,7 @@ To connect OpenOCD (https://github.com/SpinalHDL/openocd_riscv) to the simulatio src/openocd -f tcl/interface/jtag_tcp.cfg -c "set MURAX_CPU0_YAML /home/spinalvm/Spinal/VexRiscv/cpu0.yaml" -f tcl/target/murax.cfg ``` -There is some measurements of Murax SoC timings and area : +There is some measurements of Murax SoC timings and area for the 0.37 DMIPS/Mhz SoC version : ``` Murax -> diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index a362e60..2116efa 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -29,6 +29,10 @@ import vexriscv.{plugin, VexRiscvConfig, VexRiscv} case class MuraxConfig(coreFrequency : HertzNumber, onChipRamSize : BigInt, + bypassExecute : Boolean, + bypassMemory: Boolean, + bypassWriteBack: Boolean, + bypassWriteBackBuffer : Boolean, pipelineDBus : Boolean, pipelineMainBus : Boolean, pipelineApbBridge : Boolean){ @@ -37,11 +41,15 @@ case class MuraxConfig(coreFrequency : HertzNumber, object MuraxConfig{ def default = MuraxConfig( - coreFrequency = 12 MHz, - onChipRamSize = 8 kB, - pipelineDBus = true, - pipelineMainBus = false, - pipelineApbBridge = true + coreFrequency = 12 MHz, + onChipRamSize = 8 kB, + bypassExecute = false, + bypassMemory = false, + bypassWriteBack = false, + bypassWriteBackBuffer = false, + pipelineDBus = true, + pipelineMainBus = false, + pipelineApbBridge = true ) } @@ -158,10 +166,10 @@ case class Murax(config : MuraxConfig) extends Component{ new LightShifterPlugin, new DebugPlugin(debugClockDomain), new HazardSimplePlugin( - bypassExecute = false, - bypassMemory = false, - bypassWriteBack = false, - bypassWriteBackBuffer = false, + bypassExecute = bypassExecute, + bypassMemory = bypassMemory, + bypassWriteBack = bypassWriteBack, + bypassWriteBackBuffer = bypassWriteBackBuffer, pessimisticUseSrc = false, pessimisticWriteRegFile = false, pessimisticAddressMatch = false