diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index bcd5b7b..ccedab4 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -31,13 +31,13 @@ object TestsWorkspace { SpinalConfig(mergeAsyncProcess = false).generateVerilog { val configFull = VexRiscvConfig( plugins = List( -// new PcManagerSimplePlugin( -// resetVector = 0x80000000l, -// relaxedPcCalculation = false -// ), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = true + resetVector = 0x80000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = true, + catchAddressMisaligned = true, + compressedGen = true ), // new IBusCachedPlugin( // config = InstructionCacheConfig( @@ -134,103 +134,6 @@ object TestsWorkspace { ) - val configLight = VexRiscvConfig( - plugins = List( - new PcManagerSimplePlugin(0x00000000l, false), - new IBusSimplePlugin( - interfaceKeepData = true, - catchAccessFault = false - ), - - new DBusSimplePlugin( - catchAddressMisaligned = false, - catchAccessFault = false - ), - new DecoderSimplePlugin( - catchIllegalInstruction = false - ), - new RegFilePlugin( - regFileReadyKind = plugin.ASYNC, - zeroBoot = false - ), - new IntAluPlugin, - new SrcPlugin( - separatedAddSub = false - ), - // new FullBarrielShifterPlugin, - new LightShifterPlugin, - // new HazardSimplePlugin(true, true, true, true), - // new HazardSimplePlugin(false, true, false, true), - new HazardSimplePlugin( - bypassExecute = false, - bypassMemory = false, - bypassWriteBack = false, - bypassWriteBackBuffer = false, - pessimisticUseSrc = false, - pessimisticWriteRegFile = false, - pessimisticAddressMatch = false - ), -// new HazardPessimisticPlugin, - new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), - // new MulPlugin, - // new DivPlugin, - // new MachineCsr(csrConfig), - new BranchPlugin( - earlyBranch = false, - catchAddressMisaligned = false, - prediction = NONE - ) - ) - ) - - - - val configTest = VexRiscvConfig( - plugins = List( - new PcManagerSimplePlugin(0x00000000l, true), - new IBusSimplePlugin( - interfaceKeepData = true, - catchAccessFault = true - ), - new DBusSimplePlugin( - catchAddressMisaligned = true, - catchAccessFault = true - ), - new CsrPlugin(CsrPluginConfig.small(0x80000020l)), - new DecoderSimplePlugin( - catchIllegalInstruction = true - ), - new RegFilePlugin( - regFileReadyKind = plugin.SYNC, - zeroBoot = false - ), - new IntAluPlugin, - new SrcPlugin( - separatedAddSub = false - ), - new FullBarrielShifterPlugin, - // new LightShifterPlugin, - // new HazardSimplePlugin(true, true, true, true), - // new HazardSimplePlugin(false, true, false, true), - new HazardSimplePlugin( - bypassExecute = false, - bypassMemory = false, - bypassWriteBack = false, - bypassWriteBackBuffer = false, - pessimisticUseSrc = false, - pessimisticWriteRegFile = false, - pessimisticAddressMatch = false - ), -// new MulPlugin, -// new DivPlugin, - // new MachineCsr(csrConfig), - new BranchPlugin( - earlyBranch = false, - catchAddressMisaligned = true, - prediction = NONE - ) - ) - ) val toplevel = new VexRiscv(configFull) // val toplevel = new VexRiscv(configLight) diff --git a/src/main/scala/vexriscv/demo/FormalSimple.scala b/src/main/scala/vexriscv/demo/FormalSimple.scala index 0442790..60032f2 100644 --- a/src/main/scala/vexriscv/demo/FormalSimple.scala +++ b/src/main/scala/vexriscv/demo/FormalSimple.scala @@ -13,14 +13,15 @@ object FormalSimple extends App{ plugins = List( new FormalPlugin, new HaltOnExceptionPlugin, - new PcManagerSimplePlugin( - resetVector = 0x00000000l, - relaxedPcCalculation = false - ), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false + resetVector = 0x00000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = false, + catchAddressMisaligned = false, + compressedGen = false ), + new DBusSimplePlugin( catchAddressMisaligned = true, catchAccessFault = false diff --git a/src/main/scala/vexriscv/demo/GenCustomCsr.scala b/src/main/scala/vexriscv/demo/GenCustomCsr.scala index d0f0463..e0d794e 100644 --- a/src/main/scala/vexriscv/demo/GenCustomCsr.scala +++ b/src/main/scala/vexriscv/demo/GenCustomCsr.scala @@ -16,13 +16,13 @@ object GenCustomCsr extends App{ new CustomCsrDemoPlugin, new CsrPlugin(CsrPluginConfig.small), new CustomCsrDemoGpioPlugin, - new PcManagerSimplePlugin( - resetVector = 0x00000000l, - relaxedPcCalculation = false - ), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false + resetVector = 0x00000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = false, + catchAddressMisaligned = false, + compressedGen = false ), new DBusSimplePlugin( catchAddressMisaligned = false, diff --git a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala index ba19991..6a9823f 100644 --- a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala +++ b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala @@ -12,13 +12,13 @@ object GenCustomSimdAdd extends App{ config = VexRiscvConfig( plugins = List( new SimdAddPlugin, - new PcManagerSimplePlugin( - resetVector = 0x00000000l, - relaxedPcCalculation = false - ), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false + resetVector = 0x00000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = false, + catchAddressMisaligned = false, + compressedGen = false ), new DBusSimplePlugin( catchAddressMisaligned = false, diff --git a/src/main/scala/vexriscv/demo/GenDeterministicVex.scala b/src/main/scala/vexriscv/demo/GenDeterministicVex.scala index f194092..27413f8 100644 --- a/src/main/scala/vexriscv/demo/GenDeterministicVex.scala +++ b/src/main/scala/vexriscv/demo/GenDeterministicVex.scala @@ -11,13 +11,13 @@ object GenDeterministicVex extends App{ def cpu() = new VexRiscv( config = VexRiscvConfig( plugins = List( - new PcManagerSimplePlugin( - resetVector = 0x80000000l, - relaxedPcCalculation = false - ), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = true + resetVector = 0x80000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = true, + catchAddressMisaligned = true, + compressedGen = false ), new DBusSimplePlugin( catchAddressMisaligned = true, diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala index 923540b..6d7aa2b 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala @@ -12,13 +12,13 @@ object GenFullNoMmuNoCache extends App{ def cpu() = new VexRiscv( config = VexRiscvConfig( plugins = List( - new PcManagerSimplePlugin( - resetVector = 0x00000000l, - relaxedPcCalculation = false - ), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false + resetVector = 0x00000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = false, + catchAddressMisaligned = false, + compressedGen = false ), new DBusSimplePlugin( catchAddressMisaligned = false, diff --git a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala index 1171710..75bc422 100644 --- a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala +++ b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala @@ -12,13 +12,13 @@ object GenNoCacheNoMmuMaxPerf extends App{ def cpu() = new VexRiscv( config = VexRiscvConfig( plugins = List( - new PcManagerSimplePlugin( - resetVector = 0x80000000l, - relaxedPcCalculation = false - ), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = true + resetVector = 0x80000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = true, + catchAddressMisaligned = true, + compressedGen = false ), new DBusSimplePlugin( catchAddressMisaligned = true, diff --git a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala index 8a45aa3..94fec23 100644 --- a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala @@ -11,13 +11,13 @@ object GenSmallAndProductive extends App{ def cpu() = new VexRiscv( config = VexRiscvConfig( plugins = List( - new PcManagerSimplePlugin( - resetVector = 0x00000000l, - relaxedPcCalculation = false - ), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false + resetVector = 0x00000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = false, + catchAddressMisaligned = false, + compressedGen = false ), new DBusSimplePlugin( catchAddressMisaligned = false, diff --git a/src/main/scala/vexriscv/demo/GenSmallest.scala b/src/main/scala/vexriscv/demo/GenSmallest.scala index 6e86db9..40dd639 100644 --- a/src/main/scala/vexriscv/demo/GenSmallest.scala +++ b/src/main/scala/vexriscv/demo/GenSmallest.scala @@ -11,13 +11,13 @@ object GenSmallest extends App{ def cpu() = new VexRiscv( config = VexRiscvConfig( plugins = List( - new PcManagerSimplePlugin( - resetVector = 0x00000000l, - relaxedPcCalculation = false - ), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false + resetVector = 0x00000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = false, + catchAddressMisaligned = false, + compressedGen = false ), new DBusSimplePlugin( catchAddressMisaligned = false, diff --git a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala index e53e313..5f3e651 100644 --- a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala +++ b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala @@ -15,9 +15,14 @@ object GenSmallestNoCsr extends App{ // resetVector = 0x00000000l, // relaxedPcCalculation = false // ), + new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false + resetVector = 0x00000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = false, + catchAddressMisaligned = false, + compressedGen = false ), new DBusSimplePlugin( catchAddressMisaligned = false, diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index d63806e..055e94f 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -52,13 +52,13 @@ object MuraxConfig{ pipelineApbBridge = true, gpioWidth = 32, cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel - new PcManagerSimplePlugin( - resetVector = 0x80000000l, - relaxedPcCalculation = true - ), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false + resetVector = 0x80000000l, + relaxedPcCalculation = true, + prediction = NONE, + catchAccessFault = false, + catchAddressMisaligned = false, + compressedGen = false ), new DBusSimplePlugin( catchAddressMisaligned = false, diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala index cf98c60..3042c2e 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala @@ -26,10 +26,13 @@ object VexRiscvAvalonForSim{ //CPU configuration val cpuConfig = VexRiscvConfig( plugins = List( - new PcManagerSimplePlugin(0x00000000l, false), new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false + resetVector = 0x00000000l, + relaxedPcCalculation = false, + prediction = NONE, + catchAccessFault = false, + catchAddressMisaligned = false, + compressedGen = false ), new DBusSimplePlugin( catchAddressMisaligned = false, diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 12d3322..24a146e 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -102,30 +102,36 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste -class IBusSimplePlugin(interfaceKeepData : Boolean, + +class IBusSimplePlugin(resetVector : BigInt, + relaxedPcCalculation : Boolean, + prediction : BranchPrediction, catchAccessFault : Boolean, -// resetVector : BigInt, -// keepPcPlus4 : Boolean, -// decodePcGen : Boolean, + catchAddressMisaligned : Boolean, + keepPcPlus4 : Boolean = false, + compressedGen : Boolean = false, + busLatencyMin : Int = 1, pendingMax : Int = 7, - relaxedBusCmdValid : Boolean = false) extends IBusFetcherImpl( + injectorStage : Boolean = true, + relaxedBusCmdValid : Boolean = false + ) extends IBusFetcherImpl( catchAccessFault = catchAccessFault, - resetVector = BigInt(0x80000000l), - keepPcPlus4 = false, - decodePcGen = false, - compressedGen = false, - cmdToRspStageCount = 1, + resetVector = resetVector, + keepPcPlus4 = keepPcPlus4, + decodePcGen = compressedGen, + compressedGen = compressedGen, + cmdToRspStageCount = busLatencyMin, injectorReadyCutGen = false, - relaxedPcCalculation = true, - prediction = NONE, - catchAddressMisaligned = false, - injectorStage = true){ + relaxedPcCalculation = relaxedPcCalculation, + prediction = prediction, + catchAddressMisaligned = catchAddressMisaligned, + injectorStage = injectorStage){ var iBus : IBusSimpleBus = null var decodeExceptionPort : Flow[ExceptionCause] = null override def setup(pipeline: VexRiscv): Unit = { super.setup(pipeline) - iBus = master(IBusSimpleBus(interfaceKeepData)).setName("iBus") + iBus = master(IBusSimpleBus(false)).setName("iBus") if(catchAccessFault) { val exceptionService = pipeline.service(classOf[ExceptionService])