From df7ac05db988b3c3bbbf80b782d5b1f2a2c1a0c9 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 23 Jun 2021 11:48:38 +0200 Subject: [PATCH] Update 2.13 compatibility --- build.sbt | 4 ++-- src/main/scala/vexriscv/demo/Briey.scala | 8 ++++---- src/main/scala/vexriscv/demo/Murax.scala | 4 ++-- src/main/scala/vexriscv/demo/MuraxUtiles.scala | 2 +- src/test/scala/vexriscv/DhrystoneBench.scala | 4 ++-- .../scala/vexriscv/TestIndividualFeatures.scala | 14 ++++++++------ src/test/scala/vexriscv/ip/fpu/FpuTest.scala | 5 +++-- 7 files changed, 22 insertions(+), 19 deletions(-) diff --git a/build.sbt b/build.sbt index e4cf8d6..0b0f302 100644 --- a/build.sbt +++ b/build.sbt @@ -10,8 +10,8 @@ lazy val root = (project in file(".")). scalacOptions += s"-Xplugin:${new File(baseDirectory.value + s"/../SpinalHDL/idslplugin/target/scala-2.11/spinalhdl-idsl-plugin_2.11-$spinalVersion.jar")}", scalacOptions += s"-Xplugin-require:idsl-plugin", libraryDependencies ++= Seq( - "org.scalatest" % "scalatest_2.11" % "2.2.1", - "org.yaml" % "snakeyaml" % "1.8" + "org.scalatest" %% "scalatest" % "3.2.5", + "org.yaml" % "snakeyaml" % "1.8" ), name := "VexRiscv" ).dependsOn(spinalHdlIdslPlugin, spinalHdlSim,spinalHdlCore,spinalHdlLib) diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala index dd794a6..76c688d 100644 --- a/src/main/scala/vexriscv/demo/Briey.scala +++ b/src/main/scala/vexriscv/demo/Briey.scala @@ -174,9 +174,9 @@ class Briey(config: BrieyConfig) extends Component{ val io = new Bundle{ //Clocks / reset - val asyncReset = in Bool - val axiClk = in Bool - val vgaClk = in Bool + val asyncReset = in Bool() + val axiClk = in Bool() + val vgaClk = in Bool() //Main components IO val jtag = slave(Jtag()) @@ -188,7 +188,7 @@ class Briey(config: BrieyConfig) extends Component{ val uart = master(Uart()) val vga = master(Vga(vgaRgbConfig)) val timerExternal = in(PinsecTimerCtrlExternal()) - val coreInterrupt = in Bool + val coreInterrupt = in Bool() } val resetCtrlClockDomain = ClockDomain( diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 82bceb3..05c8e00 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -157,8 +157,8 @@ case class Murax(config : MuraxConfig) extends Component{ val io = new Bundle { //Clocks / reset - val asyncReset = in Bool - val mainClk = in Bool + val asyncReset = in Bool() + val mainClk = in Bool() //Main components IO val jtag = slave(Jtag()) diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala index 1e22157..22bc438 100644 --- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala +++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala @@ -142,7 +142,7 @@ class MuraxApb3Timer extends Component{ addressWidth = 8, dataWidth = 32 )) - val interrupt = out Bool + val interrupt = out Bool() } val prescaler = Prescaler(16) diff --git a/src/test/scala/vexriscv/DhrystoneBench.scala b/src/test/scala/vexriscv/DhrystoneBench.scala index a98377c..48d1b67 100644 --- a/src/test/scala/vexriscv/DhrystoneBench.scala +++ b/src/test/scala/vexriscv/DhrystoneBench.scala @@ -2,13 +2,13 @@ package vexriscv import java.io.File -import org.scalatest.FunSuite +import org.scalatest.funsuite.AnyFunSuite import spinal.core.SpinalVerilog import vexriscv.demo._ import scala.sys.process._ -class DhrystoneBench extends FunSuite { +class DhrystoneBench extends AnyFunSuite { def doCmd(cmd: String): String = { val stdOut = new StringBuilder() class Logger extends ProcessLogger { diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala index 71c6697..bd5acb0 100644 --- a/src/test/scala/vexriscv/TestIndividualFeatures.scala +++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala @@ -3,7 +3,9 @@ package vexriscv import java.io.{File, OutputStream} import java.util.concurrent.{ForkJoinPool, TimeUnit} import org.apache.commons.io.FileUtils -import org.scalatest.{BeforeAndAfterAll, FunSuite, ParallelTestExecution, Tag, Transformer} +import org.scalatest.{BeforeAndAfterAll, ParallelTestExecution, Tag, Transformer} +import org.scalatest.funsuite.AnyFunSuite + import spinal.core._ import spinal.lib.DoCmd import vexriscv.demo._ @@ -617,7 +619,7 @@ object PlayFuture extends App{ Thread.sleep(8000) } -class MultithreadedFunSuite(threadCount : Int) extends FunSuite { +class MultithreadedFunSuite(threadCount : Int) extends AnyFunSuite { val finalThreadCount = if(threadCount > 0) threadCount else { new oshi.SystemInfo().getHardware.getProcessor.getLogicalProcessorCount } @@ -650,7 +652,7 @@ class MultithreadedFunSuite(threadCount : Int) extends FunSuite { } } - override protected def test(testName: String, testTags: Tag*)(testFun: => Unit) { + def testMp(testName: String, testTags: Tag*)(testFun: => Unit) { val job = new Job(testFun) super.test(testName, testTags :_*)(job.join()) } @@ -662,7 +664,7 @@ class MultithreadedFunSuite(threadCount : Int) extends FunSuite { class FunTestPara extends MultithreadedFunSuite(3){ def createTest(name : String): Unit ={ - test(name){ + testMp(name){ for(i <- 0 to 4) { println(s"$name $i") Thread.sleep(500) @@ -745,7 +747,7 @@ class TestIndividualFeatures extends MultithreadedFunSuite(sys.env.getOrElse("VE stdOut.toString() } - test(prefix + name) { + testMp(prefix + name) { println("START TEST " + prefix + name) //Cleanup @@ -787,7 +789,7 @@ class TestIndividualFeatures extends MultithreadedFunSuite(sys.env.getOrElse("VE val rand = new Random(seed) - test("Info"){ + testMp("Info"){ println(s"MAIN_SEED=$seed") } println(s"Seed=$seed") diff --git a/src/test/scala/vexriscv/ip/fpu/FpuTest.scala b/src/test/scala/vexriscv/ip/fpu/FpuTest.scala index 280a5fe..11182ac 100644 --- a/src/test/scala/vexriscv/ip/fpu/FpuTest.scala +++ b/src/test/scala/vexriscv/ip/fpu/FpuTest.scala @@ -5,7 +5,7 @@ import java.lang import java.util.Scanner import org.apache.commons.io.FileUtils -import org.scalatest.FunSuite +import org.scalatest.funsuite.AnyFunSuite import spinal.core.SpinalEnumElement import spinal.core.sim._ import spinal.core._ @@ -18,9 +18,10 @@ import scala.collection.mutable import scala.collection.mutable.ArrayBuffer import scala.sys.process.ProcessLogger import scala.util.Random +import org.scalatest.funsuite.AnyFunSuite //TODO Warning DataCache write aggregation will disable itself -class FpuTest extends FunSuite{ +class FpuTest extends AnyFunSuite{ val b2f = lang.Float.intBitsToFloat(_) val b2d = lang.Double.longBitsToDouble(_)