From e0ae46e79491383e1c7caa3e438b4b504d229f86 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 16 Nov 2020 12:37:48 +0100 Subject: [PATCH] Fix Csr ReadWrite interration with DBusCachedPlugin execute halt # Conflicts: # src/main/scala/vexriscv/plugin/CsrPlugin.scala --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 0cb6a79..545c5fe 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -1010,18 +1010,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep val readData = Bits(32 bits) val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) - val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && readDataRegValid - val readEnable = readInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && !readDataRegValid - //arbitration.isStuckByOthers, in case of the hazardPlugin is in the executeStage - - -// def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT -// val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck) -// val writeDataEnable = input(INSTRUCTION)(13) ? writeSrc | B"xFFFFFFFF" -// val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux( -// False -> writeSrc, -// True -> Mux(input(INSTRUCTION)(12), ~writeSrc, writeSrc) -// ) + val writeEnable = writeInstruction && !arbitration.isStuck + val readEnable = readInstruction && !arbitration.isStuck val readToWriteData = CombInit(readData) val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux(