diff --git a/build.sbt b/build.sbt
index 3c2aae6..6b24b15 100644
--- a/build.sbt
+++ b/build.sbt
@@ -1,25 +1,3 @@
-//name := "VexRiscv"
-//
-//organization := "com.github.spinalhdl"
-//
-//version := "1.0.0"
-//
-//scalaVersion := "2.11.6"
-//
-//EclipseKeys.withSource := true
-//
-//libraryDependencies ++= Seq(
-//  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.1",
-//  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.1",
-//  "org.scalatest" % "scalatest_2.11" % "2.2.1",
-//  "org.yaml" % "snakeyaml" % "1.8"
-//)
-//
-//
-//
-//addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
-//scalacOptions += "-P:continuations:enable"
-//fork := true
 
 lazy val root = (project in file(".")).
   settings(
@@ -29,16 +7,16 @@ lazy val root = (project in file(".")).
       version      := "1.0.0"
     )),
     libraryDependencies ++= Seq(
-        "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.3.1",
-        "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.3.1",
+//        "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.3.1",
+//        "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.3.1",
         "org.scalatest" % "scalatest_2.11" % "2.2.1",
         "org.yaml" % "snakeyaml" % "1.8"
     ),
     name := "VexRiscv"
-  )//.dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib)
-//lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "SpinalHDL-sim")
-//lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "SpinalHDL-core")
-//lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "SpinalHDL-lib")
+  ).dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib)
+lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "sim")
+lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "core")
+lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "lib")
 
 
 fork := true
\ No newline at end of file
diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala
index ca76f8b..31c7460 100644
--- a/src/main/scala/vexriscv/demo/Briey.scala
+++ b/src/main/scala/vexriscv/demo/Briey.scala
@@ -258,10 +258,12 @@ class Briey(config: BrieyConfig) extends Component{
     )
 
     val gpioACtrl = Apb3Gpio(
-      gpioWidth = 32
+      gpioWidth = 32,
+      withReadSync = true
     )
     val gpioBCtrl = Apb3Gpio(
-      gpioWidth = 32
+      gpioWidth = 32,
+      withReadSync = true
     )
     val timerCtrl = PinsecTimerCtrl()
 
diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala
index 8a06cbc..d78beeb 100644
--- a/src/main/scala/vexriscv/demo/Murax.scala
+++ b/src/main/scala/vexriscv/demo/Murax.scala
@@ -276,7 +276,7 @@ case class Murax(config : MuraxConfig) extends Component{
 
     //******** APB peripherals *********
     val apbMapping = ArrayBuffer[(Apb3, SizeMapping)]()
-    val gpioACtrl = Apb3Gpio(gpioWidth = gpioWidth)
+    val gpioACtrl = Apb3Gpio(gpioWidth = gpioWidth, withReadSync = true)
     io.gpioA <> gpioACtrl.io.gpio
     apbMapping += gpioACtrl.io.apb -> (0x00000, 4 kB)
 
diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index fb383e5..ab59360 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -271,6 +271,20 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
   val csrMapping = new CsrMapping()
 
 
+
+  case class InterruptSource(var cond : Bool, id : Int)
+  case class InterruptPrivilege(privilege : Int){
+    var privilegeCond : Bool = null
+    val sources = ArrayBuffer[InterruptSource]()
+  }
+
+  def getInterruptPrivilege(privilege : Int) = customInterrupts.getOrElseUpdate(privilege, InterruptPrivilege(privilege))
+  var customInterrupts = mutable.LinkedHashMap[Int, InterruptPrivilege]()
+  def addInterrupt(cond : Bool, id : Int, privilege : Int): Unit = {
+    getInterruptPrivilege(privilege).sources += InterruptSource(cond, id)
+  }
+  def createInterrupt(id : Int, privilege : Int) : Bool = { val ret = Bool(); addInterrupt(ret, id, privilege); ret}
+
   override def r(csrAddress: Int, bitOffset: Int, that: Data): Unit = csrMapping.r(csrAddress, bitOffset, that)
   override def w(csrAddress: Int, bitOffset: Int, that: Data): Unit = csrMapping.w(csrAddress, bitOffset, that)
   override def onWrite(csrAddress: Int)(body: => Unit): Unit = csrMapping.onWrite(csrAddress)(body)
@@ -338,6 +352,11 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
 
     allowInterrupts = True
     allowException = True
+
+    for (privilege <- customInterrupts.values;
+         source <- privilege.sources){
+      source.cond = source.cond.pull()
+    }
   }
 
   def inhibateInterrupts() : Unit = allowInterrupts := False
@@ -500,20 +519,22 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
         minstret := minstret + 1
       }
 
-      case class InterruptSource(cond : Bool, id : Int)
-      case class InterruptPrivilege(privilege : Int, privilegeCond : Bool, sources : ArrayBuffer[InterruptSource])
-      val interruptModel = ArrayBuffer[InterruptPrivilege]()
-      if(supervisorGen) interruptModel += InterruptPrivilege(1, sstatus.SIE && privilege <= "01", ArrayBuffer(
-        InterruptSource(sip.STIP && sie.STIE,  5),
-        InterruptSource(sip.SSIP && sie.SSIE,  1),
-        InterruptSource(sip.SEIP && sie.SEIE,  9)
-      ))
 
-      interruptModel += InterruptPrivilege(3, mstatus.MIE , ArrayBuffer(
+      if(supervisorGen) {
+        getInterruptPrivilege(1).privilegeCond = sstatus.SIE && privilege <= "01"
+        getInterruptPrivilege(1).sources ++= List(
+          InterruptSource(sip.STIP && sie.STIE,  5),
+          InterruptSource(sip.SSIP && sie.SSIE,  1),
+          InterruptSource(sip.SEIP && sie.SEIE,  9)
+        )
+      }
+
+      getInterruptPrivilege(3).privilegeCond = mstatus.MIE
+      getInterruptPrivilege(3).sources ++= List(
         InterruptSource(mip.MTIP && mie.MTIE,  7),
         InterruptSource(mip.MSIP && mie.MSIE,  3),
         InterruptSource(mip.MEIP && mie.MEIE, 11)
-      ))
+      )
 
       case class DelegatorModel(value : Bits, source : Int, target : Int)
 //      def solveDelegators(delegators : Seq[DelegatorModel], id : Int, lowerBound : Int): UInt = {
@@ -621,7 +642,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
       val interrupt = False
       val interruptCode = UInt(4 bits).assignDontCare().addTag(Verilator.public)
       val interruptDelegatorHit = interruptDelegators.map(d => (d -> False)).toMap
-      for(model <- interruptModel){
+      for(model <- customInterrupts.values.toSeq.sortBy(_.privilege)){
         when(model.privilegeCond){
           when(model.sources.map(_.cond).orR){
             interrupt := True