From e0cd9a6e067e6e42f385a87af9f439f8314290f0 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Mon, 17 Feb 2020 22:45:34 +0100
Subject: [PATCH] clean iBusRsp redo

---
 src/main/scala/vexriscv/plugin/Fetcher.scala     | 16 ++++++----------
 .../scala/vexriscv/plugin/IBusCachedPlugin.scala |  8 +++-----
 .../scala/vexriscv/plugin/IBusSimplePlugin.scala | 10 ++++------
 3 files changed, 13 insertions(+), 21 deletions(-)

diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala
index 255efc2..f933ab9 100644
--- a/src/main/scala/vexriscv/plugin/Fetcher.scala
+++ b/src/main/scala/vexriscv/plugin/Fetcher.scala
@@ -76,9 +76,6 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
       }
       case DYNAMIC_TARGET => {
         fetchPrediction = pipeline.service(classOf[PredictionInterface]).askFetchPrediction()
-        if(compressedGen){
-          dynamicTargetFailureCorrection = createJumpInterface(pipeline.decode)
-        }
       }
     }
 
@@ -205,7 +202,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
 
 
     val iBusRsp = new Area {
-      val fetchFlush = False
+      val redoFetch = False
       val stages = Array.fill(cmdToRspStageCount + 1)(new Bundle {
         val input = Stream(UInt(32 bits))
         val output = Stream(UInt(32 bits))
@@ -219,10 +216,13 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
         s.output << s.input.haltWhen(s.halt)
       }
 
+      fetchPc.redo.valid := redoFetch
+      fetchPc.redo.payload := stages.last.input.payload
+
       stages.head.flush :=  False //getFlushAt(IBUS_RSP, stages.head == stages.last) || fetchFlush
       for((s,sNext) <- (stages, stages.tail).zipped) {
         val discardInputOnFlush = s != stages.head
-        sNext.flush := getFlushAt(IBUS_RSP, sNext == stages.last) || fetchFlush
+        sNext.flush := getFlushAt(IBUS_RSP, sNext == stages.last) || redoFetch
         if(s == stages.head && pcRegReusedForSecondStage) {
           sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(sNext.flush, false, collapsBubble = false, flushInput = s.flush))
           sNext.input.payload := fetchPc.pcReg
@@ -582,16 +582,12 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
           val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready)
           val bypassFailure = if(!injectorStage) False else decompressorFailure && !injector.decodeInput.valid
 
-          dynamicTargetFailureCorrection.valid := False
-          dynamicTargetFailureCorrection.payload := decode.input(PC)
           when(injectorFailure || bypassFailure){
             historyWrite.valid := True
             historyWrite.address := (decode.input(PC) >> 2).resized
             historyWrite.data.branchWish := 0
 
-            decode.arbitration.isValid := False
-            decode.arbitration.flushNext := True
-            dynamicTargetFailureCorrection.valid := True
+            iBusRsp.redoFetch := True
           }
         })
       }
diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
index 4a63364..f018bb3 100644
--- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
@@ -59,7 +59,6 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
   var iBus  : InstructionCacheMemBus = null
   var mmuBus : MemoryTranslatorBus = null
   var privilegeService : PrivilegeService = null
-  var redoBranch : Flow[UInt] = null
   var decodeExceptionPort : Flow[ExceptionCause] = null
   val tightlyCoupledPorts = ArrayBuffer[TightlyCoupledPort]()
   def tightlyGen = tightlyCoupledPorts.nonEmpty
@@ -235,10 +234,9 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
           decodeExceptionPort.code := 1
         }
 
-
-        fetchPc.redo.valid := redoFetch
-        fetchPc.redo.payload := iBusRsp.stages.last.input.payload
-        iBusRsp.fetchFlush setWhen(redoFetch)
+        when(redoFetch) {
+          iBusRsp.redoFetch := True
+        }
 
 
         cacheRspArbitration.halt setWhen (issueDetected || iBusRspOutputHalt)
diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
index c14ac30..319634d 100644
--- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
@@ -369,18 +369,16 @@ class IBusSimplePlugin(    resetVector : BigInt,
 
         val join = Stream(FetchRsp())
         val exceptionDetected = False
-        val redoRequired = False
         join.valid := stages.last.output.valid && rspBufferOutput.valid
         join.payload := fetchRsp
         stages.last.output.ready := stages.last.output.valid ? join.fire | join.ready
         rspBufferOutput.ready := join.fire
-        output << join.haltWhen(exceptionDetected || redoRequired)
+        output << join.haltWhen(exceptionDetected)
 
         if(memoryTranslatorPortConfig != null){
-          redoRequired setWhen( stages.last.input.valid && mmu.joinCtx.refilling)
-          fetchPc.redo.valid := redoRequired && iBusRsp.readyForError
-          fetchPc.redo.payload := decode.input(PC)
-          iBusRsp.fetchFlush setWhen(fetchPc.redo.valid)
+          when(stages.last.input.valid && mmu.joinCtx.refilling) {
+            iBusRsp.redoFetch := True
+          }
         }