From e1795e59d5660f627bfde5d13a1622866de8495f Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sat, 21 Sep 2019 13:00:54 +0200 Subject: [PATCH] Enable RF bypass on MUL DIV with pipeline wihout writeback/memory stages --- src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala | 2 +- src/main/scala/vexriscv/plugin/MulSimplePlugin.scala | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala index 11af4ab..1bd8fb4 100644 --- a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala @@ -31,7 +31,7 @@ class MulDivIterativePlugin(genMul : Boolean = true, SRC1_CTRL -> Src1CtrlEnum.RS, SRC2_CTRL -> Src2CtrlEnum.RS, REGFILE_WRITE_VALID -> True, - BYPASSABLE_EXECUTE_STAGE -> False, + BYPASSABLE_EXECUTE_STAGE -> Bool(pipeline.stages.last == pipeline.execute), BYPASSABLE_MEMORY_STAGE -> True, RS1_USE -> True, RS2_USE -> True diff --git a/src/main/scala/vexriscv/plugin/MulSimplePlugin.scala b/src/main/scala/vexriscv/plugin/MulSimplePlugin.scala index 1be6da7..3b407e1 100644 --- a/src/main/scala/vexriscv/plugin/MulSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulSimplePlugin.scala @@ -19,8 +19,8 @@ class MulSimplePlugin extends Plugin[VexRiscv]{ SRC1_CTRL -> Src1CtrlEnum.RS, SRC2_CTRL -> Src2CtrlEnum.RS, REGFILE_WRITE_VALID -> True, - BYPASSABLE_EXECUTE_STAGE -> False, - BYPASSABLE_MEMORY_STAGE -> False, + BYPASSABLE_EXECUTE_STAGE -> Bool(pipeline.stages.last == pipeline.execute), + BYPASSABLE_MEMORY_STAGE -> Bool(pipeline.stages.last == pipeline.memory), RS1_USE -> True, RS2_USE -> True, IS_MUL -> True