diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
index b3d7f0f..9bd8d94 100644
--- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
+++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
@@ -65,12 +65,12 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
 
   val debugBmbAccessSource = Handle[BmbAccessCapabilities]
   val debugBmbAccessRequirements = Handle[BmbAccessParameter]
-  def enableDebugBmb(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.rework{
-    this.debugClockDomain.load(debugCd.outputClockDomain)
+  def enableDebugBmb(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.on{
+    this.debugClockDomain.load(debugCd)
     val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
     debugAskReset.loadNothing()
     withDebug.load(DEBUG_BMB)
-    val slaveModel = debugCd.outputClockDomain on interconnectSmp.addSlave(
+    val slaveModel = debugCd on interconnectSmp.addSlave(
       accessSource = debugBmbAccessSource,
       accessCapabilities = debugBmbAccessSource.derivate(DebugExtensionBus.getBmbAccessParameter(_)),
       accessRequirements = debugBmbAccessRequirements,
@@ -81,7 +81,6 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
     if(debugMaster != null) interconnectSmp.addConnection(debugMaster.bus, debugBmb)
   }
 
-
   val jtag = Handle(withDebug.get == DEBUG_JTAG generate slave(Jtag()))
   val jtagInstructionCtrl = withDebug.produce(withDebug.get == DEBUG_JTAG_CTRL generate JtagTapInstructionCtrl())
   val debugBus = withDebug.produce(withDebug.get == DEBUG_BUS generate DebugExtensionBus())
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
index 58ab5ee..8c9df5f 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -76,7 +76,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
       cpu.dBus -> List(dBusCoherent.bmb)
     )
     cpu.enableDebugBmb(
-      debugCd = debugCd,
+      debugCd = debugCd.outputClockDomain,
       resetCd = systemCd,
       mapping = SizeMapping(cpuId*0x1000, 0x1000)
     )