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VexRiscv
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Handle ClockDomain improvements

This commit is contained in:
Dolu1990 2021-03-16 14:46:30 +01:00
parent 02c572b6f1
commit e23687c45d
2 changed files with 4 additions and 5 deletions
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7
src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
View File

@ -65,12 +65,12 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
val debugBmbAccessSource = Handle[BmbAccessCapabilities] val debugBmbAccessSource = Handle[BmbAccessCapabilities]
val debugBmbAccessRequirements = Handle[BmbAccessParameter] val debugBmbAccessRequirements = Handle[BmbAccessParameter]
def enableDebugBmb(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.rework{ def enableDebugBmb(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.on{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
withDebug.load(DEBUG_BMB) withDebug.load(DEBUG_BMB)
val slaveModel = debugCd.outputClockDomain on interconnectSmp.addSlave( val slaveModel = debugCd on interconnectSmp.addSlave(
accessSource = debugBmbAccessSource, accessSource = debugBmbAccessSource,
accessCapabilities = debugBmbAccessSource.derivate(DebugExtensionBus.getBmbAccessParameter(_)), accessCapabilities = debugBmbAccessSource.derivate(DebugExtensionBus.getBmbAccessParameter(_)),
accessRequirements = debugBmbAccessRequirements, accessRequirements = debugBmbAccessRequirements,
@ -81,7 +81,6 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
if(debugMaster != null) interconnectSmp.addConnection(debugMaster.bus, debugBmb) if(debugMaster != null) interconnectSmp.addConnection(debugMaster.bus, debugBmb)
} }
val jtag = Handle(withDebug.get == DEBUG_JTAG generate slave(Jtag())) val jtag = Handle(withDebug.get == DEBUG_JTAG generate slave(Jtag()))
val jtagInstructionCtrl = withDebug.produce(withDebug.get == DEBUG_JTAG_CTRL generate JtagTapInstructionCtrl()) val jtagInstructionCtrl = withDebug.produce(withDebug.get == DEBUG_JTAG_CTRL generate JtagTapInstructionCtrl())
val debugBus = withDebug.produce(withDebug.get == DEBUG_BUS generate DebugExtensionBus()) val debugBus = withDebug.produce(withDebug.get == DEBUG_BUS generate DebugExtensionBus())

2
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
View File

@ -76,7 +76,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
cpu.dBus -> List(dBusCoherent.bmb) cpu.dBus -> List(dBusCoherent.bmb)
) )
cpu.enableDebugBmb( cpu.enableDebugBmb(
debugCd = debugCd, debugCd = debugCd.outputClockDomain,
resetCd = systemCd, resetCd = systemCd,
mapping = SizeMapping(cpuId*0x1000, 0x1000) mapping = SizeMapping(cpuId*0x1000, 0x1000)
) )