From e25dfb4fbf1d11ab61710026797120c9034b9f86 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Mon, 9 Dec 2019 22:23:07 +0100 Subject: [PATCH] CsrPlugin now make SATP write rescheduling the next instruction --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 0c9b7dc..5cd161b 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -334,6 +334,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep var exceptionPendings : Vec[Bool] = null override def isExceptionPending(stage : Stage): Bool = exceptionPendings(pipeline.stages.indexOf(stage)) + var redoInterface : Flow[UInt] = null var jumpInterface : Flow[UInt] = null var timerInterrupt, externalInterrupt, softwareInterrupt : Bool = null var externalInterruptS : Bool = null @@ -430,6 +431,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep jumpInterface.valid := False jumpInterface.payload.assignDontCare() + + if(supervisorGen) { + redoInterface = pcManagerService.createJumpInterface(pipeline.execute) + redoInterface.valid := False + redoInterface.payload.assignDontCare() + } + exceptionPendings = Vec(Bool, pipeline.stages.length) timerInterrupt = in Bool() setName("timerInterrupt") externalInterrupt = in Bool() setName("externalInterrupt") @@ -619,6 +627,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep scauseAccess(CSR.SCAUSE, xlen-1 -> scause.interrupt, 0 -> scause.exceptionCode) sbadaddrAccess(CSR.SBADADDR, stval) satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN) + + + if(supervisorGen) onWrite(CSR.SATP){ + execute.arbitration.flushNext := True + redoInterface.valid := True + redoInterface.payload := execute.input(PC) + 4 + } } }