From e3411012d77dc3b33e2cf85403b3e1a81c4a4682 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Tue, 1 Aug 2017 00:01:27 +0200 Subject: [PATCH] Add links to demo software --- README.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index c55b34f..416f483 100644 --- a/README.md +++ b/README.md @@ -214,9 +214,9 @@ To connect OpenOCD (https://github.com/SpinalHDL/openocd_riscv) to the simulatio ```sh src/openocd -f tcl/interface/jtag_tcp.cfg -c "set BRIEY_CPU0_YAML /home/spinalvm/Spinal/VexRiscv/cpu0.yaml" -f tcl/target/briey.cfg -``` +```ยง -You can find multiples software examples and demo there : https://github.com/SpinalHDL/BrieySoftware +You can find multiples software examples and demo there : https://github.com/SpinalHDL/VexRiscvSocSoftware/tree/master/projects/briey You can find some FPGA project which instantiate the Briey SoC there (DE1-SoC, DE0-Nano): https://drive.google.com/drive/folders/0B-CqLXDTaMbKZGdJZlZ5THAxRTQ?usp=sharing @@ -266,6 +266,8 @@ To connect OpenOCD (https://github.com/SpinalHDL/openocd_riscv) to the simulatio src/openocd -f tcl/interface/jtag_tcp.cfg -c "set MURAX_CPU0_YAML /home/spinalvm/Spinal/VexRiscv/cpu0.yaml" -f tcl/target/murax.cfg ``` +You can find multiples software examples and demo there : https://github.com/SpinalHDL/VexRiscvSocSoftware/tree/master/projects/murax + There is some measurements of Murax SoC timings and area for the 0.37 DMIPS/Mhz SoC version : ```