From e9e7cf9e7a6c049fdc46d3321121267e1444906b Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sat, 24 Jun 2017 14:09:12 +0200 Subject: [PATCH] Add briey tracing Better debugPlugin implementation Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing) Add SingleInstructionLimiterPlugin for debug purposes --- .../VexRiscv/Plugin/DBusSimplePlugin.scala | 10 +- .../scala/VexRiscv/Plugin/DebugPlugin.scala | 6 +- .../VexRiscv/Plugin/IBusSimplePlugin.scala | 6 +- .../SingleInstructionLimiterPlugin.scala | 15 ++ src/main/scala/VexRiscv/VexRiscv.scala | 1 + src/test/cpp/briey/main.cpp | 36 +++++ src/test/cpp/briey/makefile | 10 ++ src/test/cpp/briey/wip.gtkw | 148 ++++++++---------- src/test/cpp/regression/fail.gtkw | 57 ++++--- src/test/cpp/regression/main.cpp | 10 +- 10 files changed, 174 insertions(+), 125 deletions(-) create mode 100644 src/main/scala/VexRiscv/Plugin/SingleInstructionLimiterPlugin.scala diff --git a/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala b/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala index a811eb3..5746ea4 100644 --- a/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala @@ -85,11 +85,11 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ //TODO remove val axi2 = Axi4Shared(DBusSimpleBus.getAxi4Config()) -// axi.arw >/-> axi2.arw -// axi.w >/-> axi2.w -// axi.r <-/< axi2.r -// axi.b <-/< axi2.b - axi2 << axi + axi.arw >-> axi2.arw + axi.w >> axi2.w + axi.r << axi2.r + axi.b << axi2.b +// axi2 << axi axi2 } } diff --git a/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala b/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala index c9ec045..90b42ea 100644 --- a/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala @@ -93,6 +93,7 @@ class DebugPlugin(debugClockDomain : ClockDomain) extends Plugin[VexRiscv] { val insertDecodeInstruction = False val firstCycle = RegNext(False) setWhen (io.bus.cmd.ready) + val secondCycle = RegNext(firstCycle) val resetIt = RegInit(False) val haltIt = RegInit(False) val stepIt = RegInit(False) @@ -120,10 +121,9 @@ class DebugPlugin(debugClockDomain : ClockDomain) extends Plugin[VexRiscv] { is(1) { when(io.bus.cmd.wr) { insertDecodeInstruction := True - val injectedInstructionSent = RegNext(decode.arbitration.isFiring) init (False) - decode.arbitration.haltIt setWhen (!injectedInstructionSent && !RegNext(decode.arbitration.isValid).init(False)) decode.arbitration.isValid setWhen (firstCycle) - io.bus.cmd.ready := injectedInstructionSent + decode.arbitration.haltIt setWhen (secondCycle) + io.bus.cmd.ready := !(firstCycle || secondCycle || isPipActive) } } } diff --git a/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala b/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala index 0fcf68f..5ea335a 100644 --- a/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala +++ b/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala @@ -63,9 +63,9 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste //TODO remove val axi2 = Axi4ReadOnly(IBusSimpleBus.getAxi4Config()) -// axi.ar >/-> axi2.ar -// axi.r <-/< axi2.r - axi2 << axi + axi.ar >-> axi2.ar + axi.r << axi2.r +// axi2 << axi axi2 } } diff --git a/src/main/scala/VexRiscv/Plugin/SingleInstructionLimiterPlugin.scala b/src/main/scala/VexRiscv/Plugin/SingleInstructionLimiterPlugin.scala new file mode 100644 index 0000000..62208fb --- /dev/null +++ b/src/main/scala/VexRiscv/Plugin/SingleInstructionLimiterPlugin.scala @@ -0,0 +1,15 @@ +package VexRiscv.Plugin + +import VexRiscv._ +import spinal.core._ +import spinal.lib._ + + +class SingleInstructionLimiterPlugin() extends Plugin[VexRiscv] { + override def build(pipeline: VexRiscv): Unit = { + import pipeline._ + import pipeline.config._ + + prefetch.arbitration.haltIt.setWhen(List(fetch,decode,execute,memory,writeBack).map(_.arbitration.isValid).orR) + } +} diff --git a/src/main/scala/VexRiscv/VexRiscv.scala b/src/main/scala/VexRiscv/VexRiscv.scala index c24b52a..e667785 100644 --- a/src/main/scala/VexRiscv/VexRiscv.scala +++ b/src/main/scala/VexRiscv/VexRiscv.scala @@ -63,6 +63,7 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ writeBack.input(config.INSTRUCTION) keep() addAttribute(Verilator.public) writeBack.input(config.PC) keep() addAttribute(Verilator.public) writeBack.arbitration.isValid keep() addAttribute(Verilator.public) + writeBack.arbitration.isFiring keep() addAttribute(Verilator.public) } diff --git a/src/test/cpp/briey/main.cpp b/src/test/cpp/briey/main.cpp index e16339b..50ee92e 100644 --- a/src/test/cpp/briey/main.cpp +++ b/src/test/cpp/briey/main.cpp @@ -18,6 +18,7 @@ #include #include +#include "VBriey_VexRiscv.h" class SimElement{ @@ -725,6 +726,39 @@ public: } }; +class VexRiscvTracer : public SimElement{ +public: + VBriey_VexRiscv *cpu; + ofstream instructionTraces; + ofstream regTraces; + + VexRiscvTracer(VBriey_VexRiscv *cpu){ + this->cpu = cpu; +#ifdef TRACE_INSTRUCTION + instructionTraces.open ("instructionTrace.log"); +#endif +#ifdef TRACE_REG + regTraces.open ("regTraces.log"); +#endif + } + + + + virtual void preCycle(){ +#ifdef TRACE_INSTRUCTION + if(cpu->writeBack_arbitration_isFiring){ + instructionTraces << hex << setw(8) << cpu->writeBack_INSTRUCTION << endl; + } +#endif +#ifdef TRACE_REG + if(cpu->writeBack_RegFilePlugin_regFileWrite_valid == 1 && cpu->writeBack_RegFilePlugin_regFileWrite_payload_address != 0){ + regTraces << " PC " << hex << setw(8) << cpu->writeBack_PC << " : reg[" << dec << setw(2) << (uint32_t)cpu->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << hex << setw(8) << cpu->writeBack_RegFilePlugin_regFileWrite_payload_data << endl; + } + +#endif + } +}; + class BrieyWorkspace : public Workspace{ public: BrieyWorkspace() : Workspace("Briey"){ @@ -764,6 +798,8 @@ public: //speedFactor = 100e-6; //cout << "Simulation caped to " << timeToSec << " of real time"<< endl; #endif + + axiClk->add(new VexRiscvTracer(top->Briey->axi_core_cpu)); } diff --git a/src/test/cpp/briey/makefile b/src/test/cpp/briey/makefile index b8345fd..4b01c52 100644 --- a/src/test/cpp/briey/makefile +++ b/src/test/cpp/briey/makefile @@ -1,5 +1,7 @@ DEBUG?=no TRACE?=no +TRACE_INSTRUCTION?=no +TRACE_REG?=no PRINT_PERF?=no TRACE_START=0 ADDCFLAGS += -CFLAGS -pthread @@ -18,6 +20,14 @@ ifeq ($(PRINT_PERF),yes) ADDCFLAGS += -CFLAGS -DPRINT_PERF endif +ifeq ($(TRACE_INSTRUCTION),yes) + ADDCFLAGS += -CFLAGS -DTRACE_INSTRUCTION +endif + +ifeq ($(TRACE_REG),yes) + ADDCFLAGS += -CFLAGS -DTRACE_REG +endif + ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START} diff --git a/src/test/cpp/briey/wip.gtkw b/src/test/cpp/briey/wip.gtkw index 01409c3..5c7edeb 100644 --- a/src/test/cpp/briey/wip.gtkw +++ b/src/test/cpp/briey/wip.gtkw @@ -1,122 +1,102 @@ [*] [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI -[*] Sat Jun 17 11:02:57 2017 +[*] Fri Jun 23 12:04:47 2017 [*] -[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd" -[dumpfile_mtime] "Sat Jun 17 10:33:51 2017" -[dumpfile_size] 3778117632 +[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/fail/Briey.vcd" +[dumpfile_mtime] "Fri Jun 23 09:43:01 2017" +[dumpfile_size] 1976675834 [savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/wip.gtkw" -[timestart] 123264434700 +[timestart] 174298398700 [size] 1776 953 -[pos] -1 -1 -*-17.000000 123264547400 106440000000 123264547400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[pos] -1 -353 +*-17.000000 174298828600 174053720000 174335369100 174375180000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] TOP. [treeopen] TOP.Briey. +[treeopen] TOP.Briey.axi_core_cpu. [treeopen] TOP.Briey.axi_sdramCtrl. -[sst_width] 507 -[signals_width] 567 +[sst_width] 269 +[signals_width] 586 [sst_expanded] 1 [sst_vpaned_height] 503 @28 TOP.Briey.axi_core_cpu.DebugPlugin_haltIt TOP.Briey.axi_core_cpu.DebugPlugin_haltedByBreak -TOP.Briey.axi_core_cpu.DebugPlugin_isPipActive -TOP.Briey.axi_core_cpu.DebugPlugin_resetIt -TOP.Briey.axi_core_cpu.DebugPlugin_stepIt -TOP.Briey.axi_core_cpu.timerInterrupt -TOP.Briey.axi_timerCtrl.timerA.io_tick -TOP.Briey.axi_timerCtrl.timerA.io_clear -TOP.Briey.axi_timerCtrl.timerA.io_full -@22 -TOP.Briey.axi_timerCtrl.timerA.io_limit[31:0] -@28 -TOP.Briey.axi_timerCtrl.timerA.io_tick -@22 -TOP.Briey.axi_timerCtrl.timerA.io_value[31:0] -@28 -TOP.Briey.axi_timerCtrl.prescaler_1.io_clear -@22 -TOP.Briey.axi_timerCtrl.prescaler_1.io_limit[15:0] -@28 -TOP.Briey.axi_timerCtrl.prescaler_1.io_overflow -@22 -TOP.Briey.axi_timerCtrl.io_apb_PADDR[7:0] -@28 -TOP.Briey.axi_timerCtrl.io_apb_PENABLE -@22 -TOP.Briey.axi_timerCtrl.io_apb_PRDATA[31:0] -@28 -TOP.Briey.axi_timerCtrl.io_apb_PREADY -TOP.Briey.axi_timerCtrl.io_apb_PSEL[0] -@22 -TOP.Briey.axi_timerCtrl.io_apb_PWDATA[31:0] -@28 -TOP.Briey.axi_timerCtrl.io_apb_PWRITE -TOP.Briey.axi_timerCtrl.timerABridge_busClearing -TOP.Briey.axi_timerCtrl.timerABridge_clearsEnable[0] -TOP.Briey.axi_timerCtrl.timerABridge_ticksEnable[1:0] -TOP.Briey.axi_core_cpu.writeBack_arbitration_isValid @22 TOP.Briey.axi_core_cpu.writeBack_PC[31:0] +@28 +TOP.Briey.axi_core_cpu.writeBack_arbitration_isFiring +@22 +TOP.Briey.axi_core_cpu.writeBack_PC[31:0] +TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(12)[31:0] +TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(13)[31:0] +TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(15)[31:0] +@800022 +#{TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[0:4]} (4)TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] (3)TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] (2)TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] (1)TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] (0)TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] +@24 TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] +@1001200 +-group_end +@22 TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0] @28 TOP.Briey.axi_core_cpu.writeBack_RegFilePlugin_regFileWrite_valid @22 -TOP.Briey.axi_core_cpu.writeBack_INSTRUCTION[31:0] -TOP.Briey.axi_core_cpu.decode_INSTRUCTION[31:0] -TOP.Briey.axi_core_cpu.decode_PC[31:0] +TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(2)[31:0] +TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_writeBack_badAddr[31:0] @28 -TOP.Briey.axi_core_cpu.decode_arbitration_isValid +TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_writeBack_haltIt +TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_writeBack_isValid @22 -TOP.Briey.axi_core_cpu.iBus_cmd_payload_address[31:0] +TOP.Briey.axi_core_cpu.dBus_cmd_payload_address[31:0] +TOP.Briey.axi_core_cpu.dBus_cmd_payload_data[31:0] @28 -TOP.Briey.axi_core_cpu.iBus_cmd_ready -TOP.Briey.axi_core_cpu.iBus_cmd_valid +TOP.Briey.axi_core_cpu.dBus_cmd_payload_last +TOP.Briey.axi_core_cpu.dBus_cmd_payload_length[2:0] @22 -TOP.Briey.axi_core_cpu.iBus_rsp_payload_data[31:0] +TOP.Briey.axi_core_cpu.dBus_cmd_payload_mask[3:0] @28 -TOP.Briey.axi_core_cpu.iBus_rsp_valid +TOP.Briey.axi_core_cpu.dBus_cmd_payload_wr +TOP.Briey.axi_core_cpu.dBus_cmd_ready +TOP.Briey.axi_core_cpu.dBus_cmd_valid @22 -TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_addr[25:0] +TOP.Briey.axi_core_cpu.dBus_rsp_payload_data[31:0] @28 -TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_burst[1:0] +TOP.Briey.axi_core_cpu.dBus_rsp_payload_error +TOP.Briey.axi_core_cpu.dBus_rsp_valid @22 -TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_id[3:0] -TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_len[7:0] +TOP.Briey.axi_ram.io_axi_r_payload_data[31:0] +TOP.Briey.axi_ram.io_axi_r_payload_id[3:0] @28 -TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_size[2:0] -TOP.Briey.axi_sdramCtrl.io_axi_arw_payload_write -TOP.Briey.axi_sdramCtrl.io_axi_arw_ready -TOP.Briey.axi_sdramCtrl.io_axi_arw_valid +TOP.Briey.axi_ram.io_axi_r_payload_last +TOP.Briey.axi_ram.io_axi_r_payload_resp[1:0] +TOP.Briey.axi_ram.io_axi_r_ready +TOP.Briey.axi_ram.io_axi_r_valid @22 -TOP.Briey.axi_sdramCtrl.io_axi_r_payload_data[31:0] -TOP.Briey.axi_sdramCtrl.io_axi_r_payload_id[3:0] +TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_execute_args_address[31:0] +TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_execute_args_data[31:0] @28 -TOP.Briey.axi_sdramCtrl.io_axi_r_payload_last -TOP.Briey.axi_sdramCtrl.io_axi_r_ready -TOP.Briey.axi_sdramCtrl.io_axi_r_valid +TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_execute_args_wr +TOP.Briey.axi_core_cpu.dataCache_1.io_cpu_execute_isValid +TOP.Briey.axi_core_cpu.execute_arbitration_isFiring @22 -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_address[24:0] -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_context_id[3:0] +TOP.Briey.axi_core_cpu.execute_PC[31:0] +TOP.Briey.axi_ram.io_axi_arw_payload_addr[11:0] +TOP.Briey.axi_ram.io_axi_arw_payload_len[7:0] @28 -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_context_last +TOP.Briey.axi_ram.io_axi_arw_payload_size[2:0] +TOP.Briey.axi_ram.io_axi_arw_payload_write +TOP.Briey.axi_ram.io_axi_arw_ready +TOP.Briey.axi_ram.io_axi_arw_valid @22 -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_data[15:0] +TOP.Briey.axi_ram.io_axi_w_payload_data[31:0] +TOP.Briey.axi_ram.io_axi_w_payload_strb[3:0] @28 -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_mask[1:0] -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_write -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_ready -@29 -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_valid +TOP.Briey.axi_ram.io_axi_w_ready +TOP.Briey.axi_ram.io_axi_w_valid +TOP.Briey.axi_core_cpu.DebugPlugin_haltIt @22 -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_payload_context_id[3:0] -@28 -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_payload_context_last -@22 -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_payload_data[15:0] -@28 -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_ready -TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_valid +TOP.Briey.axi_core_cpu.execute_INSTRUCTION[31:0] +TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(11)[31:0] +TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(14)[31:0] [pattern_trace] 1 [pattern_trace] 0 diff --git a/src/test/cpp/regression/fail.gtkw b/src/test/cpp/regression/fail.gtkw index 3ddc974..fd018b7 100644 --- a/src/test/cpp/regression/fail.gtkw +++ b/src/test/cpp/regression/fail.gtkw @@ -1,27 +1,21 @@ [*] [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI -[*] Wed May 31 17:28:39 2017 +[*] Sat Jun 24 10:59:33 2017 [*] [dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/regression/debugPluginExternal.vcd" -[dumpfile_mtime] "Wed May 31 17:28:23 2017" -[dumpfile_size] 285487729 +[dumpfile_mtime] "Sat Jun 24 10:59:20 2017" +[dumpfile_size] 147859982 [savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/regression/fail.gtkw" -[timestart] 1754228 -[size] 1776 953 -[pos] -775 -353 -*-5.000000 1754292 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[timestart] 0 +[size] 1728 935 +[pos] -775 -1 +*-16.000000 221100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] TOP. [treeopen] TOP.VexRiscv. -[sst_width] 264 -[signals_width] 416 +[sst_width] 260 +[signals_width] 486 [sst_expanded] 1 -[sst_vpaned_height] 279 -@28 -TOP.VexRiscv.DebugPlugin_haltIt -TOP.VexRiscv.DebugPlugin_insertDecodeInstruction -TOP.VexRiscv.DebugPlugin_isPipActive -TOP.VexRiscv.DebugPlugin_isPipBusy -TOP.VexRiscv.clk +[sst_vpaned_height] 273 @22 TOP.VexRiscv.dataCache_1.io_cpu_execute_args_address[31:0] @28 @@ -30,27 +24,32 @@ TOP.VexRiscv.dataCache_1.io_cpu_execute_args_clean TOP.VexRiscv.dataCache_1.io_cpu_execute_args_data[31:0] @28 TOP.VexRiscv.dataCache_1.io_cpu_execute_args_forceUncachedAccess -@29 TOP.VexRiscv.dataCache_1.io_cpu_execute_args_invalidate -@28 TOP.VexRiscv.dataCache_1.io_cpu_execute_args_kind[0] TOP.VexRiscv.dataCache_1.io_cpu_execute_args_size[1:0] TOP.VexRiscv.dataCache_1.io_cpu_execute_args_way TOP.VexRiscv.dataCache_1.io_cpu_execute_args_wr +TOP.VexRiscv.DebugPlugin_haltIt +TOP.VexRiscv.DebugPlugin_haltedByBreak +TOP.VexRiscv.DebugPlugin_stepIt +@22 +TOP.VexRiscv.execute_PC[31:0] +@28 TOP.VexRiscv.dataCache_1.io_cpu_execute_isValid @22 -TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_address[31:0] -TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_data[31:0] -TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_length[3:0] -TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_mask[3:0] +TOP.VexRiscv.RegFilePlugin_regFile(15)[31:0] +TOP.VexRiscv.RegFilePlugin_regFile(2)[31:0] +TOP.VexRiscv.DebugPlugin_busReadDataReg[31:0] +TOP.debug_bus_cmd_payload_address[7:0] +TOP.debug_bus_cmd_payload_data[31:0] @28 -TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_wr -TOP.VexRiscv.dataCache_1.io_mem_cmd_ready -TOP.VexRiscv.dataCache_1.io_mem_cmd_valid +TOP.debug_bus_cmd_payload_wr +@29 +TOP.debug_bus_cmd_valid +TOP.debug_bus_cmd_ready +@23 +TOP.debug_bus_rsp_data[31:0] @22 -TOP.VexRiscv.dataCache_1.victim_request_payload_address[31:0] -@28 -TOP.VexRiscv.dataCache_1.victim_request_ready -TOP.VexRiscv.dataCache_1.victim_request_valid +TOP.VexRiscv.RegFilePlugin_regFile(2)[31:0] [pattern_trace] 1 [pattern_trace] 0 diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 6d4a4fe..174b017 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -256,6 +256,11 @@ public: } switch(addr){ + case 0xF0010000u: { + cout << mem[0xF0010000u]; + logTraces << (char)mem[0xF0010000u]; + break; + } case 0xF00FFF00u: { cout << mem[0xF00FFF00u]; logTraces << (char)mem[0xF00FFF00u]; @@ -283,6 +288,7 @@ public: case 0xF00FFF44u: *data = mTime >> 32; break; case 0xF00FFF48u: *data = mTimeCmp; break; case 0xF00FFF4Cu: *data = mTimeCmp >> 32; break; + case 0xF0010004u: *data = ~0; break; } memTraces << #ifdef TRACE_WITH_TIME @@ -793,9 +799,10 @@ public: top->debug_bus_cmd_payload_data = data; } else { bool dummy; - printf("wr=%d size=%d address=%x data=%x\n",wr,size,address,data); + //printf("wr=%d size=%d address=%x data=%x\n",wr,size,address,data); ws->dBusAccess(address,wr,size,0xFFFFFFFF, &data, &dummy); if(!wr){ + //cout << hex << setw(8) << address << " -> " << hex << setw(8) << data << endl; if(-1 == send(clientHandle,&data,4,0)) connectionReset(); } } @@ -1022,6 +1029,7 @@ public: printf("Should read 4 bytes"); fail(); } + return *((uint32_t*) buffer); }