From eafeb5fe493e5cdf9523f565a17be090724ec6c4 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 28 Nov 2022 11:04:02 +0100 Subject: [PATCH] Add EmbeddedRiscvJtag.debugCd --- src/main/scala/vexriscv/TestsWorkspace.scala | 1 + .../demo/GenFullWithRiscvPrivilegedDebugJtag.scala | 1 + src/main/scala/vexriscv/demo/SynthesisBench.scala | 1 + src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala | 8 +++++--- src/test/cpp/regression/main.cpp | 1 + 5 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index f102d81..32645db 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -152,6 +152,7 @@ object TestsWorkspace { version = 1, idle = 7 ), + debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")), withTunneling = false, withTap = true ) diff --git a/src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala b/src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala index e6496b1..7dd17dd 100644 --- a/src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala +++ b/src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala @@ -82,6 +82,7 @@ object GenFullWithRiscvPrivilegedDebugJtag extends App{ version = 1, idle = 7 ), + debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")), withTap = true, withTunneling = false ), diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index 7a1ff35..d018819 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -483,6 +483,7 @@ object VexRiscvCustomSynthesisBench { version = 1, idle = 7 ), + debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")), withTunneling = false, withTap = true )).setDefinitionName(getRtlPath().split("\\.").head)) diff --git a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala index c75c4d1..3366e72 100644 --- a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala +++ b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala @@ -13,6 +13,7 @@ import vexriscv._ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter, + var debugCd : ClockDomain = null, var withTap : Boolean = true, var withTunneling : Boolean = false ) extends Plugin[VexRiscv] with VexRiscvRegressionArg{ @@ -24,16 +25,17 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter, var jtagInstruction : JtagTapInstructionCtrl = null var ndmreset : Bool = null -// val debugCd = Handle[ClockDomain].setName("debugCd") -// val noTapCd = Handle[ClockDomain].setName("jtagCd") + + def setDebugCd(cd : ClockDomain) : this.type = {debugCd = cd; this} override def setup(pipeline: VexRiscv): Unit = { jtag = withTap generate slave(Jtag()).setName("jtag") jtagInstruction = !withTap generate slave(JtagTapInstructionCtrl()).setName("jtagInstruction") ndmreset = out(Bool()).setName("ndmreset") + assert(debugCd != null, "You need to set the debugCd of the VexRiscv EmbeddedRiscvJtag.") } - override def build(pipeline: VexRiscv): Unit = { + override def build(pipeline: VexRiscv): Unit = debugCd{ val XLEN = 32 val dm = DebugModule( DebugModuleParameter( diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 0c3fdd3..67dff41 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -3150,6 +3150,7 @@ void Workspace::fillSimELements(){ #endif #ifdef RISCV_JTAG simElements.push_back(new Jtag(&top->jtag_tms, &top->jtag_tdi, &top->jtag_tdo, &top->jtag_tck, 4)); + simElements.push_back(new VexRiscvJtag(this)); #endif #ifdef VEXRISCV_JTAG simElements.push_back(new Jtag(&top->jtag_tms, &top->jtag_tdi, &top->jtag_tdo, &top->jtag_tck, 4));