From ebda7526b52091c1fc7f114e9e356b4ebb0edc5d Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 17 Dec 2017 17:57:09 +0100 Subject: [PATCH] MuraxSim 1.0.0 --- .gitignore | 2 + src/main/scala/vexriscv/demo/Murax.scala | 1 + src/test/scala/vexriscv/MuraxSim.scala | 99 +++++------------------ src/test/scala/vexriscv/TcpJtag.scala | 43 ++++++++++ src/test/scala/vexriscv/UartDecoder.scala | 29 +++++++ src/test/scala/vexriscv/UartEncoder.scala | 28 +++++++ 6 files changed, 121 insertions(+), 81 deletions(-) create mode 100644 src/test/scala/vexriscv/TcpJtag.scala create mode 100644 src/test/scala/vexriscv/UartDecoder.scala create mode 100644 src/test/scala/vexriscv/UartEncoder.scala diff --git a/.gitignore b/.gitignore index 44aab3f..627a066 100644 --- a/.gitignore +++ b/.gitignore @@ -42,3 +42,5 @@ obj_dir *.tcl *.o + +*verilatorSim/ \ No newline at end of file diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 2653fb9..e929c19 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -127,6 +127,7 @@ object MuraxConfig{ bypassWriteBack = true, bypassWriteBackBuffer = true ) +// config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin])) = new FullBarrielShifterPlugin() config } diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala index 27a771c..a24ea2b 100644 --- a/src/test/scala/vexriscv/MuraxSim.scala +++ b/src/test/scala/vexriscv/MuraxSim.scala @@ -1,24 +1,21 @@ package vexriscv -import java.awt.Graphics -import java.io.{InputStream, OutputStream} -import java.net.ServerSocket -import javax.swing.{JFrame, JPanel} import spinal.sim._ import spinal.core._ import spinal.core.SimManagedApi._ import vexriscv.demo.{Murax, MuraxConfig} -import scala.concurrent.Future -import scala.util.Random -import scala.concurrent.ExecutionContext.Implicits.global +import java.awt.Graphics +import javax.swing.{JFrame, JPanel} + + object MuraxSim { def main(args: Array[String]): Unit = { // val config = MuraxConfig.default.copy(onChipRamSize = 256 kB) val config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex") - SimConfig(new Murax(config)).doManagedSim{dut => + SimConfig(new Murax(config)).allOptimisation.doManagedSim{dut => val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong val jtagClkPeriod = mainClkPeriod*4 val uartBaudRate = 115200 @@ -41,87 +38,27 @@ object MuraxSim { cycleCounter += 1 if(cycleCounter == 100000){ val currentTime = System.nanoTime() -// println(f"${cycleCounter/((currentTime - lastTime)*1e-9)*1e-3}%4.0f kHz") + println(f"${cycleCounter/((currentTime - lastTime)*1e-9)*1e-3}%4.0f kHz") lastTime = currentTime cycleCounter = 0 } } } + val tcpJtag = TcpJtag( + jtag = dut.io.jtag, + jtagClkPeriod = jtagClkPeriod + ) - val jtag = fork { - var inputStream : InputStream = null - var outputStream : OutputStream = null + val uartTx = UartDecoder( + uartPin = dut.io.uart.txd, + baudPeriod = uartBaudPeriod + ) - val server = Future { - val socket = new ServerSocket(7894) - println("WAITING FOR TCP JTAG CONNECTION") - while (true) { - val connection = socket.accept() - connection.setTcpNoDelay(true) - outputStream = connection.getOutputStream() - inputStream = connection.getInputStream() - println("TCP JTAG CONNECTION") - } - } - - while(true) { - sleep(mainClkPeriod * 1000) - while(inputStream != null && inputStream.available() != 0){ - val buffer = inputStream.read() - dut.io.jtag.tms #= (buffer & 1) != 0; - dut.io.jtag.tdi #= (buffer & 2) != 0; - dut.io.jtag.tck #= (buffer & 8) != 0; - if((buffer & 4) != 0){ - outputStream.write(if(dut.io.jtag.tdo.toBoolean) 1 else 0) - } - sleep(jtagClkPeriod/2) - } - } - } - - val uartTx = fork{ - waitUntil(dut.io.uart.txd.toBoolean == true) - - while(true) { - waitUntil(dut.io.uart.txd.toBoolean == false) - sleep(uartBaudPeriod/2) - - assert(dut.io.uart.txd.toBoolean == false) - sleep(uartBaudPeriod) - - var buffer = 0 - (0 to 7).foreachSim{ bitId => - if(dut.io.uart.txd.toBoolean) - buffer |= 1 << bitId - sleep(uartBaudPeriod) - } - - assert(dut.io.uart.txd.toBoolean == true) - print(buffer.toChar) - } - } - - val uartRx = fork{ - dut.io.uart.rxd #= true - while(true) { - if(System.in.available() != 0){ - val buffer = System.in.read() - dut.io.uart.rxd #= false - sleep(uartBaudPeriod) - - (0 to 7).foreachSim{ bitId => - dut.io.uart.rxd #= ((buffer >> bitId) & 1) != 0 - sleep(uartBaudPeriod) - } - - dut.io.uart.rxd #= true - sleep(uartBaudPeriod) - } else { - sleep(uartBaudPeriod * 10) - } - } - } + val uartRx = UartEncoder( + uartPin = dut.io.uart.rxd, + baudPeriod = uartBaudPeriod + ) val leds = fork{ diff --git a/src/test/scala/vexriscv/TcpJtag.scala b/src/test/scala/vexriscv/TcpJtag.scala new file mode 100644 index 0000000..1ce4806 --- /dev/null +++ b/src/test/scala/vexriscv/TcpJtag.scala @@ -0,0 +1,43 @@ +package vexriscv + +import java.io.{InputStream, OutputStream} +import java.net.ServerSocket + +import spinal.core.SimManagedApi._ +import spinal.lib.com.jtag.Jtag + +import scala.concurrent.Future +import scala.concurrent.ExecutionContext.Implicits.global + +object TcpJtag { + def apply(jtag: Jtag, jtagClkPeriod: Long) = fork { + var inputStream: InputStream = null + var outputStream: OutputStream = null + + val server = Future { + val socket = new ServerSocket(7894) + println("WAITING FOR TCP JTAG CONNECTION") + while (true) { + val connection = socket.accept() + connection.setTcpNoDelay(true) + outputStream = connection.getOutputStream() + inputStream = connection.getInputStream() + println("TCP JTAG CONNECTION") + } + } + + while (true) { + sleep(jtagClkPeriod * 200) + while (inputStream != null && inputStream.available() != 0) { + val buffer = inputStream.read() + jtag.tms #= (buffer & 1) != 0; + jtag.tdi #= (buffer & 2) != 0; + jtag.tck #= (buffer & 8) != 0; + if ((buffer & 4) != 0) { + outputStream.write(if (jtag.tdo.toBoolean) 1 else 0) + } + sleep(jtagClkPeriod / 2) + } + } + } +} diff --git a/src/test/scala/vexriscv/UartDecoder.scala b/src/test/scala/vexriscv/UartDecoder.scala new file mode 100644 index 0000000..fdb9b97 --- /dev/null +++ b/src/test/scala/vexriscv/UartDecoder.scala @@ -0,0 +1,29 @@ +package vexriscv + +import spinal.sim._ +import spinal.core.SimManagedApi._ +import spinal.core.{Bool, assert} + +object UartDecoder { + def apply(uartPin : Bool, baudPeriod : Long) = fork{ + waitUntil(uartPin.toBoolean == true) + + while(true) { + waitUntil(uartPin.toBoolean == false) + sleep(baudPeriod/2) + + assert(uartPin.toBoolean == false) + sleep(baudPeriod) + + var buffer = 0 + (0 to 7).suspendable.foreach{ bitId => + if(uartPin.toBoolean) + buffer |= 1 << bitId + sleep(baudPeriod) + } + + assert(uartPin.toBoolean == true) + print(buffer.toChar) + } + } +} diff --git a/src/test/scala/vexriscv/UartEncoder.scala b/src/test/scala/vexriscv/UartEncoder.scala new file mode 100644 index 0000000..8053b1e --- /dev/null +++ b/src/test/scala/vexriscv/UartEncoder.scala @@ -0,0 +1,28 @@ +package vexriscv + +import spinal.sim._ +import spinal.core.Bool +import spinal.core.SimManagedApi._ + +object UartEncoder { + def apply(uartPin : Bool, baudPeriod : Long) = fork{ + uartPin #= true + while(true) { + if(System.in.available() != 0){ + val buffer = System.in.read() + uartPin #= false + sleep(baudPeriod) + + (0 to 7).suspendable.foreach{ bitId => + uartPin #= ((buffer >> bitId) & 1) != 0 + sleep(baudPeriod) + } + + uartPin #= true + sleep(baudPeriod) + } else { + sleep(baudPeriod * 10) + } + } + } +}