From ec4837a744f2e84c701569e4ff6c51a115bf62ac Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Sun, 12 Mar 2017 12:39:33 +0100
Subject: [PATCH] wip

---
 sim/cmd.txt                               |  4 +++
 sim/tester.cpp                            | 38 +++++++++++++++++++++++
 src/main/scala/SpinalRiscv/TopLevel.scala |  8 ++++-
 3 files changed, 49 insertions(+), 1 deletion(-)
 create mode 100644 sim/cmd.txt
 create mode 100644 sim/tester.cpp

diff --git a/sim/cmd.txt b/sim/cmd.txt
new file mode 100644
index 0000000..3b4e3a4
--- /dev/null
+++ b/sim/cmd.txt
@@ -0,0 +1,4 @@
+
+
+verilator -cc  ../VexRiscv.v --trace -Wno-WIDTH --exe tester.cpp
+make -j -C obj_dir/ -f VVexRiscv.mk VVexRiscv
\ No newline at end of file
diff --git a/sim/tester.cpp b/sim/tester.cpp
new file mode 100644
index 0000000..ea3793c
--- /dev/null
+++ b/sim/tester.cpp
@@ -0,0 +1,38 @@
+#include "VVexRiscv.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+
+
+int main(int argc, char **argv, char **env) {
+  int i;
+  int clk;
+  Verilated::commandArgs(argc, argv);
+  // init top verilog instance
+  VVexRiscv* top = new VVexRiscv;
+  // init trace dump
+  Verilated::traceEverOn(true);
+  VerilatedVcdC* tfp = new VerilatedVcdC;
+  top->trace (tfp, 99);
+  tfp->open ("sim.vcd");
+  // initialize simulation inputs
+  top->clk = 1;
+ // top->rst = 1;
+ // top->cen = 0;
+ // top->wen = 0;
+ // top->dat = 0x55;
+  // run simulation for 100 clock periods
+  for (i=0; i<20; i++) {
+ //   top->rst = (i < 2);
+    // dump variables into VCD file and toggle clock
+    for (clk=0; clk<2; clk++) {
+      tfp->dump (2*i+clk);
+      top->clk = !top->clk;
+      top->eval ();
+    }
+  //  top->cen = (i > 5);
+  //  top->wen = (i == 10);
+    if (Verilated::gotFinish())  exit(0);
+  }
+  tfp->close();
+  exit(0);
+}
diff --git a/src/main/scala/SpinalRiscv/TopLevel.scala b/src/main/scala/SpinalRiscv/TopLevel.scala
index fd5b88f..2c5d6f6 100644
--- a/src/main/scala/SpinalRiscv/TopLevel.scala
+++ b/src/main/scala/SpinalRiscv/TopLevel.scala
@@ -275,6 +275,12 @@ class NoPredictionBranchPlugin extends Plugin[VexRiscv]{
         BranchCtrlEnum.JALR -> (input(REG1).asUInt + imm.i_sext.asUInt),
         default             -> (input(PC)          + imm.b_sext.asUInt)    //B
       )
+
+      when(jumpInterface.valid){
+        prefetch.arbitration.removeIt := True
+        fetch.arbitration.removeIt    := True
+        decode.arbitration.removeIt   := True
+      }
     }
   }
 }
@@ -809,7 +815,7 @@ class OutputAluResult extends Plugin[VexRiscv]{
 
 object TopLevel {
   def main(args: Array[String]) {
-    SpinalVhdl{
+    SpinalVerilog{
       val config = VexRiscvConfig(
         pcWidth = 32
       )