From eeb65ed1c001ece8115787c2ae2ce7a2f06f0467 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 24 Mar 2023 08:39:07 +0100 Subject: [PATCH] VexRiscvBmbGenrator now use relaxedReset --- src/main/scala/vexriscv/VexRiscvBmbGenerator.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala index 4af0e08..269f036 100644 --- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala +++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala @@ -47,7 +47,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener def enableJtag(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{ this.debugClockDomain.load(debugCd.outputClockDomain) - val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) + val resetBridge = resetCd.relaxedReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() withDebug.load(DEBUG_JTAG) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) @@ -55,7 +55,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener def enableJtagInstructionCtrl(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{ this.debugClockDomain.load(debugCd.outputClockDomain) - val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) + val resetBridge = resetCd.relaxedReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() withDebug.load(DEBUG_JTAG_CTRL) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) @@ -63,7 +63,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener def enableDebugBus(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{ this.debugClockDomain.load(debugCd.outputClockDomain) - val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) + val resetBridge = resetCd.relaxedReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() withDebug.load(DEBUG_BUS) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) @@ -87,7 +87,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener val debugBmbAccessRequirements = Handle[BmbAccessParameter] def enableDebugBmb(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGeneratorIf, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.on{ this.debugClockDomain.load(debugCd) - val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) + val resetBridge = resetCd.relaxedReset(debugReset, ResetSensitivity.HIGH) debugAskReset.loadNothing() withDebug.load(DEBUG_BMB) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false)