From eee9927baf875fd5ab270542a7188442fd559ade Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 28 Apr 2020 22:10:56 +0200 Subject: [PATCH] IBusCachedPlugin now support memory data width multiple of 32 --- src/main/scala/vexriscv/ip/InstructionCache.scala | 9 ++++----- src/test/cpp/regression/main.cpp | 11 ++++++++--- src/test/cpp/regression/makefile | 4 ++++ src/test/scala/vexriscv/TestIndividualFeatures.scala | 9 +++++---- 4 files changed, 21 insertions(+), 12 deletions(-) diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala index 09b1a8a..469377c 100644 --- a/src/main/scala/vexriscv/ip/InstructionCache.scala +++ b/src/main/scala/vexriscv/ip/InstructionCache.scala @@ -70,7 +70,7 @@ case class InstructionCacheConfig( cacheSize : Int, def getBmbParameter() = BmbParameter( addressWidth = 32, - dataWidth = 32, + dataWidth = memDataWidth, lengthWidth = log2Up(this.bytePerLine), sourceWidth = 0, contextWidth = 0, @@ -278,7 +278,6 @@ case class InstructionCacheFlushBus() extends Bundle with IMasterSlave{ class InstructionCache(p : InstructionCacheConfig) extends Component{ import p._ - assert(cpuDataWidth == memDataWidth, "Need testing") val io = new Bundle{ val flush = in Bool() val cpu = slave(InstructionCacheCpuBus(p)) @@ -287,7 +286,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ val lineWidth = bytePerLine*8 val lineCount = cacheSize/bytePerLine - val wordWidth = Math.max(memDataWidth,32) + val wordWidth = cpuDataWidth val wordWidthLog2 = log2Up(wordWidth) val wordPerLine = lineWidth/wordWidth val memWordPerLine = lineWidth/memDataWidth @@ -295,7 +294,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ val bytePerMemWord = memDataWidth/8 val wayLineCount = lineCount/wayCount val wayLineLog2 = log2Up(wayLineCount) - val wayWordCount = wayLineCount * wordPerLine + val wayMemWordCount = wayLineCount * memWordPerLine val tagRange = addressWidth-1 downto log2Up(wayLineCount*bytePerLine) val lineRange = tagRange.low-1 downto log2Up(bytePerLine) @@ -314,7 +313,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ val ways = Seq.fill(wayCount)(new Area{ val tags = Mem(LineTag(),wayLineCount) - val datas = Mem(Bits(memDataWidth bits),wayWordCount) + val datas = Mem(Bits(memDataWidth bits),wayMemWordCount) if(preResetFlush){ tags.initBigInt(List.fill(wayLineCount)(BigInt(0))) diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 82e0671..5fa9635 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -2026,10 +2026,15 @@ public: ws->fail(); } #endif - ws->iBusAccess(address,&top->iBus_rsp_payload_data,&error); + error = false; + for(int idx = 0;idx < IBUS_DATA_WIDTH/32;idx++){ + bool localError; + ws->iBusAccess(address+idx*4,((uint32_t*)&top->iBus_rsp_payload_data)+idx,&localError); + error |= localError; + } top->iBus_rsp_payload_error = error; - pendingCount--; - address = address + 4; + pendingCount-=IBUS_DATA_WIDTH/32; + address = address + IBUS_DATA_WIDTH/8; top->iBus_rsp_valid = 1; } if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I(7) < 100 && pendingCount == 0; diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile index 160707a..9836326 100644 --- a/src/test/cpp/regression/makefile +++ b/src/test/cpp/regression/makefile @@ -3,6 +3,7 @@ REGRESSION_PATH?=./ VEXRISCV_FILE?=../../../../VexRiscv.v IBUS?=CACHED IBUS_TC?=no +IBUS_DATA_WIDTH?=32 DBUS?=CACHED TRACE?=no TRACE_ACCESS?=no @@ -41,8 +42,11 @@ STOP_ON_ERROR?=no COREMARK=no WITH_USER_IO?=no + ADDCFLAGS += -CFLAGS -DREGRESSION_PATH='\"$(REGRESSION_PATH)/\"' ADDCFLAGS += -CFLAGS -DIBUS_${IBUS} +ADDCFLAGS += -CFLAGS -DIBUS_DATA_WIDTH=${IBUS_DATA_WIDTH} + ADDCFLAGS += -CFLAGS -DDBUS_${DBUS} ADDCFLAGS += -CFLAGS -DREDO=${REDO} ADDCFLAGS += -CFLAGS -pthread diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala index f23299a..98da229 100644 --- a/src/test/scala/vexriscv/TestIndividualFeatures.scala +++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala @@ -354,7 +354,8 @@ class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") { val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET)) val relaxedPcCalculation, twoCycleCache, injectorStage = r.nextBoolean() val twoCycleRam = r.nextBoolean() && twoCycleCache - val bytePerLine = List(8,16,32,64)(r.nextInt(4)) + val memDataWidth = List(32,64,128)(r.nextInt(3)) + val bytePerLine = Math.max(memDataWidth/8, List(8,16,32,64)(r.nextInt(4))) var cacheSize = 0 var wayCount = 0 do{ @@ -362,8 +363,8 @@ class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") { wayCount = 1 << r.nextInt(3) }while(cacheSize/wayCount < 512 || (catchAll && cacheSize/wayCount > 4096)) - new VexRiscvPosition("Cached" + (if(twoCycleCache) "2cc" else "") + (if(injectorStage) "Injstage" else "") + (if(twoCycleRam) "2cr" else "") + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(relaxedPcCalculation) "Relax" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")+ (if(tighlyCoupled)"Tc" else "")) with InstructionAnticipatedPosition{ - override def testParam = "IBUS=CACHED" + (if(compressed) " COMPRESSED=yes" else "") + (if(tighlyCoupled)" IBUS_TC=yes" else "") + new VexRiscvPosition(s"Cached${memDataWidth}d" + (if(twoCycleCache) "2cc" else "") + (if(injectorStage) "Injstage" else "") + (if(twoCycleRam) "2cr" else "") + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(relaxedPcCalculation) "Relax" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")+ (if(tighlyCoupled)"Tc" else "")) with InstructionAnticipatedPosition{ + override def testParam = s"IBUS=CACHED IBUS_DATA_WIDTH=$memDataWidth" + (if(compressed) " COMPRESSED=yes" else "") + (if(tighlyCoupled)" IBUS_TC=yes" else "") override def applyOn(config: VexRiscvConfig): Unit = { val p = new IBusCachedPlugin( resetVector = 0x80000000l, @@ -378,7 +379,7 @@ class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") { wayCount = wayCount, addressWidth = 32, cpuDataWidth = 32, - memDataWidth = 32, + memDataWidth = memDataWidth, catchIllegalAccess = catchAll, catchAccessFault = catchAll, asyncTagMemory = false,