From f13dba847c560bd9cfd909770214fa23b30b35f0 Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Fri, 2 Feb 2018 11:14:55 +0100
Subject: [PATCH] Add custom csr gpio example

---
 .../vexriscv/demo/CustomCsrDemoPlugin.scala   | 29 +++++++++++++++++++
 .../scala/vexriscv/demo/GenCustomCsr.scala    |  1 +
 .../scala/vexriscv/plugin/CsrPlugin.scala     | 17 +++++++----
 3 files changed, 41 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/vexriscv/demo/CustomCsrDemoPlugin.scala b/src/main/scala/vexriscv/demo/CustomCsrDemoPlugin.scala
index 97aecbe..a763c83 100644
--- a/src/main/scala/vexriscv/demo/CustomCsrDemoPlugin.scala
+++ b/src/main/scala/vexriscv/demo/CustomCsrDemoPlugin.scala
@@ -1,6 +1,8 @@
 package vexriscv.demo
 
 import spinal.core._
+import spinal.lib.io.TriStateArray
+import spinal.lib.{Flow, master}
 import vexriscv.plugin.{CsrInterface, Plugin}
 import vexriscv.{DecoderService, Stageable, VexRiscv}
 
@@ -32,3 +34,30 @@ class CustomCsrDemoPlugin extends Plugin[VexRiscv]{
     }
   }
 }
+
+
+class CustomCsrDemoGpioPlugin extends Plugin[VexRiscv]{
+  var gpio : TriStateArray = null
+
+
+  override def setup(pipeline: VexRiscv): Unit = {
+    gpio = master(TriStateArray(32 bits)).setName("gpio")
+  }
+
+  override def build(pipeline: VexRiscv): Unit = {
+    import pipeline._
+    import pipeline.config._
+
+    pipeline plug new Area{
+      val writeReg, writeEnableReg = Reg(Bits(32 bits))
+
+      val csrService = pipeline.service(classOf[CsrInterface])
+      csrService.rw(0xB08, writeReg)
+      csrService.rw(0xB09, writeEnableReg)
+      csrService.r(0xB0A, gpio.read)
+
+      gpio.writeEnable := writeEnableReg
+      gpio.write := writeReg
+    }
+  }
+}
diff --git a/src/main/scala/vexriscv/demo/GenCustomCsr.scala b/src/main/scala/vexriscv/demo/GenCustomCsr.scala
index 8978efa..d0f0463 100644
--- a/src/main/scala/vexriscv/demo/GenCustomCsr.scala
+++ b/src/main/scala/vexriscv/demo/GenCustomCsr.scala
@@ -15,6 +15,7 @@ object GenCustomCsr extends App{
       plugins = List(
         new CustomCsrDemoPlugin,
         new CsrPlugin(CsrPluginConfig.small),
+        new CustomCsrDemoGpioPlugin,
         new PcManagerSimplePlugin(
           resetVector = 0x00000000l,
           relaxedPcCalculation = false
diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index f859311..5efb3b4 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -55,7 +55,11 @@ case class CsrPluginConfig(
 }
 
 object CsrPluginConfig{
-  val all = CsrPluginConfig(
+  def all : CsrPluginConfig = all(0x00000020l)
+  def small : CsrPluginConfig = small(0x00000020l)
+  def smallest : CsrPluginConfig = smallest(0x00000020l)
+
+  def all(mtvecInit : BigInt) : CsrPluginConfig = CsrPluginConfig(
     catchIllegalAccess = true,
     mvendorid      = 11,
     marchid        = 22,
@@ -64,7 +68,7 @@ object CsrPluginConfig{
     misaExtensionsInit = 66,
     misaAccess     = CsrAccess.READ_WRITE,
     mtvecAccess    = CsrAccess.READ_WRITE,
-    mtvecInit      = 0x00000020l,
+    mtvecInit      = mtvecInit,
     mepcAccess     = CsrAccess.READ_WRITE,
     mscratchGen    = true,
     mcauseAccess   = CsrAccess.READ_WRITE,
@@ -76,7 +80,7 @@ object CsrPluginConfig{
     ucycleAccess   = CsrAccess.READ_ONLY
   )
 
-  val small = CsrPluginConfig(
+  def small(mtvecInit : BigInt)  = CsrPluginConfig(
     catchIllegalAccess = false,
     mvendorid      = null,
     marchid        = null,
@@ -85,7 +89,7 @@ object CsrPluginConfig{
     misaExtensionsInit = 66,
     misaAccess     = CsrAccess.NONE,
     mtvecAccess    = CsrAccess.NONE,
-    mtvecInit      = 0x00000020l,
+    mtvecInit      = mtvecInit,
     mepcAccess     = CsrAccess.READ_WRITE,
     mscratchGen    = false,
     mcauseAccess   = CsrAccess.READ_ONLY,
@@ -97,7 +101,7 @@ object CsrPluginConfig{
     ucycleAccess   = CsrAccess.NONE
   )
 
-  val smallest = CsrPluginConfig(
+  def smallest(mtvecInit : BigInt)  = CsrPluginConfig(
     catchIllegalAccess = false,
     mvendorid      = null,
     marchid        = null,
@@ -106,7 +110,7 @@ object CsrPluginConfig{
     misaExtensionsInit = 66,
     misaAccess     = CsrAccess.NONE,
     mtvecAccess    = CsrAccess.NONE,
-    mtvecInit      = 0x00000020l,
+    mtvecInit      = mtvecInit,
     mepcAccess     = CsrAccess.NONE,
     mscratchGen    = false,
     mcauseAccess   = CsrAccess.READ_ONLY,
@@ -146,6 +150,7 @@ trait CsrInterface{
   def rw(csrAddress : Int, thats : (Int, Data)*) : Unit = for(that <- thats) rw(csrAddress,that._1, that._2)
   def r [T <: Data](csrAddress : Int, thats : (Int, Data)*) : Unit = for(that <- thats) r(csrAddress,that._1, that._2)
   def rw[T <: Data](csrAddress : Int, that : T): Unit = rw(csrAddress,0,that)
+  def w[T <: Data](csrAddress : Int, that : T): Unit = w(csrAddress,0,that)
   def r [T <: Data](csrAddress : Int, that : T): Unit = r(csrAddress,0,that)
   def isWriting(csrAddress : Int) : Bool = {
     val ret = False