diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
index 8b299de..99393ac 100644
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@@ -211,6 +211,7 @@ class success : public std::exception { };
 #define MCYCLEH    0xB80 // MRW Upper 32 bits of mcycle, RV32I only.
 #define MINSTRETH  0xB82 // MRW Upper 32 bits of minstret, RV32I only.
 
+
 #define SSTATUS 0x100
 #define SIE 0x104
 #define STVEC 0x105
@@ -373,25 +374,9 @@ public:
 		};
 	};
 	
+
 	bool lrscReserved;
 
-	struct pmpcfg_s {
-		uint32_t r : 1;
-		uint32_t w : 1;	
-		uint32_t x : 1;	
-		uint32_t a : 2;	
-		uint32_t _dummy : 2;	
-		uint32_t l : 1;	
-	} __attribute__((packed)); 
-
-	union pmpcfg_u {
-		uint32_t raw;
-		pmpcfg_s reg[4];
-	};
-
-	pmpcfg_u pmpcfg[4];
-	uint32_t pmpaddr[16];
-
 	RiscvGolden() {
 		pc = 0x80000000;
 		regs[0] = 0;
@@ -416,10 +401,6 @@ public:
 		ipInput = 0;
 		stepCounter = 0;
 		lrscReserved = false;
-		for (int i = 0; i < 4; i++)
-			pmpcfg[i].raw = 0;
-		for (int i = 0; i < 16; i++)
-			pmpaddr[i] = 0;
 	}
 
 	virtual void rfWrite(int32_t address, int32_t data) {
@@ -444,10 +425,8 @@ public:
 
 	enum AccessKind {READ,WRITE,EXECUTE,READ_WRITE};
 	virtual bool isMmuRegion(uint32_t v) = 0;
-
-
-	bool v2p(uint32_t v, uint32_t *p, AccessKind kind) {
-		uint32_t effectivePrivilege = status.mprv && kind != EXECUTE ? status.mpp : privilege;
+	bool v2p(uint32_t v, uint32_t *p, AccessKind kind){
+	    uint32_t effectivePrivilege = status.mprv && kind != EXECUTE ? status.mpp : privilege;
 		if(effectivePrivilege == 3 || satp.mode == 0 || !isMmuRegion(v)){
 			*p = v;
 		} else {
@@ -549,7 +528,7 @@ public:
 
 	virtual bool csrRead(int32_t csr, uint32_t *value){
 		if(((csr >> 8) & 0x3) > privilege) return true;
-		switch(csr) {
+		switch(csr){
 		case MSTATUS: *value = status.raw & MSTATUS_READ_MASK; break;
 		case MIP: *value = getIp().raw; break;
 		case MIE: *value = ie.raw; break;
@@ -571,7 +550,6 @@ public:
 		case SEPC: *value = sepc; break;
 		case SSCRATCH: *value = sscratch; break;
 		case SATP: *value = satp.raw; break;
-
 		default: return true; break;
 		}
 		return false;
@@ -610,6 +588,8 @@ public:
 		case SCAUSE: scause.raw = value; break;
 		case STVAL: sbadaddr = value; break;
 		case SEPC: sepc = value; break;
+		case SSCRATCH: sscratch = value; break;
+		case SATP: satp.raw = value; break;
 
 		default: ilegalInstruction(); return true; break;
 		}
diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile
index c71c880..5f64034 100644
--- a/src/test/cpp/regression/makefile
+++ b/src/test/cpp/regression/makefile
@@ -15,7 +15,7 @@ CSR_SKIP_TEST?=no
 EBREAK?=no
 FENCEI?=no
 MMU?=yes
-PMP?=yes
+PMP?=no
 SEED?=no
 LRSC?=no
 AMO?=no
diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala
index 64c8ad6..b2f35aa 100644
--- a/src/test/scala/vexriscv/TestIndividualFeatures.scala
+++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala
@@ -46,6 +46,7 @@ abstract class  VexRiscvPosition(name: String) extends ConfigPosition[VexRiscvCo
 class VexRiscvUniverse extends ConfigUniverse
 
 object VexRiscvUniverse{
+  val CACHE_ALL = new VexRiscvUniverse
   val CATCH_ALL = new VexRiscvUniverse
   val MMU = new VexRiscvUniverse
   val PMP = new VexRiscvUniverse
@@ -322,9 +323,10 @@ class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") {
 
   override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
     val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
+    val cacheAll = universes.contains(VexRiscvUniverse.CACHE_ALL)
     val mmuConfig = if(universes.contains(VexRiscvUniverse.MMU)) MmuPortConfig( portTlbSize = 4) else null
 
-    if(r.nextDouble() < 0.5){
+    if(r.nextDouble() < 0.5 && !cacheAll){
       val latency = r.nextInt(5) + 1
       val compressed = r.nextDouble() < rvcRate
       val injectorStage = r.nextBoolean() || latency == 1
@@ -403,13 +405,14 @@ class DBusDimension extends VexRiscvDimension("DBus") {
 
   override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
     val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
+    val cacheAll = universes.contains(VexRiscvUniverse.CACHE_ALL)
     val mmuConfig = if(universes.contains(VexRiscvUniverse.MMU)) MmuPortConfig( portTlbSize = 4) else null
     val noMemory = universes.contains(VexRiscvUniverse.NO_MEMORY)
     val noWriteBack = universes.contains(VexRiscvUniverse.NO_WRITEBACK)
 
 
 
-    if(r.nextDouble() < 0.4 || noMemory){
+    if((r.nextDouble() < 0.4 || noMemory) && !cacheAll){
       val withLrSc = catchAll
       val earlyInjection = r.nextBoolean() && !universes.contains(VexRiscvUniverse.NO_WRITEBACK)
       new VexRiscvPosition("Simple" + (if(earlyInjection) "Early" else "Late")) {
@@ -760,18 +763,15 @@ class TestIndividualFeatures extends MultithreadedFunSuite {
       }
     } else {
       if(machineOsRate > rand.nextDouble()) {
+        universe += VexRiscvUniverse.CACHE_ALL
         universe += VexRiscvUniverse.CATCH_ALL
         universe += VexRiscvUniverse.PMP
         if(demwRate < rand.nextDouble()){
           universe += VexRiscvUniverse.NO_WRITEBACK
         }
       }
-      if(demwRate > rand.nextDouble()){
-      }else if(demRate > rand.nextDouble()){
+      if(demRate > rand.nextDouble()){
         universe += VexRiscvUniverse.NO_WRITEBACK
-      } else {
-        universe += VexRiscvUniverse.NO_WRITEBACK
-        universe += VexRiscvUniverse.NO_MEMORY
       }
     }