From e357420d11205dc53c9d6e9b580b2a38f4695914 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 29 Mar 2023 11:10:45 +0200 Subject: [PATCH 1/5] CsrPluginConfig more var --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 1d03584..8733901 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -39,10 +39,10 @@ object CsrAccess { case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage, priority : Int, codeWidth : Int) case class CsrPluginConfig( catchIllegalAccess : Boolean, - mvendorid : BigInt, - marchid : BigInt, - mimpid : BigInt, - mhartid : BigInt, + var mvendorid : BigInt, + var marchid : BigInt, + var mimpid : BigInt, + var mhartid : BigInt, misaExtensionsInit : Int, misaAccess : CsrAccess, mtvecAccess : CsrAccess, From 9c2e05cce09ce0521e18150b3c1e0a40a74148f6 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 29 Mar 2023 14:56:53 +0200 Subject: [PATCH 2/5] Ensure that fence.i wait d$ inflight write and reschedule the next instruction --- src/main/scala/vexriscv/ip/DataCache.scala | 6 +++++- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 11 ++++++----- src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 9 +++++++++ 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index a2e43aa..17766c2 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -207,12 +207,14 @@ case class DataCacheCpuBus(p : DataCacheConfig, mmu : MemoryTranslatorBusParamet val redo = Bool() val flush = Stream(DataCacheFlush(p.lineCount)) + val writesPending = Bool() + override def asMaster(): Unit = { master(execute) master(memory) master(writeBack) master(flush) - in(redo) + in(redo, writesPending) } } @@ -717,6 +719,8 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam } val uncached = history.readAsync(rPtr.resized) val full = RegNext(wPtr - rPtr >= pendingMax-1) + val empty = wPtr === rPtr + io.cpu.writesPending := !empty io.cpu.execute.haltIt setWhen(full) } diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 8733901..2204a65 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -497,7 +497,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep object ENV_CTRL extends Stageable(EnvCtrlEnum()) object IS_CSR extends Stageable(Bool) - object IS_SFENCE_VMA extends Stageable(Bool) + object RESCHEDULE_NEXT extends Stageable(Bool) object CSR_WRITE_OPCODE extends Stageable(Bool) object CSR_READ_OPCODE extends Stageable(Bool) object PIPELINED_CSR_READ extends Stageable(Bits(32 bits)) @@ -639,8 +639,9 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep if(utimeAccess != CsrAccess.NONE) utime = in UInt(64 bits) setName("utime") if(supervisorGen) { - decoderService.addDefault(IS_SFENCE_VMA, False) - decoderService.add(SFENCE_VMA, List(IS_SFENCE_VMA -> True)) + decoderService.addDefault(RESCHEDULE_NEXT, False) + decoderService.add(SFENCE_VMA, List(RESCHEDULE_NEXT -> True)) + decoderService.add(FENCE_I, List(RESCHEDULE_NEXT -> True)) } xretAwayFromMachine = False @@ -1143,7 +1144,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep redoInterface.payload := decode.input(PC) val rescheduleNext = False - when(execute.arbitration.isValid && execute.input(IS_SFENCE_VMA)) { rescheduleNext := True } + when(execute.arbitration.isValid && execute.input(RESCHEDULE_NEXT)) { rescheduleNext := True } duringWrite(CSR.SATP) { rescheduleNext := True } when(rescheduleNext){ @@ -1581,7 +1582,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep if(!pipelineCsrRead) output(REGFILE_WRITE_DATA) := readData } - when(arbitration.isValid && (input(IS_CSR) || (if(supervisorGen) input(IS_SFENCE_VMA) else False))) { + when(arbitration.isValid && (input(IS_CSR) || (if(supervisorGen) input(RESCHEDULE_NEXT) else False))) { arbitration.haltItself setWhen(blockedBySideEffects) } diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index ea34213..623add8 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -160,6 +160,7 @@ class DBusCachedPlugin(val config : DataCacheConfig, object MEMORY_LRSC extends Stageable(Bool) object MEMORY_AMO extends Stageable(Bool) object MEMORY_FENCE extends Stageable(Bool) + object MEMORY_FENCE_WR extends Stageable(Bool) object MEMORY_FORCE_CONSTISTENCY extends Stageable(Bool) object IS_DBUS_SHARING extends Stageable(Bool()) object MEMORY_VIRTUAL_ADDRESS extends Stageable(UInt(32 bits)) @@ -267,6 +268,8 @@ class DBusCachedPlugin(val config : DataCacheConfig, case true => { decoderService.addDefault(MEMORY_FENCE, False) decoderService.add(FENCE, List(MEMORY_FENCE -> True)) + decoderService.addDefault(MEMORY_FENCE_WR, False) + decoderService.add(FENCE_I, List(MEMORY_FENCE_WR -> True)) } } @@ -405,6 +408,12 @@ class DBusCachedPlugin(val config : DataCacheConfig, ) } + if(withWriteResponse){ + when(arbitration.isValid && input(MEMORY_FENCE_WR) && cache.io.cpu.writesPending){ + arbitration.haltItself := True + } + } + if(tightlyGen){ tightlyCoupledAddressStage match { case false => From b4d5a315cf8a495ccf502c66453f7593d616ca0f Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 31 Mar 2023 10:11:53 +0200 Subject: [PATCH 3/5] CsrPlugin implement dummy pmp if no pmp is there --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 10 +++++----- src/test/cpp/regression/main.cpp | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 2204a65..afe3e6c 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -1692,11 +1692,11 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep } //When no PMP => -// if(!csrMapping.mapping.contains(0x3A0)){ -// when(arbitration.isValid && input(IS_CSR) && U(csrAddress) >= 0x3A0 && U(csrAddress) <= 0x3EF){ -// csrMapping.allowCsrSignal := True -// } -// } + if(!csrMapping.mapping.contains(0x3A0)){ + when(arbitration.isValid && input(IS_CSR) && (csrAddress(11 downto 2) ## B"00" === 0x3A0 || csrAddress(11 downto 4) ## B"0000" === 0x3B0)){ + csrMapping.allowCsrSignal := True + } + } illegalAccess clearWhen(csrMapping.allowCsrSignal) diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 3bbd26c..1f20d00 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -630,7 +630,7 @@ public: #endif default: { -// if(csr >= 0x3A0 && csr <= 0x3EF) break; //PMP + if(csr >= 0x3A0 && csr <= 0x3A3 || csr >= 0x3B0 && csr <= 0x3BF) break; //PMP return true; }break; } @@ -686,7 +686,7 @@ public: #endif default: { -// if(csr >= 0x3A0 && csr <= 0x3EF) break; //PMP + if(csr >= 0x3A0 && csr <= 0x3A3 || csr >= 0x3B0 && csr <= 0x3BF) break; //PMP ilegalInstruction(); return true; }break; From cb0bacfce981491b1093940b9bd5452cba58db3a Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 31 Mar 2023 10:12:15 +0200 Subject: [PATCH 4/5] implement dummy pmp as 1.10 spec says --- src/test/cpp/raw/privSpec/build/privSpec.hex | 142 +++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 src/test/cpp/raw/privSpec/build/privSpec.hex diff --git a/src/test/cpp/raw/privSpec/build/privSpec.hex b/src/test/cpp/raw/privSpec/build/privSpec.hex new file mode 100644 index 0000000..e8dd426 --- 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+:10082000B74000007390003073103000F3200030A8 +:1008300037610080B3F0200063942004B7400000CB +:100840007390003073102000F32000303761008077 +:10085000B3F0200063962002B74000007390003090 +:1008600073101000F320003037610080B3F02000D7 +:1008700063982000B7400000739000306F000001C3 +:10088000370110F0130141F22320C101370110F0AC +:10089000130101F2232001001300000013000000E7 +:1008A00013000000130000001300000013000000FC +:0808B000000000400000000000 +:00000001FF From 95e61a7951b5f46bed3e2fbd09da87d13ebd91f4 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 4 Apr 2023 11:47:49 +0200 Subject: [PATCH 5/5] Revert CfuPlugin --- .../scala/vexriscv/plugin/CfuPlugin.scala | 52 ++++++------------- 1 file changed, 17 insertions(+), 35 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CfuPlugin.scala b/src/main/scala/vexriscv/plugin/CfuPlugin.scala index 2e878ea..00b720d 100644 --- a/src/main/scala/vexriscv/plugin/CfuPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CfuPlugin.scala @@ -1,6 +1,6 @@ package vexriscv.plugin -import vexriscv.{DecoderService, ExceptionCause, ExceptionService, JumpService, Stage, Stageable, VexRiscv} +import vexriscv.{DecoderService, ExceptionCause, ExceptionService, Stage, Stageable, VexRiscv} import spinal.core._ import spinal.lib._ import spinal.lib.bus.bmb.WeakConnector @@ -92,9 +92,7 @@ object CfuPlugin{ case class CfuPluginEncoding(instruction : MaskedLiteral, functionId : List[Range], - input2Kind : CfuPlugin.Input2Kind.E, - withCmd : Boolean = true, - withRsp : Boolean = true){ + input2Kind : CfuPlugin.Input2Kind.E){ val functionIdWidth = functionId.map(_.size).sum } @@ -113,7 +111,6 @@ class CfuPlugin(val stageCount : Int, // assert(p.CFU_FUNCTION_ID_W == 3) var bus : CfuBus = null -// var redoInterface : Flow[UInt] = null lazy val forkStage = pipeline.execute lazy val joinStage = pipeline.stages(Math.min(pipeline.stages.length - 1, pipeline.indexOf(forkStage) + stageCount)) @@ -123,45 +120,31 @@ class CfuPlugin(val stageCount : Int, val CFU_IN_FLIGHT = new Stageable(Bool()).setCompositeName(this, "CFU_IN_FLIGHT") val CFU_ENCODING = new Stageable(UInt(log2Up(encodings.size) bits)).setCompositeName(this, "CFU_ENCODING") val CFU_INPUT_2_KIND = new Stageable(CfuPlugin.Input2Kind()).setCompositeName(this, "CFU_INPUT_2_KIND") - val CFU_WITH_CMD = new Stageable(Bool()).setCompositeName(this, "CFU_WITH_CMD") - val CFU_WITH_RSP = new Stageable(Bool()).setCompositeName(this, "CFU_WITH_RSP") override def setup(pipeline: VexRiscv): Unit = { import pipeline._ import pipeline.config._ -// val pcManagerService = pipeline.service(classOf[JumpService]) -// if(encodings.contains(_.cmd)redoInterface = pcManagerService.createJumpInterface(pipeline.writeBack) - bus = master(CfuBus(p)) val decoderService = pipeline.service(classOf[DecoderService]) decoderService.addDefault(CFU_ENABLE, False) - decoderService.addDefault(CFU_WITH_CMD, False) - decoderService.addDefault(CFU_WITH_RSP, False) for((encoding, id) <- encodings.zipWithIndex){ - var actions : List[(Stageable[_ <: BaseType], Any)] = List( + var actions = List( CFU_ENABLE -> True, + REGFILE_WRITE_VALID -> True, + BYPASSABLE_EXECUTE_STAGE -> Bool(stageCount == 0), + BYPASSABLE_MEMORY_STAGE -> Bool(stageCount <= 1), + RS1_USE -> True, CFU_ENCODING -> U(id), - CFU_WITH_CMD -> Bool(encoding.withCmd), - CFU_WITH_RSP -> Bool(encoding.withRsp) + CFU_INPUT_2_KIND -> encoding.input2Kind() ) - if(encoding.withCmd){ - actions :+= RS1_USE -> True - actions :+= CFU_INPUT_2_KIND -> encoding.input2Kind() - encoding.input2Kind match { - case CfuPlugin.Input2Kind.RS => - actions :+= RS2_USE -> True - case CfuPlugin.Input2Kind.IMM_I => - } - } - - if(encoding.withRsp){ - actions :+= REGFILE_WRITE_VALID -> True - actions :+= BYPASSABLE_EXECUTE_STAGE -> Bool(stageCount == 0) - actions :+= BYPASSABLE_MEMORY_STAGE -> Bool(stageCount <= 1) + encoding.input2Kind match { + case CfuPlugin.Input2Kind.RS => + actions :+= RS2_USE -> True + case CfuPlugin.Input2Kind.IMM_I => } decoderService.add( @@ -208,7 +191,7 @@ class CfuPlugin(val stageCount : Int, import forkStage._ input(CFU_ENABLE).clearWhen(!input(LEGAL_INSTRUCTION)) val hazard = stages.dropWhile(_ != forkStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR - val scheduleWish = arbitration.isValid && input(CFU_ENABLE) && input(CFU_WITH_CMD) + val scheduleWish = arbitration.isValid && input(CFU_ENABLE) val schedule = scheduleWish && !hazard arbitration.haltItself setWhen(scheduleWish && hazard) @@ -251,13 +234,12 @@ class CfuPlugin(val stageCount : Int, bus.rsp.combStage() } - val hazard = stages.dropWhile(_ != joinStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR rsp.ready := False - when((arbitration.isValid || input(CFU_IN_FLIGHT)) && input(CFU_WITH_RSP)){ - arbitration.haltItself setWhen(!rsp.valid || hazard) - rsp.ready := !arbitration.isStuckByOthers && !hazard + when(input(CFU_IN_FLIGHT)){ + arbitration.haltItself setWhen(!rsp.valid) + rsp.ready := !arbitration.isStuckByOthers output(REGFILE_WRITE_DATA) := rsp.outputs(0) - if(p.CFU_WITH_STATUS) when(rsp.fire){ + if(p.CFU_WITH_STATUS) when(arbitration.isFiring){ switch(rsp.status) { for (i <- 1 to 6) is(i) { csr.status.flags(i-1) := True