From f46ad43f393cd345ca0f81ed716eaddcb7d76e4b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 10 Jan 2022 13:39:41 +0100 Subject: [PATCH] DataCache.withInternalLrSc reserved clearing fix --- src/main/scala/vexriscv/ip/DataCache.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index c5e2487..43bb919 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -864,8 +864,8 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam val lrSc = withInternalLrSc generate new Area{ val reserved = RegInit(False) - when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.isLrsc){ - reserved := !request.wr + when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.wr){ + reserved := False } } @@ -1167,4 +1167,4 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam s1.invalidations := RegNextWhen((input.valid && input.enable && input.address(lineRange) === s0.input.address(lineRange)) ? wayHits | 0, s0.input.ready) } } -} \ No newline at end of file +}