From 3e17461cc71c226f6a02df0e2d3d52554ef53f28 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 16 Sep 2018 11:00:56 +0200 Subject: [PATCH 01/56] Add optional XIP to Murax --- build.sbt | 56 ++++++++++++------ src/main/scala/vexriscv/demo/Murax.scala | 58 +++++++++++++++---- .../scala/vexriscv/demo/MuraxUtiles.scala | 4 +- 3 files changed, 89 insertions(+), 29 deletions(-) diff --git a/build.sbt b/build.sbt index 499e838..7569f96 100644 --- a/build.sbt +++ b/build.sbt @@ -1,22 +1,44 @@ -name := "VexRiscv" - -organization := "com.github.spinalhdl" - -version := "1.0.0" - -scalaVersion := "2.11.6" - -EclipseKeys.withSource := true - -libraryDependencies ++= Seq( - "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.0", - "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.0", - "org.scalatest" % "scalatest_2.11" % "2.2.1", - "org.yaml" % "snakeyaml" % "1.8" -) +//name := "VexRiscv" +// +//organization := "com.github.spinalhdl" +// +//version := "1.0.0" +// +//scalaVersion := "2.11.6" +// +//EclipseKeys.withSource := true +// +//libraryDependencies ++= Seq( +// "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.1", +// "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.1", +// "org.scalatest" % "scalatest_2.11" % "2.2.1", +// "org.yaml" % "snakeyaml" % "1.8" +//) +// +// +// +//addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2") +//scalacOptions += "-P:continuations:enable" +//fork := true +lazy val root = (project in file(".")). + settings( + inThisBuild(List( + organization := "com.github.spinalhdl", + scalaVersion := "2.11.6", + version := "1.0.0" + )), + libraryDependencies ++= Seq( + "org.scalatest" % "scalatest_2.11" % "2.2.1", + "org.yaml" % "snakeyaml" % "1.8" + ), + name := "VexRiscv" + ).dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib) +lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "SpinalHDL-sim") +lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "SpinalHDL-core") +lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "SpinalHDL-lib") addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2") scalacOptions += "-P:continuations:enable" -fork := true +fork := true \ No newline at end of file diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index b492397..aac654f 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -5,13 +5,14 @@ import spinal.lib._ import spinal.lib.bus.amba3.apb._ import spinal.lib.bus.misc.SizeMapping import spinal.lib.com.jtag.Jtag +import spinal.lib.com.spi.ddr.SpiDdrMaster import spinal.lib.com.uart._ import spinal.lib.io.{InOutWrapper, TriStateArray} import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer} import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal} import vexriscv.plugin._ import vexriscv.{VexRiscv, VexRiscvConfig, plugin} - +import spinal.lib.com.spi.ddr._ import scala.collection.mutable.ArrayBuffer /** @@ -38,10 +39,21 @@ case class MuraxConfig(coreFrequency : HertzNumber, pipelineApbBridge : Boolean, gpioWidth : Int, uartCtrlConfig : UartCtrlMemoryMappedConfig, + xipConfig : SpiDdrMasterCtrl.MemoryMappingParameters, cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){ require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions") + val genXpi = xipConfig != null + + def addXip(): MuraxConfig = copy(xipConfig = SpiDdrMasterCtrl.MemoryMappingParameters( + SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(4, 1)).addAllMods(), + cmdFifoDepth = 32, + rspFifoDepth = 32, + xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32) + )) } + + object MuraxConfig{ def default = MuraxConfig( coreFrequency = 12 MHz, @@ -51,6 +63,7 @@ object MuraxConfig{ pipelineMainBus = false, pipelineApbBridge = true, gpioWidth = 32, + xipConfig = null, cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel new IBusSimplePlugin( resetVector = 0x80000000l, @@ -146,6 +159,8 @@ case class Murax(config : MuraxConfig) extends Component{ //Peripherals IO val gpioA = master(TriStateArray(gpioWidth bits)) val uart = master(Uart()) + + val xpi = ifGen(genXpi)(master(SpiDdrMaster(xipConfig.ctrl.spi))) } @@ -232,11 +247,13 @@ case class Murax(config : MuraxConfig) extends Component{ //****** MainBus slaves ******** + val mainBusMapping = ArrayBuffer[(SimpleBus,SizeMapping)]() val ram = new MuraxSimpleBusRam( onChipRamSize = onChipRamSize, onChipRamHexFile = onChipRamHexFile, simpleBusConfig = simpleBusConfig ) + mainBusMapping += ram.io.bus -> (0x80000000l, onChipRamSize) val apbBridge = new MuraxSimpleBusToApbBridge( apb3Config = Apb3Config( @@ -246,39 +263,54 @@ case class Murax(config : MuraxConfig) extends Component{ pipelineBridge = pipelineApbBridge, simpleBusConfig = simpleBusConfig ) + mainBusMapping += apbBridge.io.simpleBus -> (0xF0000000l, 1 MB) //******** APB peripherals ********* + val apbMapping = ArrayBuffer[(Apb3, SizeMapping)]() val gpioACtrl = Apb3Gpio(gpioWidth = gpioWidth) io.gpioA <> gpioACtrl.io.gpio + apbMapping += gpioACtrl.io.apb -> (0x00000, 4 kB) val uartCtrl = Apb3UartCtrl(uartCtrlConfig) uartCtrl.io.uart <> io.uart externalInterrupt setWhen(uartCtrl.io.interrupt) + apbMapping += uartCtrl.io.apb -> (0x10000, 4 kB) val timer = new MuraxApb3Timer() timerInterrupt setWhen(timer.io.interrupt) + apbMapping += timer.io.apb -> (0x20000, 4 kB) + + val xpi = ifGen(genXpi)(new Area{ + val ctrl = Apb3SpiDdrMasterCtrl(xipConfig) + ctrl.io.spi <> io.xpi + externalInterrupt setWhen(ctrl.io.interrupt) + apbMapping += ctrl.io.apb -> (0x1F000, 4 kB) + + val accessBus = new SimpleBus(SimpleBusConfig(24,32)) + mainBusMapping += accessBus -> (0x90000000l, 16 MB) + + ctrl.io.xip.cmd.valid <> (accessBus.cmd.valid && !accessBus.cmd.wr) + ctrl.io.xip.cmd.ready <> accessBus.cmd.ready + ctrl.io.xip.cmd.payload <> accessBus.cmd.address + + ctrl.io.xip.rsp.valid <> accessBus.rsp.valid + ctrl.io.xip.rsp.payload <> accessBus.rsp.data + }) //******** Memory mappings ********* val apbDecoder = Apb3Decoder( master = apbBridge.io.apb, - slaves = List[(Apb3, SizeMapping)]( - gpioACtrl.io.apb -> (0x00000, 4 kB), - uartCtrl.io.apb -> (0x10000, 4 kB), - timer.io.apb -> (0x20000, 4 kB) - ) + slaves = apbMapping ) val mainBusDecoder = new Area { val logic = new MuraxSimpleBusDecoder( master = mainBusArbiter.io.masterBus, - specification = List[(SimpleBus,SizeMapping)]( - ram.io.bus -> (0x80000000l, onChipRamSize), - apbBridge.io.simpleBus -> (0xF0000000l, 1 MB) - ), + specification = mainBusMapping, pipelineMaster = pipelineMainBus ) } @@ -293,6 +325,12 @@ object Murax{ } } +object MuraxWithXip{ + def main(args: Array[String]) { + SpinalVerilog(Murax(MuraxConfig.default.addXip())) + } +} + object MuraxDhrystoneReady{ def main(args: Array[String]) { SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB))) diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala index 8aaf8a0..8d60db5 100644 --- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala +++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala @@ -130,7 +130,7 @@ class MuraxSimpleBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean } } -class MuraxSimpleBusDecoder(master : SimpleBus, val specification : List[(SimpleBus,SizeMapping)], pipelineMaster : Boolean) extends Area{ +class MuraxSimpleBusDecoder(master : SimpleBus, val specification : Seq[(SimpleBus,SizeMapping)], pipelineMaster : Boolean) extends Area{ val masterPipelined = SimpleBus(master.config) if(!pipelineMaster) { masterPipelined.cmd << master.cmd @@ -146,7 +146,7 @@ class MuraxSimpleBusDecoder(master : SimpleBus, val specification : List[(Simple val hits = for((slaveBus, memorySpace) <- specification) yield { val hit = memorySpace.hit(masterPipelined.cmd.address) slaveBus.cmd.valid := masterPipelined.cmd.valid && hit - slaveBus.cmd.payload := masterPipelined.cmd.payload + slaveBus.cmd.payload := masterPipelined.cmd.payload.resized hit } val noHit = !hits.orR From b51ac03a5eea22da8c55dfb2d4e2e96f6b240992 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 18 Sep 2018 16:53:26 +0200 Subject: [PATCH 02/56] murax xip flash integration wip --- .../iCE40-hx8k_breakout_board_xip/Makefile | 38 ++++++++ .../iCE40-hx8k_breakout_board_xip/README.md | 84 ++++++++++++++++++ .../img/cram-programming-config.png | Bin 0 -> 814776 bytes .../img/iCE40HX8K-breakout-revA.png | Bin 0 -> 40253 bytes .../toplevel.pcf | 23 +++++ .../iCE40-hx8k_breakout_board_xip/toplevel.v | 76 ++++++++++++++++ src/main/scala/vexriscv/demo/Murax.scala | 2 +- src/test/scala/vexriscv/MuraxSim.scala | 6 +- 8 files changed, 226 insertions(+), 3 deletions(-) create mode 100644 scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile create mode 100644 scripts/Murax/iCE40-hx8k_breakout_board_xip/README.md create mode 100644 scripts/Murax/iCE40-hx8k_breakout_board_xip/img/cram-programming-config.png create mode 100644 scripts/Murax/iCE40-hx8k_breakout_board_xip/img/iCE40HX8K-breakout-revA.png create mode 100644 scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.pcf create mode 100644 scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile b/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile new file mode 100644 index 0000000..309e0df --- /dev/null +++ b/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile @@ -0,0 +1,38 @@ + + +VERILOG = ../../../Murax.v toplevel.v + +generate : + #(cd ../../..; sbt "run-main vexriscv.demo.MuraxWithXip") + +../../../Murax.v : + #(cd ../../..; sbt "run-main vexriscv.demo.MuraxWithXip") + +../../../Murax.v*.bin: + +bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin + mkdir -p bin + rm -f Murax.v*.bin + cp ../../../Murax.v*.bin . | true + yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG} + +bin/toplevel.asc : toplevel.pcf bin/toplevel.blif + arachne-pnr -p toplevel.pcf -d 8k --max-passes 600 -P ct256 bin/toplevel.blif -o bin/toplevel.asc + +bin/toplevel.bin : bin/toplevel.asc + icepack bin/toplevel.asc bin/toplevel.bin + +compile : bin/toplevel.bin + +time: bin/toplevel.bin + icetime -tmd hx8k bin/toplevel.asc + +prog : bin/toplevel.bin + iceprog -S bin/toplevel.bin + +sudo-prog : bin/toplevel.bin + sudo iceprog -S bin/toplevel.bin + +clean : + rm -rf bin + rm -f Murax.v*.bin diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/README.md b/scripts/Murax/iCE40-hx8k_breakout_board_xip/README.md new file mode 100644 index 0000000..62078a3 --- /dev/null +++ b/scripts/Murax/iCE40-hx8k_breakout_board_xip/README.md @@ -0,0 +1,84 @@ +This example is for the +[Lattice iCE40HX-8K Breakout Board](http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx). + +An image of this board is shown below; +![img/iCE40HX8K-breakout-revA.png] + +This board can be purchased for ~$USD 49 directly from Lattice and is supported +by the IceStorm +[`iceprog`](https://github.com/cliffordwolf/icestorm/tree/master/iceprog) tool. + + +# Using the example + +## Before Starting + +Before starting make sure that your board is configured for `CRAM Programming` +mode. This requires removing jumper `J7` and putting the pair of jumpers on +`J6` to be parallel to the text on the board. + +This is shown in **Figure 5** of the +[iCE40HX-8K Breakout Board User Guide](http://www.latticesemi.com/view_document?document_id=50373). +which is also reproduced below; +![img/cram-programming-config.png] + +Once your board is ready, you should follow the setup instructions at the +[top level](../../../README.md). + +You should make sure you have the following tools installed; + * Yosys + * arachne-pnr + * icestorm tools (like icepack and iceprog) + * riscv toolchain + * sbt + +## Building + +You should be able to just type `make compile` and get output similar to this; +``` +... + place time 10.14s +route... + pass 1, 15 shared. + pass 2, 4 shared. + pass 3, 1 shared. + pass 4, 0 shared. + +After routing: +span_4 4406 / 29696 +span_12 951 / 5632 + + route time 9.12s +write_txt bin/toplevel.asc... +icepack bin/toplevel.asc bin/toplevel.bin +``` + +The process should take around 30 seconds on a reasonable fast computer. + +## Programming + +After building you should be able to run `make prog`. You may need to run `make +sudo-prog` if root is needed to access your USB devices. + +You should get output like the following; +``` +iceprog -S bin/toplevel.bin +init.. +cdone: high +reset.. +cdone: low +programming.. +cdone: high +Bye. +``` + +After programming the LEDs at the top of the board should start flashing in an +interesting pattern. + +## Connect + +After programming you should be able to connect to the serial port and have the +output echoed back to you. + +On Linux you can do this using a command like `screen /dev/ttyUSB1`. Then as +you type you should get back the same characters. diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/cram-programming-config.png b/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/cram-programming-config.png new file mode 100644 index 0000000000000000000000000000000000000000..48562bb4578cb57f857b8fefb1fcf3abf2366f9d GIT binary patch literal 814776 zcmce+V~}P+vo89!?e1yY)6=$XYudJL+qP}nwr$(C&wTsD-f`}a{rBct6)P$uE2CCb zW<_S!6DB7k3I~k^4FCY(#KnXZ007{ce{BU4{2!+Pv5fxT2V7rLR0#0%pC`AgB;g+i z%2rIx0RVs>{7(Z)qJqc%$AoYcmllTDhd=|Op*kGCoB7AWHB(Y`6tuCjGO~93*98Cs z?Tz#tjSLA~%p6S#M8&1$3~7uY0007jxDdaR>-wdaizm*|+c#r_hs*hr)^&0RHF_2u zMr|FvZtWQ;FrgnGFkx)0oB%Sg4x~6m4;v^j6rmqtI*J5Aqnv+PvA8|h#ISJlW`v=W z)>_uf%SiKDM}lKN0|tXE4?6Lgv-3D7P1x;LRC|`{t+2r zpC-iL6!+!1vmb~Zc!O!g-7zY}i^NFOUH49&_aADxF4iOLC7)m$(f~-^^{Av*vA7k` z=~v3^_otk?#qCv&kYJ#ZZ^RX9ob?Gb)Bbdm>!B-`%?KawR**SV!6{%bdGBwy){Eu| z`UZSiRAesKV@S`RCCK&!kZ=;WaKa0XC4ed#6WOS@1I+Tq6VItgDC-AZ@Rmd|q+RkWLG9S7U- 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100644 index 0000000..4962e25 --- /dev/null +++ b/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.pcf @@ -0,0 +1,23 @@ +## iCE40-hx8k breakout board + +set_io io_J3 J3 +set_io io_H16 H16 +set_io io_G15 G15 +set_io io_G16 G16 +set_io io_F15 F15 +set_io io_B12 B12 +set_io io_B10 B10 +set_io io_led[0] B5 +set_io io_led[1] B4 +set_io io_led[2] A2 +set_io io_led[3] A1 +set_io io_led[4] C5 +set_io io_led[5] C4 +set_io io_led[6] B3 +set_io io_led[7] C3 + +#XIP +set_io io_P12 P12 +set_io io_P11 P11 +set_io io_R11 R11 +set_io io_R12 R12 \ No newline at end of file diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v b/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v new file mode 100644 index 0000000..db884cc --- /dev/null +++ b/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps + +module toplevel( + input io_J3, + input io_H16, + input io_G15, + output io_G16, + input io_F15, + output io_B12, + input io_B10, + + input io_P12, + output io_P11, + output io_R11, + output io_R12, + + output [7:0] io_led + + ); + + wire [31:0] io_gpioA_read; + wire [31:0] io_gpioA_write; + wire [31:0] io_gpioA_writeEnable; + wire io_mainClk; + wire io_jtag_tck; + + SB_GB mainClkBuffer ( + .USER_SIGNAL_TO_GLOBAL_BUFFER (io_J3), + .GLOBAL_BUFFER_OUTPUT ( io_mainClk) + ); + + SB_GB jtagClkBuffer ( + .USER_SIGNAL_TO_GLOBAL_BUFFER (io_H16), + .GLOBAL_BUFFER_OUTPUT ( io_jtag_tck) + ); + + assign io_led = io_gpioA_write[7 : 0]; + + + wire [1:0] io_xpi_sclk_write; + wire io_xpi_data_0_writeEnable; + wire [1:0] io_xpi_data_0_read; + wire [1:0] io_xpi_data_0_write; + wire io_xpi_data_1_writeEnable; + wire [1:0] io_xpi_data_1_read; + wire [1:0] io_xpi_data_1_write; + wire [0:0] io_xpi_ss; + + assign io_P11 = io_xpi_data_0_write[0]; + assign io_xpi_data_1_read[0] = io_P12; + assign io_xpi_data_1_read[1] = io_P12; + assign io_R11 = io_xpi_sclk_write[0]; + assign io_R12 = io_xpi_ss[0]; + + Murax murax ( + .io_asyncReset(0), + .io_mainClk (io_mainClk ), + .io_jtag_tck(io_jtag_tck), + .io_jtag_tdi(io_G15), + .io_jtag_tdo(io_G16), + .io_jtag_tms(io_F15), + .io_gpioA_read (io_gpioA_read), + .io_gpioA_write (io_gpioA_write), + .io_gpioA_writeEnable(io_gpioA_writeEnable), + .io_uart_txd(io_B12), + .io_uart_rxd(io_B10), + .io_xpi_sclk_write(io_xpi_sclk_write), + .io_xpi_data_0_writeEnable(io_xpi_data_0_writeEnable), + .io_xpi_data_0_read(io_xpi_data_0_read), + .io_xpi_data_0_write(io_xpi_data_0_write), + .io_xpi_data_1_writeEnable(io_xpi_data_1_writeEnable), + .io_xpi_data_1_read(io_xpi_data_1_read), + .io_xpi_data_1_write(io_xpi_data_1_write), + .io_xpi_ss(io_xpi_ss) + ); +endmodule \ No newline at end of file diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index aac654f..df82e83 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -45,7 +45,7 @@ case class MuraxConfig(coreFrequency : HertzNumber, val genXpi = xipConfig != null def addXip(): MuraxConfig = copy(xipConfig = SpiDdrMasterCtrl.MemoryMappingParameters( - SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(4, 1)).addAllMods(), + SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(2, 1)).addAllMods(), cmdFifoDepth = 32, rspFifoDepth = 32, xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32) diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala index 46131cd..4d65b63 100644 --- a/src/test/scala/vexriscv/MuraxSim.scala +++ b/src/test/scala/vexriscv/MuraxSim.scala @@ -20,8 +20,8 @@ import scala.collection.mutable object MuraxSim { def main(args: Array[String]): Unit = { // def config = MuraxConfig.default.copy(onChipRamSize = 256 kB) - def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex") - + def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex").addXip() + val simSlowDown = true SimConfig.allOptimisation.withWave.compile(new Murax(config)).doSimUntilVoid{dut => val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong val jtagClkPeriod = mainClkPeriod*4 @@ -47,6 +47,7 @@ object MuraxSim { baudPeriod = uartBaudPeriod ) + if(config.xipConfig != null)dut.io.xpi.data(1).read #= 0 val guiThread = fork{ val guiToSim = mutable.Queue[Any]() @@ -101,6 +102,7 @@ object MuraxSim { dut.io.gpioA.read #= (dut.io.gpioA.write.toLong & dut.io.gpioA.writeEnable.toLong) | (switchValue() << 8) ledsValue = dut.io.gpioA.write.toLong ledsFrame.repaint() + if(simSlowDown) Thread.sleep(400) } } } From ff1d1072a7dd600dc31191554b023d808f94ae8f Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 19 Sep 2018 00:09:14 +0200 Subject: [PATCH 03/56] XIP is physicaly working on murax --- .../iCE40-hx8k_breakout_board_xip/toplevel.v | 10 +- src/main/c/murax/xipBootloader/.gitignore | 6 ++ src/main/c/murax/xipBootloader/crt.S | 54 +++++++++++ src/main/c/murax/xipBootloader/demo.S | 24 +++++ src/main/c/murax/xipBootloader/makefile | 23 +++++ src/main/c/murax/xipBootloader/mapping.ld | 96 +++++++++++++++++++ src/main/scala/vexriscv/demo/Murax.scala | 29 +++--- .../scala/vexriscv/demo/MuraxUtiles.scala | 23 +++++ src/test/scala/vexriscv/MuraxSim.scala | 2 +- 9 files changed, 249 insertions(+), 18 deletions(-) create mode 100644 src/main/c/murax/xipBootloader/.gitignore create mode 100644 src/main/c/murax/xipBootloader/crt.S create mode 100644 src/main/c/murax/xipBootloader/demo.S create mode 100644 src/main/c/murax/xipBootloader/makefile create mode 100644 src/main/c/murax/xipBootloader/mapping.ld diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v b/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v index db884cc..5034de8 100644 --- a/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v +++ b/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v @@ -9,8 +9,8 @@ module toplevel( output io_B12, input io_B10, - input io_P12, - output io_P11, + output io_P12, + input io_P11, output io_R11, output io_R12, @@ -46,9 +46,9 @@ module toplevel( wire [1:0] io_xpi_data_1_write; wire [0:0] io_xpi_ss; - assign io_P11 = io_xpi_data_0_write[0]; - assign io_xpi_data_1_read[0] = io_P12; - assign io_xpi_data_1_read[1] = io_P12; + assign io_P12 = io_xpi_data_0_write[0]; + assign io_xpi_data_1_read[0] = io_P11; + assign io_xpi_data_1_read[1] = io_P11; assign io_R11 = io_xpi_sclk_write[0]; assign io_R12 = io_xpi_ss[0]; diff --git a/src/main/c/murax/xipBootloader/.gitignore b/src/main/c/murax/xipBootloader/.gitignore new file mode 100644 index 0000000..ca41ed2 --- /dev/null +++ b/src/main/c/murax/xipBootloader/.gitignore @@ -0,0 +1,6 @@ +*.bin +*.elf +*.map +*.d +*.asm +*.o \ No newline at end of file diff --git a/src/main/c/murax/xipBootloader/crt.S b/src/main/c/murax/xipBootloader/crt.S new file mode 100644 index 0000000..178f788 --- /dev/null +++ b/src/main/c/murax/xipBootloader/crt.S @@ -0,0 +1,54 @@ +#define CTRL_BASE 0xF001F000 +#define XIP_BASE 0xE0040000 +#define CTRL_DATA 0x00 +#define CTRL_STATUS 0x04 +#define CTRL_MODE 0x08 +#define CTRL_RATE 0x20 +#define CTRL_SS_SETUP 0x24 +#define CTRL_SS_HOLD 0x28 +#define CTRL_SS_DISABLE 0x2C + +#define CTRL_XIP_CONFIG 0x40 +#define CTRL_XIP_MODE 0x44 + +.global crtStart +.global main + +#define CTRL x31 + +crtStart: + li x31, CTRL_BASE + sw x0, CTRL_MODE(CTRL) + li t0, 2 + sw t0, CTRL_RATE(CTRL) + li t0, 4 + sw t0, CTRL_SS_SETUP(CTRL) + sw t0, CTRL_SS_HOLD(CTRL) + sw t0, CTRL_SS_DISABLE(CTRL) + + + li a0, 0x880 + call spiWrite + li a0, 0x181 + call spiWrite + li a0, 0x183 + call spiWrite + li a0, 0x800 + call spiWrite + + + li t0, 0x00FF010B + sw t0, CTRL_XIP_MODE(CTRL) + li t0, 0x1 + sw t0, CTRL_XIP_CONFIG(CTRL) + li t0, XIP_BASE + jr t0 + + +spiWrite: + sw a0,CTRL_DATA(CTRL) +spiWrite_wait: + lw t0,CTRL_STATUS(CTRL) + srli t0,t0,0x10 + beqz t0,spiWrite_wait + ret diff --git a/src/main/c/murax/xipBootloader/demo.S b/src/main/c/murax/xipBootloader/demo.S new file mode 100644 index 0000000..34d02b1 --- /dev/null +++ b/src/main/c/murax/xipBootloader/demo.S @@ -0,0 +1,24 @@ +#define GPIO_BASE 0xF0000000 +#define GPIO_OUTPUT 4 +#define GPIO_OUTPUT_ENABLE 8 + + +.global crtStart + +crtStart: + + + li x31, GPIO_BASE + li t0, 0x000000FF + sw t0, GPIO_OUTPUT_ENABLE(x31) + + li t0,0 +redo: + sw t0, GPIO_OUTPUT(x31) + li t1,10000 + addi t0,t0,1 +loop: + addi t1,t1,-1 + bnez t1, loop + j redo + diff --git a/src/main/c/murax/xipBootloader/makefile b/src/main/c/murax/xipBootloader/makefile new file mode 100644 index 0000000..56b8ab8 --- /dev/null +++ b/src/main/c/murax/xipBootloader/makefile @@ -0,0 +1,23 @@ +CFLAGS= -march=rv32i -mabi=ilp32 -g -O3 -MD +LFLAGS= -nostdlib -mcmodel=medany -nostartfiles -ffreestanding -fPIC -fPIE + + +all: crt.S demo.S + riscv64-unknown-elf-gcc -c $(CFLAGS) -o crt.o crt.S + riscv64-unknown-elf-gcc $(CFLAGS) -o crt.elf crt.o $(LFLAGS) -Wl,-Bstatic,-T,mapping.ld,-Map,crt.map,--print-memory-usage + riscv64-unknown-elf-objdump -S -d crt.elf > crt.asm + riscv64-unknown-elf-objcopy -O binary crt.elf crt.bin + + riscv64-unknown-elf-gcc -c $(CFLAGS) -o demo.o demo.S + riscv64-unknown-elf-gcc $(CFLAGS) -o demo.elf demo.o $(LFLAGS) -Wl,-Bstatic,-T,mapping.ld,-Map,demo.map,--print-memory-usage + riscv64-unknown-elf-objdump -S -d demo.elf > demo.asm + riscv64-unknown-elf-objcopy -O binary demo.elf demo.bin + + + +clean: + rm -f *.o + rm -f *.bin + rm -f *.elf + rm -f *.asm + rm -f *.map \ No newline at end of file diff --git a/src/main/c/murax/xipBootloader/mapping.ld b/src/main/c/murax/xipBootloader/mapping.ld new file mode 100644 index 0000000..cc1b070 --- /dev/null +++ b/src/main/c/murax/xipBootloader/mapping.ld @@ -0,0 +1,96 @@ +/* +This is free and unencumbered software released into the public domain. + +Anyone is free to copy, modify, publish, use, compile, sell, or +distribute this software, either in source code form or as a compiled +binary, for any purpose, commercial or non-commercial, and by any +means. +*/ +OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") +OUTPUT_ARCH(riscv) +ENTRY(crtStart) + +MEMORY { + mem : ORIGIN = 0x80000000, LENGTH = 0x00000400 +} + +_stack_size = DEFINED(_stack_size) ? _stack_size : 0; + +SECTIONS { + + .vector : { + *crt.o(.text); + } > mem + + .memory : { + *(.text); + end = .; + } > mem + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } > mem + + .ctors : + { + . = ALIGN(4); + _ctors_start = .; + KEEP(*(.init_array*)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + . = ALIGN(4); + _ctors_end = .; + } > mem + + .data : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } > mem + + .bss (NOLOAD) : { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _bss_start = .; + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > mem + + .noinit (NOLOAD) : { + . = ALIGN(4); + *(.noinit .noinit.*) + . = ALIGN(4); + } > mem + + ._stack (NOLOAD): + { + . = ALIGN(16); + PROVIDE (_stack_end = .); + . = . + _stack_size; + . = ALIGN(16); + PROVIDE (_stack_start = .); + } > mem + +} + diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index df82e83..2716e04 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -44,18 +44,13 @@ case class MuraxConfig(coreFrequency : HertzNumber, require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions") val genXpi = xipConfig != null - def addXip(): MuraxConfig = copy(xipConfig = SpiDdrMasterCtrl.MemoryMappingParameters( - SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(2, 1)).addAllMods(), - cmdFifoDepth = 32, - rspFifoDepth = 32, - xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32) - )) } object MuraxConfig{ - def default = MuraxConfig( + def default : MuraxConfig = default(false) + def default(withXip : Boolean) = MuraxConfig( coreFrequency = 12 MHz, onChipRamSize = 8 kB, onChipRamHexFile = null, @@ -63,10 +58,15 @@ object MuraxConfig{ pipelineMainBus = false, pipelineApbBridge = true, gpioWidth = 32, - xipConfig = null, + xipConfig = ifGen(withXip) (SpiDdrMasterCtrl.MemoryMappingParameters( + SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(2, 1)).addAllMods(), + cmdFifoDepth = 32, + rspFifoDepth = 32, + xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32) + )), cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel new IBusSimplePlugin( - resetVector = 0x80000000l, + resetVector = if(withXip) 0xF001E000l else 0x80000000l, relaxedPcCalculation = true, prediction = NONE, catchAccessFault = false, @@ -224,7 +224,9 @@ case class Murax(config : MuraxConfig) extends Component{ val timerInterrupt = False val externalInterrupt = False for(plugin <- cpu.plugins) plugin match{ - case plugin : IBusSimplePlugin => mainBusArbiter.io.iBus <> plugin.iBus + case plugin : IBusSimplePlugin => + mainBusArbiter.io.iBus.cmd <> plugin.iBus.cmd.halfPipe() //TODO !! + mainBusArbiter.io.iBus.rsp <> plugin.iBus.rsp case plugin : DBusSimplePlugin => { if(!pipelineDBus) mainBusArbiter.io.dBus <> plugin.dBus @@ -289,7 +291,7 @@ case class Murax(config : MuraxConfig) extends Component{ apbMapping += ctrl.io.apb -> (0x1F000, 4 kB) val accessBus = new SimpleBus(SimpleBusConfig(24,32)) - mainBusMapping += accessBus -> (0x90000000l, 16 MB) + mainBusMapping += accessBus -> (0xE0000000l, 16 MB) ctrl.io.xip.cmd.valid <> (accessBus.cmd.valid && !accessBus.cmd.wr) ctrl.io.xip.cmd.ready <> accessBus.cmd.ready @@ -297,6 +299,9 @@ case class Murax(config : MuraxConfig) extends Component{ ctrl.io.xip.rsp.valid <> accessBus.rsp.valid ctrl.io.xip.rsp.payload <> accessBus.rsp.data + + val bootloader = Apb3Rom("src/main/c/murax/xipBootloader/crt.bin") + apbMapping += bootloader.io.apb -> (0x1E000, 4 kB) }) @@ -327,7 +332,7 @@ object Murax{ object MuraxWithXip{ def main(args: Array[String]) { - SpinalVerilog(Murax(MuraxConfig.default.addXip())) + SpinalVerilog(Murax(MuraxConfig.default(withXip = true))) } } diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala index 8d60db5..44ca954 100644 --- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala +++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala @@ -1,5 +1,7 @@ package vexriscv.demo +import java.nio.{ByteBuffer, ByteOrder} + import spinal.core._ import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory} import spinal.lib.bus.misc.SizeMapping @@ -96,6 +98,27 @@ class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpl } + +case class Apb3Rom(onChipRamBinFile : String) extends Component{ + import java.nio.file.{Files, Paths} + val byteArray = Files.readAllBytes(Paths.get(onChipRamBinFile)) + val wordCount = (byteArray.length+3)/4 + val buffer = ByteBuffer.wrap(Files.readAllBytes(Paths.get(onChipRamBinFile))).order(ByteOrder.LITTLE_ENDIAN); + val wordArray = (0 until wordCount).map(i => { + val v = buffer.getInt + if(v < 0) BigInt(v.toLong & 0xFFFFFFFFl) else BigInt(v) + }) + + val io = new Bundle{ + val apb = slave(Apb3(log2Up(wordCount*4),32)) + } + + val rom = Mem(Bits(32 bits), wordCount) initBigInt(wordArray) +// io.apb.PRDATA := rom.readSync(io.apb.PADDR >> 2) + io.apb.PRDATA := rom.readAsync(RegNext(io.apb.PADDR >> 2)) + io.apb.PREADY := True +} + class MuraxSimpleBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean, simpleBusConfig : SimpleBusConfig) extends Component{ assert(apb3Config.dataWidth == simpleBusConfig.dataWidth) diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala index 4d65b63..a6cee0a 100644 --- a/src/test/scala/vexriscv/MuraxSim.scala +++ b/src/test/scala/vexriscv/MuraxSim.scala @@ -20,7 +20,7 @@ import scala.collection.mutable object MuraxSim { def main(args: Array[String]): Unit = { // def config = MuraxConfig.default.copy(onChipRamSize = 256 kB) - def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex").addXip() + def config = MuraxConfig.default(withXip = true).copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex") val simSlowDown = true SimConfig.allOptimisation.withWave.compile(new Murax(config)).doSimUntilVoid{dut => val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong From 5024cc5616f2314795c6df3db7095c0f58e30209 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 20 Sep 2018 13:11:20 +0200 Subject: [PATCH 04/56] Hardware breakpoint feature added Murax XIP debugging passed tests --- src/main/scala/vexriscv/Services.scala | 4 + src/main/scala/vexriscv/TestsWorkspace.scala | 66 ++++++++-------- src/main/scala/vexriscv/demo/Murax.scala | 6 +- .../scala/vexriscv/plugin/DebugPlugin.scala | 76 +++++++++---------- 4 files changed, 76 insertions(+), 76 deletions(-) diff --git a/src/main/scala/vexriscv/Services.scala b/src/main/scala/vexriscv/Services.scala index 6ed4dcb..5a6dba2 100644 --- a/src/main/scala/vexriscv/Services.scala +++ b/src/main/scala/vexriscv/Services.scala @@ -88,4 +88,8 @@ class BusReport{ class CacheReport { @BeanProperty var size = 0 @BeanProperty var bytePerLine = 0 +} + +class DebugReport { + @BeanProperty var hardwareBreakpointCount = 0 } \ No newline at end of file diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index 094c99b..04635db 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -31,40 +31,40 @@ object TestsWorkspace { SpinalConfig(mergeAsyncProcess = false).generateVerilog { val configFull = VexRiscvConfig( plugins = List( - new IBusSimplePlugin( - resetVector = 0x80000000l, - relaxedPcCalculation = false, - relaxedBusCmdValid = false, - prediction = NONE, - historyRamSizeLog2 = 10, - catchAccessFault = true, - compressedGen = true, - busLatencyMin = 1, - injectorStage = true - ), -// new IBusCachedPlugin( +// new IBusSimplePlugin( // resetVector = 0x80000000l, +// relaxedPcCalculation = false, +// relaxedBusCmdValid = false, +// prediction = NONE, +// historyRamSizeLog2 = 10, +// catchAccessFault = true, // compressedGen = true, -// prediction = DYNAMIC_TARGET, -// injectorStage = true, -// config = InstructionCacheConfig( -// cacheSize = 1024*16, -// bytePerLine = 32, -// wayCount = 1, -// addressWidth = 32, -// cpuDataWidth = 32, -// memDataWidth = 32, -// catchIllegalAccess = true, -// catchAccessFault = true, -// catchMemoryTranslationMiss = true, -// asyncTagMemory = false, -// twoCycleRam = false, -// twoCycleCache = true -// ), -// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( -// portTlbSize = 4 -// ) +// busLatencyMin = 1, +// injectorStage = true // ), + new IBusCachedPlugin( + resetVector = 0x80000000l, + compressedGen = true, + prediction = DYNAMIC_TARGET, + injectorStage = true, + config = InstructionCacheConfig( + cacheSize = 1024*16, + bytePerLine = 32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchIllegalAccess = true, + catchAccessFault = true, + catchMemoryTranslationMiss = true, + asyncTagMemory = false, + twoCycleRam = false, + twoCycleCache = true + ), + memoryTranslatorPortConfig = MemoryTranslatorPortConfig( + portTlbSize = 4 + ) + ), // new DBusSimplePlugin( // catchAddressMisaligned = true, // catchAccessFault = true, @@ -108,7 +108,7 @@ object TestsWorkspace { new SrcPlugin( separatedAddSub = false ), - new FullBarrelShifterPlugin(earlyInjection = false), + new FullBarrelShifterPlugin(earlyInjection = true), // new LightShifterPlugin, new HazardSimplePlugin( bypassExecute = true, @@ -132,7 +132,7 @@ object TestsWorkspace { new CsrPlugin(CsrPluginConfig.all(0x80000020l).copy(deterministicInteruptionEntry = false)), new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( - earlyBranch = false, + earlyBranch = true, catchAddressMisaligned = true ), new YamlPlugin("cpu0.yaml") diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 2716e04..6532458 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -40,6 +40,7 @@ case class MuraxConfig(coreFrequency : HertzNumber, gpioWidth : Int, uartCtrlConfig : UartCtrlMemoryMappedConfig, xipConfig : SpiDdrMasterCtrl.MemoryMappingParameters, + hardwareBreakpointCount : Int, cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){ require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions") val genXpi = xipConfig != null @@ -64,6 +65,7 @@ object MuraxConfig{ rspFifoDepth = 32, xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32) )), + hardwareBreakpointCount = if(withXip) 3 else 0, cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel new IBusSimplePlugin( resetVector = if(withXip) 0xF001E000l else 0x80000000l, @@ -77,7 +79,7 @@ object MuraxConfig{ catchAccessFault = false, earlyInjection = false ), - new CsrPlugin(CsrPluginConfig.smallest(mtvecInit = 0x80000020l)), + new CsrPlugin(CsrPluginConfig.smallest(mtvecInit = if(withXip) 0xE0040020l else 0x80000000l)), new DecoderSimplePlugin( catchIllegalInstruction = false ), @@ -216,7 +218,7 @@ case class Murax(config : MuraxConfig) extends Component{ //Instanciate the CPU val cpu = new VexRiscv( config = VexRiscvConfig( - plugins = cpuPlugins += new DebugPlugin(debugClockDomain) + plugins = cpuPlugins += new DebugPlugin(debugClockDomain, hardwareBreakpointCount) ) ) diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala index a91348a..70aef22 100644 --- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala @@ -96,7 +96,7 @@ case class DebugExtensionIo() extends Bundle with IMasterSlave{ -class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] { +class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : Int = 0) extends Plugin[VexRiscv] { var io : DebugExtensionIo = null val injectionAsks = ArrayBuffer[(Stage, Bool)]() @@ -104,6 +104,7 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] { object IS_EBREAK extends Stageable(Bool) + object DO_EBREAK extends Stageable(Bool) override def setup(pipeline: VexRiscv): Unit = { import Riscv._ import pipeline.config._ @@ -113,15 +114,18 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] { val decoderService = pipeline.service(classOf[DecoderService]) decoderService.addDefault(IS_EBREAK, False) - decoderService.add(EBREAK,List( - IS_EBREAK -> True, - SRC_USE_SUB_LESS -> False, - SRC1_CTRL -> Src1CtrlEnum.RS, // Zero - SRC2_CTRL -> Src2CtrlEnum.PC, - ALU_CTRL -> AluCtrlEnum.ADD_SUB //Used to get the PC value in busReadDataReg - )) + decoderService.add(EBREAK,List(IS_EBREAK -> True)) injectionPort = pipeline.service(classOf[IBusFetcher]).getInjectionPort() + + if(pipeline.serviceExist(classOf[ReportService])){ + val report = pipeline.service(classOf[ReportService]) + report.add("debug" -> { + val e = new DebugReport() + e.hardwareBreakpointCount = hardwareBreakpointCount + e + }) + } } @@ -141,6 +145,11 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] { val isPipBusy = isPipActive || RegNext(isPipActive) val haltedByBreak = RegInit(False) + val hardwareBreakpoints = Vec(Reg(new Bundle{ + val valid = Bool() + val pc = UInt(31 bits) + }), hardwareBreakpointCount) + hardwareBreakpoints.foreach(_.valid init(False)) val busReadDataReg = Reg(Bits(32 bit)) when(writeBack.arbitration.isValid) { @@ -160,8 +169,8 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] { injectionPort.payload := io.bus.cmd.data when(io.bus.cmd.valid) { - switch(io.bus.cmd.address(2 downto 2)) { - is(0) { + switch(io.bus.cmd.address(7 downto 2)) { + is(0x0) { when(io.bus.cmd.wr) { stepIt := io.bus.cmd.data(4) resetIt setWhen (io.bus.cmd.data(16)) clearWhen (io.bus.cmd.data(24)) @@ -169,45 +178,31 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] { haltedByBreak clearWhen (io.bus.cmd.data(25)) } } - is(1) { + is(0x1) { when(io.bus.cmd.wr) { injectionPort.valid := True io.bus.cmd.ready := injectionPort.ready } } + for(i <- 0 until hardwareBreakpointCount){ + is(0x10 + i){ + when(io.bus.cmd.wr){ + hardwareBreakpoints(i).assignFromBits(io.bus.cmd.data) + } + } + } } } - - -// Component.current.addPrePopTask(() => { -// //Check if the decode instruction is driven by a register -// val instructionDriver = try {decode.input(INSTRUCTION).getDrivingReg} catch { case _ : Throwable => null} -// if(instructionDriver != null){ //If yes => -// //Insert the instruction by writing the "fetch to decode instruction register", -// // Work even if it need to cross some hierarchy (caches) -// instructionDriver.component.rework { -// when(insertDecodeInstruction.pull()) { -// instructionDriver := io.bus.cmd.data.pull() -// } -// } -// } else{ -// //Insert the instruction via a mux in the decode stage -// when(RegNext(insertDecodeInstruction)){ -// decode.input(INSTRUCTION) := RegNext(io.bus.cmd.data) -// } -// } -// }) -// - - when(execute.input(IS_EBREAK)){ - when(execute.arbitration.isValid ) { - iBusFetcher.flushIt() - iBusFetcher.haltIt() - decode.arbitration.flushAll := True - } - when(execute.arbitration.isFiring) { + decode.insert(DO_EBREAK) := !haltIt && (decode.input(IS_EBREAK) || hardwareBreakpoints.map(hb => hb.valid && hb.pc === (execute.input(PC) >> 1)).foldLeft(False)(_ || _)) + when(execute.arbitration.isValid && execute.input(DO_EBREAK)){ + iBusFetcher.flushIt() + iBusFetcher.haltIt() + execute.arbitration.haltByOther := True + busReadDataReg := execute.input(PC).asBits + when(List(memory, writeBack).map(_.arbitration.isValid).orR === False){ + execute.arbitration.flushAll := True haltIt := True haltedByBreak := True } @@ -215,7 +210,6 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] { when(haltIt) { iBusFetcher.haltIt() -// decode.arbitration.haltByOther := True } when(stepIt && iBusFetcher.incoming()) { From bdc3246f5afc26f121131f3ab9ed94e33cc0acb8 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 23 Sep 2018 19:23:43 +0200 Subject: [PATCH 05/56] Fix xip gitignore --- src/main/c/murax/xipBootloader/.gitignore | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/c/murax/xipBootloader/.gitignore b/src/main/c/murax/xipBootloader/.gitignore index ca41ed2..2b33f1e 100644 --- a/src/main/c/murax/xipBootloader/.gitignore +++ b/src/main/c/murax/xipBootloader/.gitignore @@ -1,4 +1,3 @@ -*.bin *.elf *.map *.d From 56fd73fbbc3f30bd7bdf64c0ac2e384e93712b7e Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 23 Sep 2018 19:26:11 +0200 Subject: [PATCH 06/56] Add missing bin files --- src/main/c/murax/xipBootloader/crt.bin | Bin 0 -> 120 bytes src/main/c/murax/xipBootloader/demo.bin | Bin 0 -> 48 bytes 2 files changed, 0 insertions(+), 0 deletions(-) create mode 100755 src/main/c/murax/xipBootloader/crt.bin create mode 100755 src/main/c/murax/xipBootloader/demo.bin diff --git a/src/main/c/murax/xipBootloader/crt.bin b/src/main/c/murax/xipBootloader/crt.bin new file mode 100755 index 0000000000000000000000000000000000000000..d64a1cb00efe30e57fa9ae8eb357f1590f780573 GIT binary patch literal 120 zcmdn~pYen85`KosObQIj3*wn3GdVCQFN$YUUIN6+;+f1v85o3FSv%e{9AFk^6_9w( z-~glzfb;>FT*G??2Bz&y{~0DXZ4vE<%Gcy-XZW030pZ`CWWB!-_Vg5e`AOHYn Cd=EPS literal 0 HcmV?d00001 From 86efb75f6aac3a50bbfcd2749c7721e0d6b1fc3f Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 23 Sep 2018 22:05:53 +0200 Subject: [PATCH 07/56] rework fetcher --- src/main/scala/vexriscv/plugin/Fetcher.scala | 116 ++++++++---------- .../vexriscv/plugin/IBusCachedPlugin.scala | 73 +++-------- .../vexriscv/plugin/IBusSimplePlugin.scala | 53 ++++---- .../vexriscv/TestIndividualFeatures.scala | 4 +- 4 files changed, 104 insertions(+), 142 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 5584ab2..986502e 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -18,7 +18,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, val compressedGen : Boolean, val cmdToRspStageCount : Int, val injectorReadyCutGen : Boolean, - val relaxedPcCalculation : Boolean, val prediction : BranchPrediction, val historyRamSizeLog2 : Int, val injectorStage : Boolean) extends Plugin[VexRiscv] with JumpService with IBusFetcher{ @@ -111,39 +110,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits))) } - val fetchPc = if(relaxedPcCalculation) new PcFetch { - //PC calculation without Jump - val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public) - - val pcPlus4 = pcReg + 4 - if (keepPcPlus4) KeepAttribute(pcPlus4) - when(preOutput.fire) { - pcReg := pcPlus4 - } - - //Realign - if(compressedGen){ - when(preOutput.fire){ - pcReg(1 downto 0) := 0 - } - } - - preOutput.valid := RegNext(True) init (False) // && !jump.pcLoad.valid - preOutput.payload := pcReg - - //application of the selected jump request - if(predictionPcLoad != null) { - when(predictionPcLoad.valid) { - pcReg := predictionPcLoad.payload - preOutput.valid := False - } - } - when(jump.pcLoad.valid) { - pcReg := jump.pcLoad.payload - } - - - } else new PcFetch{ + val fetchPc = new PcFetch{ //PC calculation without Jump val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public) val inc = RegInit(False) @@ -216,14 +183,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, }) -// val iBusCmd = new Area { -// def input = fetchPc.output -// -// // ... -// -// val output = Stream(UInt(32 bits)) -// } - case class FetchRsp() extends Bundle { val pc = UInt(32 bits) val rsp = IBusSimpleRsp() @@ -232,22 +191,51 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, val iBusRsp = new Area { - val input = Stream(UInt(32 bits)) - val inputPipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount) - val inputPipelineHalt = Vec(False, cmdToRspStageCount-1) - for(i <- 0 until cmdToRspStageCount) { - // val doFlush = if(i == cmdToRspStageCount- 1 && ???) killLastStage else flush - inputPipeline(i) << {i match { - case 0 => input.m2sPipeWithFlush(flush, relaxedPcCalculation, collapsBubble = false) - case _ => inputPipeline(i-1).haltWhen(inputPipelineHalt(i-1)).m2sPipeWithFlush(flush,collapsBubble = false) - }} +// val input = Stream(UInt(32 bits)) +// val inputPipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount) +// val inputPipelineHalt = Vec(False, cmdToRspStageCount-1) +// for(i <- 0 until cmdToRspStageCount) { +// inputPipeline(i) << {i match { +// case 0 => input.m2sPipeWithFlush(flush, false, collapsBubble = false) +// case _ => inputPipeline(i-1).haltWhen(inputPipelineHalt(i-1)).m2sPipeWithFlush(flush,collapsBubble = false) +// }} +// } + +// val stages = Array.fill(cmdToRspStageCount)(Stream(UInt(32 bits))) + val stages = Array.fill(cmdToRspStageCount + 1)(new Bundle { + val input = Stream(UInt(32 bits)) + val output = Stream(UInt(32 bits)) + val halt = Bool + val inputSample = Bool + }) + + stages(0).input << fetchPc.output + stages(0).inputSample := True + for(s <- stages) { + s.halt := False + s.output << s.input.haltWhen(s.halt) } + for((s,sNext) <- (stages, stages.tail).zipped) { + sNext.input << s.output.m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false) + } + +// +// val pipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount + 1) +// val halts = Vec(False, cmdToRspStageCount) +// for(i <- 0 until cmdToRspStageCount + 1) { +// pipeline(i) << {i match { +// case 0 => pipeline(0) << fetchPc.output.haltWhen(halts(i)) +// case 1 => pipeline(1).m2sPipeWithFlush(flush, false, collapsBubble = false) +// case _ => inputPipeline(i-1).haltWhen(inputPipelineHalt(i-1)).m2sPipeWithFlush(flush,collapsBubble = false) +// }} +// } + // ... val readyForError = True val output = Stream(FetchRsp()) - incomingInstruction setWhen(inputPipeline.map(_.valid).orR) + incomingInstruction setWhen(stages.tail.map(_.input.valid).reduce(_ || _)) } val decompressor = ifGen(decodePcGen)(new Area{ @@ -326,10 +314,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, val valids = pcUpdatedGen(True, False :: List(execute, memory, writeBack).map(_.arbitration.isStuck), true) pcValids := Vec(valids.takeRight(4)) } else new Area{ - val valids = pcUpdatedGen(True, iBusRsp.inputPipeline.map(!_.ready) ++ (if (injectorStage) List(!decodeInput.ready) else Nil) ++ List(execute, memory, writeBack).map(_.arbitration.isStuck), relaxedPcCalculation) - if(relaxedPcCalculation && fetchPrediction != null) when(fetchPc.predictionPcLoad.valid){ - valids(0).getDrivingReg := False - } + val valids = pcUpdatedGen(True, iBusRsp.stages.tail.map(!_.input.ready) ++ (if (injectorStage) List(!decodeInput.ready) else Nil) ++ List(execute, memory, writeBack).map(_.arbitration.isStuck), false) pcValids := Vec(valids.takeRight(4)) } @@ -426,7 +411,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, } def stage1ToInjectorPipe[T <: Data](input : T): (T,T) ={ - val iBusRspContext = iBusRsp.inputPipeline.tail.foldLeft(input)((data,stream) => RegNextWhen(data, stream.ready)) + val iBusRspContext = iBusRsp.stages.drop(1).dropRight(1).foldLeft(input)((data,stage) => RegNextWhen(data, stage.output.ready)) // val decompressorContext = ifGen(compressedGen)(new Area{ // val lastContext = RegNextWhen(iBusRspContext, decompressor.input.fire) // val output = decompressor.bufferValid ? lastContext | iBusRspContext @@ -450,8 +435,8 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, val historyCache = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) val historyWrite = historyCache.writePort - val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.inputPipeline(0).ready) - val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.inputPipeline(0).payload >> 2).resized + val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready) + val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(0).input.payload >> 2).resized case class DynamicContext() extends Bundle{ val hazard = Bool @@ -459,7 +444,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, } val fetchContext = DynamicContext() fetchContext.hazard := hazard - fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush) + fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || flush) object PREDICTION_CONTEXT extends Stageable(DynamicContext()) decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._2 @@ -509,8 +494,8 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) val historyWrite = history.writePort - val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush) - val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))) else True) + val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready || flush) + val hit = line.source === (iBusRsp.stages(1).input.payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.stages(1).input.payload(1))) else True) //Avoid stoping instruction fetch in the middle patch if(compressedGen && cmdToRspStageCount == 1){ @@ -518,9 +503,10 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, } //Avoid write to read hazard - val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.inputPipeline(0).ready) - val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.inputPipeline(0).payload >> 2).resized - fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.inputPipeline(0).fire //XXX && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1)) + val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready) + val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(1).input.payload >> 2).resized + //TODO improve predictionPcLoad way of doing things + fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).output.fire //XXX && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1)) fetchPc.predictionPcLoad.payload := line.target case class PredictionResult() extends Bundle{ diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index 187e95c..405c277 100644 --- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -23,14 +23,14 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, keepPcPlus4 = keepPcPlus4, decodePcGen = compressedGen, compressedGen = compressedGen, - cmdToRspStageCount = (if(config.twoCycleCache) 2 else 1), + cmdToRspStageCount = (if(config.twoCycleCache) 2 else 1) + (if(relaxedPcCalculation) 1 else 0), injectorReadyCutGen = false, - relaxedPcCalculation = relaxedPcCalculation, prediction = prediction, historyRamSizeLog2 = historyRamSizeLog2, injectorStage = !config.twoCycleCache || injectorStage){ import config._ + var iBus : InstructionCacheMemBus = null var mmuBus : MemoryTranslatorBus = null var privilegeService : PrivilegeService = null @@ -99,18 +99,20 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus") iBus <> cache.io.mem iBus.cmd.address.allowOverride := cache.io.mem.cmd.address // - debugAddressOffset - + + val stageOffset = if(relaxedPcCalculation) 1 else 0 + def stages = iBusRsp.stages.drop(stageOffset) //Connect prefetch cache side - cache.io.cpu.prefetch.isValid := fetchPc.output.valid - cache.io.cpu.prefetch.pc := fetchPc.output.payload - iBusRsp.input << fetchPc.output.haltWhen(cache.io.cpu.prefetch.haltIt) + cache.io.cpu.prefetch.isValid := stages(0).input.valid + cache.io.cpu.prefetch.pc := stages(0).input.payload + stages(0).halt setWhen(cache.io.cpu.prefetch.haltIt) cache.io.cpu.fetch.isRemoved := flush val iBusRspOutputHalt = False if (mmuBus != null) { cache.io.cpu.fetch.mmuBus <> mmuBus - (if(twoCycleCache) iBusRsp.inputPipelineHalt(0) else iBusRspOutputHalt) setWhen(mmuBus.cmd.isValid && !mmuBus.rsp.hit && !mmuBus.rsp.miss) + (if(twoCycleCache) stages(1).halt else iBusRspOutputHalt) setWhen(mmuBus.cmd.isValid && !mmuBus.rsp.hit && !mmuBus.rsp.miss) } else { cache.io.cpu.fetch.mmuBus.rsp.physicalAddress := cache.io.cpu.fetch.mmuBus.cmd.virtualAddress cache.io.cpu.fetch.mmuBus.rsp.allowExecute := True @@ -123,15 +125,15 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, } //Connect fetch cache side - cache.io.cpu.fetch.isValid := iBusRsp.inputPipeline(0).valid - cache.io.cpu.fetch.isStuck := !iBusRsp.inputPipeline(0).ready - cache.io.cpu.fetch.pc := iBusRsp.inputPipeline(0).payload + cache.io.cpu.fetch.isValid := stages(1).input.valid + cache.io.cpu.fetch.isStuck := !stages(1).input.ready + cache.io.cpu.fetch.pc := stages(1).input.payload if(twoCycleCache){ - cache.io.cpu.decode.isValid := iBusRsp.inputPipeline(1).valid - cache.io.cpu.decode.isStuck := !iBusRsp.inputPipeline(1).ready - cache.io.cpu.decode.pc := iBusRsp.inputPipeline(1).payload + cache.io.cpu.decode.isValid := stages(2).input.valid + cache.io.cpu.decode.isStuck := !stages(2).input.ready + cache.io.cpu.decode.pc := stages(2).input.payload cache.io.cpu.decode.isUser := (if (privilegeService != null) privilegeService.isUser(decode) else False) if((!twoCycleRam || wayCount == 1) && !compressedGen && !injectorStage){ @@ -145,7 +147,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, // val missHalt = cache.io.cpu.fetch.isValid && cache.io.cpu.fetch.cacheMiss val cacheRsp = if(twoCycleCache) cache.io.cpu.decode else cache.io.cpu.fetch - val cacheRspArbitration = iBusRsp.inputPipeline(if(twoCycleCache) 1 else 0) + val cacheRspArbitration = stages(if(twoCycleCache) 2 else 1) var issueDetected = False val redoFetch = False //RegNext(False) init(False) when(cacheRsp.isValid && cacheRsp.cacheMiss && !issueDetected){ @@ -174,49 +176,12 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, } } - - iBusRsp.output.arbitrationFrom(cacheRspArbitration.haltWhen(issueDetected || iBusRspOutputHalt)) + cacheRspArbitration.halt setWhen(issueDetected || iBusRspOutputHalt) + iBusRsp.output.arbitrationFrom(cacheRspArbitration.output) iBusRsp.output.rsp.inst := cacheRsp.data - iBusRsp.output.pc := cacheRspArbitration.payload + iBusRsp.output.pc := cacheRspArbitration.output.payload -// if (dataOnDecode) { -// decode.insert(INSTRUCTION) := cache.io.cpu.decode.data -// } else { -// iBusRsp.outputBeforeStage.arbitrationFrom(iBusRsp.inputPipeline(0)) -// iBusRsp.outputBeforeStage.rsp.inst := cache.io.cpu.fetch.data -// iBusRsp.outputBeforeStage.pc := iBusRsp.inputPipeline(0).payload -// } -// -// cache.io.cpu.decode.pc := injector.inputBeforeHalt.pc -// -// val ownDecode = pipeline.plugins.filter(_.isInstanceOf[InstructionInjector]).foldLeft(True)(_ && !_.asInstanceOf[InstructionInjector].isInjecting(decode)) -// cache.io.cpu.decode.isValid := decode.arbitration.isValid && ownDecode -// cache.io.cpu.decode.isStuck := !injector.inputBeforeHalt.ready -// cache.io.cpu.decode.isUser := (if (privilegeService != null) privilegeService.isUser(decode) else False) -// // cache.io.cpu.decode.pc := decode.input(PC) -// -// redoBranch.valid := decode.arbitration.isValid && ownDecode && cache.io.cpu.decode.cacheMiss && !cache.io.cpu.decode.mmuMiss && !cache.io.cpu.decode.illegalAccess -// redoBranch.payload := decode.input(PC) -// when(redoBranch.valid) { -// decode.arbitration.redoIt := True -// decode.arbitration.flushAll := True -// } - - // val redo = RegInit(False) clearWhen(decode.arbitration.isValid) setWhen(redoBranch.valid) - // when(redoBranch.valid || redo){ - // service(classOf[InterruptionInhibitor]).inhibateInterrupts() - // } - -// if (catchSomething) { -// val accessFault = if (catchAccessFault) cache.io.cpu.decode.error else False -// val mmuMiss = if (catchMemoryTranslationMiss) cache.io.cpu.decode.mmuMiss else False -// val illegalAccess = if (catchIllegalAccess) cache.io.cpu.decode.illegalAccess else False - -// decodeExceptionPort.valid := decode.arbitration.isValid && ownDecode && (accessFault || mmuMiss || illegalAccess) -// decodeExceptionPort.code := mmuMiss ? U(14) | 1 -// decodeExceptionPort.badAddr := decode.input(PC) -// } memory plug new Area { diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 523a2ef..6e415c0 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -159,9 +159,8 @@ class IBusSimplePlugin(resetVector : BigInt, keepPcPlus4 = keepPcPlus4, decodePcGen = compressedGen, compressedGen = compressedGen, - cmdToRspStageCount = busLatencyMin, + cmdToRspStageCount = busLatencyMin + (if(relaxedPcCalculation) 1 else 0), injectorReadyCutGen = false, - relaxedPcCalculation = relaxedPcCalculation, prediction = prediction, historyRamSizeLog2 = historyRamSizeLog2, injectorStage = injectorStage){ @@ -187,36 +186,49 @@ class IBusSimplePlugin(resetVector : BigInt, pipeline plug new FetchArea(pipeline) { + + //Avoid sending to many iBus cmd val pendingCmd = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0) val pendingCmdNext = pendingCmd + iBus.cmd.fire.asUInt - iBus.rsp.fire.asUInt pendingCmd := pendingCmdNext val cmd = if(relaxedBusCmdValid) new Area { - assert(relaxedPcCalculation, "relaxedBusCmdValid can only be used with relaxedPcCalculation") - def input = fetchPc.output - def output = iBusRsp.input + ??? + /* def inputStage = iBusRsp.stages(0) + val busFork = Stream(UInt(32 bits)) + val busForkedReg = RegInit(False) + if(!relaxedPcCalculation) busForkedReg clearWhen(flush) + busForkedReg setWhen(iBus.cmd.fire) + busForkedReg clearWhen(inputStage.output.ready) + if(relaxedPcCalculation) busForkedReg clearWhen(flush) + val busForked = Bool + busForked := (if(!relaxedPcCalculation) (busForkedReg && !flush) else (busForkedReg)) + + + busFork.valid := inputStage.input.valid && !busForkedReg + busFork.payload := inputStage.input.payload + + inputStage.halt setWhen() + output.valid := (inputStage.input.valid && iBus.cmd.fire) || busForked + output.payload := input.payload + input.ready := output.fire - val fork = StreamForkVex(input, 2, flush) - val busFork = fork(0) - val pipFork = fork(1) - output << pipFork val okBus = pendingCmd =/= pendingMax iBus.cmd.valid := busFork.valid && okBus iBus.cmd.pc := busFork.payload(31 downto 2) @@ "00" - busFork.ready := iBus.cmd.ready && okBus + busFork.ready := iBus.cmd.ready && okBus*/ } else new Area { - def input = fetchPc.output - def output = iBusRsp.input + def stage = iBusRsp.stages(if(relaxedPcCalculation) 1 else 0) + stage.halt setWhen(stage.input.valid && (!iBus.cmd.valid || !iBus.cmd.ready)) - output << input.continueWhen(iBus.cmd.fire) - - iBus.cmd.valid := input.valid && output.ready && pendingCmd =/= pendingMax - iBus.cmd.pc := input.payload(31 downto 2) @@ "00" + iBus.cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax + iBus.cmd.pc := stage.input.payload(31 downto 2) @@ "00" } + val rsp = new Area { import iBusRsp._ //Manage flush for iBus transactions in flight @@ -226,20 +238,19 @@ class IBusSimplePlugin(resetVector : BigInt, discardCounter := (if(relaxedPcCalculation) pendingCmdNext else pendingCmd - iBus.rsp.fire.asUInt) } - - val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), cmdToRspStageCount + (if(relaxedBusCmdValid) 1 else 0)) + val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), cmdToRspStageCount - (if(relaxedPcCalculation) 0 else 0)) rspBuffer.io.push << iBus.rsp.throwWhen(discardCounter =/= 0).toStream rspBuffer.io.flush := flush val fetchRsp = FetchRsp() - fetchRsp.pc := inputPipeline.last.payload + fetchRsp.pc := stages.last.output.payload fetchRsp.rsp := rspBuffer.io.pop.payload fetchRsp.rsp.error.clearWhen(!rspBuffer.io.pop.valid) //Avoid interference with instruction injection from the debug plugin var issueDetected = False - val join = StreamJoin(Seq(inputPipeline.last, rspBuffer.io.pop), fetchRsp) - inputPipeline.last.ready setWhen(!inputPipeline.last.valid) + val join = StreamJoin(Seq(stages.last.output, rspBuffer.io.pop), fetchRsp) + stages.last.output.ready setWhen(!stages.last.output.valid) output << join.haltWhen(issueDetected) if(catchAccessFault){ diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala index 3474e7b..d7eae7e 100644 --- a/src/test/scala/vexriscv/TestIndividualFeatures.scala +++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala @@ -522,8 +522,8 @@ class TestIndividualFeatures extends FunSuite { // val seed = -2412372746600605141l -// val testId = Some(mutable.HashSet[Int](15)) -// val seed = -8861778219266506530l +// val testId = Some(mutable.HashSet[Int](1,6,11,17,23,24)) +// val seed = -7309275932954927463l val rand = new Random(seed) From 1e3b75ef1d3e29d0dfd52d32080aa89ced519b1e Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 23 Sep 2018 22:06:21 +0200 Subject: [PATCH 08/56] xip typo --- .../iCE40-hx8k_breakout_board_xip/toplevel.v | 42 +++++++++---------- src/main/scala/vexriscv/demo/Murax.scala | 6 +-- src/test/scala/vexriscv/MuraxSim.scala | 2 +- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v b/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v index 5034de8..659d024 100644 --- a/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v +++ b/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v @@ -37,20 +37,20 @@ module toplevel( assign io_led = io_gpioA_write[7 : 0]; - wire [1:0] io_xpi_sclk_write; - wire io_xpi_data_0_writeEnable; - wire [1:0] io_xpi_data_0_read; - wire [1:0] io_xpi_data_0_write; - wire io_xpi_data_1_writeEnable; - wire [1:0] io_xpi_data_1_read; - wire [1:0] io_xpi_data_1_write; - wire [0:0] io_xpi_ss; + wire [1:0] io_xip_sclk_write; + wire io_xip_data_0_writeEnable; + wire [1:0] io_xip_data_0_read; + wire [1:0] io_xip_data_0_write; + wire io_xip_data_1_writeEnable; + wire [1:0] io_xip_data_1_read; + wire [1:0] io_xip_data_1_write; + wire [0:0] io_xip_ss; - assign io_P12 = io_xpi_data_0_write[0]; - assign io_xpi_data_1_read[0] = io_P11; - assign io_xpi_data_1_read[1] = io_P11; - assign io_R11 = io_xpi_sclk_write[0]; - assign io_R12 = io_xpi_ss[0]; + assign io_P12 = io_xip_data_0_write[0]; + assign io_xip_data_1_read[0] = io_P11; + assign io_xip_data_1_read[1] = io_P11; + assign io_R11 = io_xip_sclk_write[0]; + assign io_R12 = io_xip_ss[0]; Murax murax ( .io_asyncReset(0), @@ -64,13 +64,13 @@ module toplevel( .io_gpioA_writeEnable(io_gpioA_writeEnable), .io_uart_txd(io_B12), .io_uart_rxd(io_B10), - .io_xpi_sclk_write(io_xpi_sclk_write), - .io_xpi_data_0_writeEnable(io_xpi_data_0_writeEnable), - .io_xpi_data_0_read(io_xpi_data_0_read), - .io_xpi_data_0_write(io_xpi_data_0_write), - .io_xpi_data_1_writeEnable(io_xpi_data_1_writeEnable), - .io_xpi_data_1_read(io_xpi_data_1_read), - .io_xpi_data_1_write(io_xpi_data_1_write), - .io_xpi_ss(io_xpi_ss) + .io_xip_sclk_write(io_xip_sclk_write), + .io_xip_data_0_writeEnable(io_xip_data_0_writeEnable), + .io_xip_data_0_read(io_xip_data_0_read), + .io_xip_data_0_write(io_xip_data_0_write), + .io_xip_data_1_writeEnable(io_xip_data_1_writeEnable), + .io_xip_data_1_read(io_xip_data_1_read), + .io_xip_data_1_write(io_xip_data_1_write), + .io_xip_ss(io_xip_ss) ); endmodule \ No newline at end of file diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 6532458..8b47602 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -162,7 +162,7 @@ case class Murax(config : MuraxConfig) extends Component{ val gpioA = master(TriStateArray(gpioWidth bits)) val uart = master(Uart()) - val xpi = ifGen(genXpi)(master(SpiDdrMaster(xipConfig.ctrl.spi))) + val xip = ifGen(genXpi)(master(SpiDdrMaster(xipConfig.ctrl.spi))) } @@ -286,9 +286,9 @@ case class Murax(config : MuraxConfig) extends Component{ timerInterrupt setWhen(timer.io.interrupt) apbMapping += timer.io.apb -> (0x20000, 4 kB) - val xpi = ifGen(genXpi)(new Area{ + val xip = ifGen(genXpi)(new Area{ val ctrl = Apb3SpiDdrMasterCtrl(xipConfig) - ctrl.io.spi <> io.xpi + ctrl.io.spi <> io.xip externalInterrupt setWhen(ctrl.io.interrupt) apbMapping += ctrl.io.apb -> (0x1F000, 4 kB) diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala index a6cee0a..53c22b3 100644 --- a/src/test/scala/vexriscv/MuraxSim.scala +++ b/src/test/scala/vexriscv/MuraxSim.scala @@ -47,7 +47,7 @@ object MuraxSim { baudPeriod = uartBaudPeriod ) - if(config.xipConfig != null)dut.io.xpi.data(1).read #= 0 + if(config.xipConfig != null)dut.io.xip.data(1).read #= 0 val guiThread = fork{ val guiToSim = mutable.Queue[Any]() From aff436ddcf4ff2d09d1829ad5f7a7f5a4f3f550e Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 24 Sep 2018 18:31:33 +0200 Subject: [PATCH 09/56] Sync with SpinalHDL head Add mmu test into the dhrystone regression command --- src/main/scala/vexriscv/TestsWorkspace.scala | 10 +++++----- src/main/scala/vexriscv/demo/GenFull.scala | 4 ++-- src/main/scala/vexriscv/demo/Murax.scala | 6 +++--- .../scala/vexriscv/demo/VexRiscvAvalonForSim.scala | 10 +++++----- .../demo/VexRiscvAvalonWithIntegratedJtag.scala | 10 +++++----- .../vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala | 10 +++++----- .../vexriscv/demo/VexRiscvCachedWishboneForSim.scala | 8 ++++---- src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 2 +- .../scala/vexriscv/plugin/DecoderSimplePlugin.scala | 2 +- .../vexriscv/plugin/ExternalInterruptArrayPlugin.scala | 2 +- .../scala/vexriscv/plugin/MemoryTranslatorPlugin.scala | 1 + src/test/scala/vexriscv/DhrystoneBench.scala | 2 +- 12 files changed, 34 insertions(+), 33 deletions(-) diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index 04635db..8d50ad9 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -28,7 +28,7 @@ import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag} object TestsWorkspace { def main(args: Array[String]) { - SpinalConfig(mergeAsyncProcess = false).generateVerilog { + SpinalConfig(mergeAsyncProcess = false, anonymSignalPrefix = "zz_").generateVerilog { val configFull = VexRiscvConfig( plugins = List( // new IBusSimplePlugin( @@ -44,11 +44,11 @@ object TestsWorkspace { // ), new IBusCachedPlugin( resetVector = 0x80000000l, - compressedGen = true, - prediction = DYNAMIC_TARGET, + compressedGen = false, + prediction = NONE, injectorStage = true, config = InstructionCacheConfig( - cacheSize = 1024*16, + cacheSize = 4096, bytePerLine = 32, wayCount = 1, addressWidth = 32, @@ -72,7 +72,7 @@ object TestsWorkspace { // ), new DBusCachedPlugin( config = new DataCacheConfig( - cacheSize = 4096*4, + cacheSize = 4096, bytePerLine = 32, wayCount = 1, addressWidth = 32, diff --git a/src/main/scala/vexriscv/demo/GenFull.scala b/src/main/scala/vexriscv/demo/GenFull.scala index bc0f039..36b0b4d 100644 --- a/src/main/scala/vexriscv/demo/GenFull.scala +++ b/src/main/scala/vexriscv/demo/GenFull.scala @@ -54,7 +54,7 @@ object GenFull extends App{ ) ), new MemoryTranslatorPlugin( - tlbSize = 64, + tlbSize = 32, virtualRange = _(31 downto 28) === 0xC, ioRange = _(31 downto 28) === 0xF ), @@ -82,7 +82,7 @@ object GenFull extends App{ ), new MulPlugin, new DivPlugin, - new CsrPlugin(CsrPluginConfig.small), + new CsrPlugin(CsrPluginConfig.small(0x80000020l)), new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( earlyBranch = false, diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 8b47602..89859e5 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -43,7 +43,7 @@ case class MuraxConfig(coreFrequency : HertzNumber, hardwareBreakpointCount : Int, cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){ require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions") - val genXpi = xipConfig != null + val genXip = xipConfig != null } @@ -162,7 +162,7 @@ case class Murax(config : MuraxConfig) extends Component{ val gpioA = master(TriStateArray(gpioWidth bits)) val uart = master(Uart()) - val xip = ifGen(genXpi)(master(SpiDdrMaster(xipConfig.ctrl.spi))) + val xip = ifGen(genXip)(master(SpiDdrMaster(xipConfig.ctrl.spi))) } @@ -286,7 +286,7 @@ case class Murax(config : MuraxConfig) extends Component{ timerInterrupt setWhen(timer.io.interrupt) apbMapping += timer.io.apb -> (0x20000, 4 kB) - val xip = ifGen(genXpi)(new Area{ + val xip = ifGen(genXip)(new Area{ val ctrl = Apb3SpiDdrMasterCtrl(xipConfig) ctrl.io.spi <> io.xip externalInterrupt setWhen(ctrl.io.interrupt) diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala index 5a720cf..fb872aa 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala @@ -141,31 +141,31 @@ object VexRiscvAvalonForSim{ var iBus : AvalonMM = null for (plugin <- cpuConfig.plugins) plugin match { case plugin: IBusSimplePlugin => { - plugin.iBus.asDirectionLess() //Unset IO properties of iBus + plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus iBus = master(plugin.iBus.toAvalon()) .setName("iBusAvalon") .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) } case plugin: IBusCachedPlugin => { - plugin.iBus.asDirectionLess() //Unset IO properties of iBus + plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus iBus = master(plugin.iBus.toAvalon()) .setName("iBusAvalon") .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) } case plugin: DBusSimplePlugin => { - plugin.dBus.asDirectionLess() + plugin.dBus.setAsDirectionLess() master(plugin.dBus.toAvalon()) .setName("dBusAvalon") .addTag(ClockDomainTag(ClockDomain.current)) } case plugin: DBusCachedPlugin => { - plugin.dBus.asDirectionLess() + plugin.dBus.setAsDirectionLess() master(plugin.dBus.toAvalon()) .setName("dBusAvalon") .addTag(ClockDomainTag(ClockDomain.current)) } case plugin: DebugPlugin => { - plugin.io.bus.asDirectionLess() + plugin.io.bus.setAsDirectionLess() slave(plugin.io.bus.fromAvalon()) .setName("debugBusAvalon") .addTag(ClockDomainTag(plugin.debugClockDomain)) diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala index 15f5db0..ebaabba 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala @@ -139,31 +139,31 @@ object VexRiscvAvalonWithIntegratedJtag{ var iBus : AvalonMM = null for (plugin <- cpuConfig.plugins) plugin match { case plugin: IBusSimplePlugin => { - plugin.iBus.asDirectionLess() //Unset IO properties of iBus + plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus iBus = master(plugin.iBus.toAvalon()) .setName("iBusAvalon") .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) } case plugin: IBusCachedPlugin => { - plugin.iBus.asDirectionLess() //Unset IO properties of iBus + plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus iBus = master(plugin.iBus.toAvalon()) .setName("iBusAvalon") .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) } case plugin: DBusSimplePlugin => { - plugin.dBus.asDirectionLess() + plugin.dBus.setAsDirectionLess() master(plugin.dBus.toAvalon()) .setName("dBusAvalon") .addTag(ClockDomainTag(ClockDomain.current)) } case plugin: DBusCachedPlugin => { - plugin.dBus.asDirectionLess() + plugin.dBus.setAsDirectionLess() master(plugin.dBus.toAvalon()) .setName("dBusAvalon") .addTag(ClockDomainTag(ClockDomain.current)) } case plugin: DebugPlugin => { - plugin.io.bus.asDirectionLess() + plugin.io.bus.setAsDirectionLess() val jtag = slave(new Jtag()) .setName("jtag") jtag <> plugin.io.bus.fromJtag() diff --git a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala index 475efa4..b8d7242 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala @@ -140,31 +140,31 @@ object VexRiscvAxi4WithIntegratedJtag{ var iBus : Axi4ReadOnly = null for (plugin <- cpuConfig.plugins) plugin match { case plugin: IBusSimplePlugin => { - plugin.iBus.asDirectionLess() //Unset IO properties of iBus + plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig()) .setName("iBusAxi") .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) } case plugin: IBusCachedPlugin => { - plugin.iBus.asDirectionLess() //Unset IO properties of iBus + plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig()) .setName("iBusAxi") .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) } case plugin: DBusSimplePlugin => { - plugin.dBus.asDirectionLess() + plugin.dBus.setAsDirectionLess() master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig()) .setName("dBusAxi") .addTag(ClockDomainTag(ClockDomain.current)) } case plugin: DBusCachedPlugin => { - plugin.dBus.asDirectionLess() + plugin.dBus.setAsDirectionLess() master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig()) .setName("dBusAxi") .addTag(ClockDomainTag(ClockDomain.current)) } case plugin: DebugPlugin => { - plugin.io.bus.asDirectionLess() + plugin.io.bus.setAsDirectionLess() val jtag = slave(new Jtag()) .setName("jtag") jtag <> plugin.io.bus.fromJtag() diff --git a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala index 35cad08..20254b6 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala @@ -118,19 +118,19 @@ object VexRiscvCachedWishboneForSim{ cpu.rework { for (plugin <- cpuConfig.plugins) plugin match { case plugin: IBusSimplePlugin => { - plugin.iBus.asDirectionLess() //Unset IO properties of iBus + plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus master(plugin.iBus.toWishbone()).setName("iBusWishbone") } case plugin: IBusCachedPlugin => { - plugin.iBus.asDirectionLess() + plugin.iBus.setAsDirectionLess() master(plugin.iBus.toWishbone()).setName("iBusWishbone") } case plugin: DBusSimplePlugin => { - plugin.dBus.asDirectionLess() + plugin.dBus.setAsDirectionLess() master(plugin.dBus.toWishbone()).setName("dBusWishbone") } case plugin: DBusCachedPlugin => { - plugin.dBus.asDirectionLess() + plugin.dBus.setAsDirectionLess() master(plugin.dBus.toWishbone()).setName("dBusWishbone") } case _ => diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index 0547c69..02f47eb 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -12,7 +12,7 @@ class DAxiCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An override def build(pipeline: VexRiscv): Unit = { super.build(pipeline) - dBus.asDirectionLess() + dBus.setAsDirectionLess() dAxi = master(dBus.toAxi4Shared().toAxi4()).setName("dAxi") dBus = null //For safety, as nobody should use it anymore :) } diff --git a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala index ad33efc..3d60498 100644 --- a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala @@ -151,7 +151,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, forceLegalI import toplevel.config._ toplevel.getAllIo.foreach{io => if(io.isInput) io.assignDontCare() - io.asDirectionLess() + io.setAsDirectionLess() } toplevel.decode.input(INSTRUCTION).removeAssignments() toplevel.decode.input(INSTRUCTION) := Delay((in Bits(32 bits)).setName("instruction"),2) diff --git a/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala b/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala index ee200ea..fd1a561 100644 --- a/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala +++ b/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala @@ -14,7 +14,7 @@ class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC val csr = pipeline.service(classOf[CsrPlugin]) val mask = Reg(Bits(arrayWidth bits)) init(0) val pendings = mask & RegNext(externalInterruptArray) - csr.externalInterrupt.asDirectionLess() := pendings.orR + csr.externalInterrupt.setAsDirectionLess() := pendings.orR csr.rw(maskCsrId, mask) csr.r(pendingsCsrId, pendings) } diff --git a/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala b/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala index 4c72131..db31022 100644 --- a/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala @@ -129,6 +129,7 @@ class MemoryTranslatorPlugin(tlbSize : Int, } //Manage TLBW0 and TLBW1 instructions + //TODO not exception safe (sideeffect) execute plug new Area{ import execute._ val tlbWriteBuffer = Reg(UInt(20 bits)) diff --git a/src/test/scala/vexriscv/DhrystoneBench.scala b/src/test/scala/vexriscv/DhrystoneBench.scala index 938384d..7358574 100644 --- a/src/test/scala/vexriscv/DhrystoneBench.scala +++ b/src/test/scala/vexriscv/DhrystoneBench.scala @@ -89,7 +89,7 @@ class DhrystoneBench extends FunSuite{ getDmips( name = "GenFull", gen = GenFull.main(null), - testCmd = "make clean run REDO=10 CSR=no MMU=no" + testCmd = "make clean run REDO=10 CSR=no" ) test("final_report") { From 6dde73f97cb042ddd40e45ee5639d19728ae83eb Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 27 Sep 2018 00:55:30 +0200 Subject: [PATCH 10/56] Murax demo with XIP is now fully defined in SpinalHDL --- .../iCE40-hx8k_breakout_board_xip/Makefile | 42 ++--- ...> Murax_iCE40_hx8k_breakout_board_xip.pcf} | 0 .../iCE40-hx8k_breakout_board_xip/toplevel.v | 33 +--- src/main/scala/vexriscv/demo/Murax.scala | 143 +++++++++++++++++- 4 files changed, 169 insertions(+), 49 deletions(-) rename scripts/Murax/iCE40-hx8k_breakout_board_xip/{toplevel.pcf => Murax_iCE40_hx8k_breakout_board_xip.pcf} (100%) diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile b/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile index 309e0df..ca74503 100644 --- a/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile +++ b/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile @@ -1,38 +1,38 @@ -VERILOG = ../../../Murax.v toplevel.v +VERILOG = ../../../Murax_iCE40_hx8k_breakout_board_xip.v generate : - #(cd ../../..; sbt "run-main vexriscv.demo.MuraxWithXip") + #(cd ../../..; sbt "run-main vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip") -../../../Murax.v : - #(cd ../../..; sbt "run-main vexriscv.demo.MuraxWithXip") +../../../Murax_iCE40_hx8k_breakout_board_xip.v : + #(cd ../../..; sbt "run-main vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip") -../../../Murax.v*.bin: +../../../Murax_iCE40_hx8k_breakout_board_xip.v*.bin: -bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin +bin/Murax_iCE40_hx8k_breakout_board_xip.blif : ${VERILOG} ../../../Murax_iCE40_hx8k_breakout_board_xip.v*.bin mkdir -p bin - rm -f Murax.v*.bin - cp ../../../Murax.v*.bin . | true - yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG} + rm -f Murax_iCE40_hx8k_breakout_board_xip.v*.bin + cp ../../../Murax_iCE40_hx8k_breakout_board_xip.v*.bin . | true + yosys -v3 -p "synth_ice40 -top Murax_iCE40_hx8k_breakout_board_xip -blif bin/Murax_iCE40_hx8k_breakout_board_xip.blif" ${VERILOG} -bin/toplevel.asc : toplevel.pcf bin/toplevel.blif - arachne-pnr -p toplevel.pcf -d 8k --max-passes 600 -P ct256 bin/toplevel.blif -o bin/toplevel.asc +bin/Murax_iCE40_hx8k_breakout_board_xip.asc : Murax_iCE40_hx8k_breakout_board_xip.pcf bin/Murax_iCE40_hx8k_breakout_board_xip.blif + arachne-pnr -p Murax_iCE40_hx8k_breakout_board_xip.pcf -d 8k --max-passes 600 -P ct256 bin/Murax_iCE40_hx8k_breakout_board_xip.blif -o bin/Murax_iCE40_hx8k_breakout_board_xip.asc -bin/toplevel.bin : bin/toplevel.asc - icepack bin/toplevel.asc bin/toplevel.bin +bin/Murax_iCE40_hx8k_breakout_board_xip.bin : bin/Murax_iCE40_hx8k_breakout_board_xip.asc + icepack bin/Murax_iCE40_hx8k_breakout_board_xip.asc bin/Murax_iCE40_hx8k_breakout_board_xip.bin -compile : bin/toplevel.bin +compile : bin/Murax_iCE40_hx8k_breakout_board_xip.bin -time: bin/toplevel.bin - icetime -tmd hx8k bin/toplevel.asc +time: bin/Murax_iCE40_hx8k_breakout_board_xip.bin + icetime -tmd hx8k bin/Murax_iCE40_hx8k_breakout_board_xip.asc -prog : bin/toplevel.bin - iceprog -S bin/toplevel.bin +prog : bin/Murax_iCE40_hx8k_breakout_board_xip.bin + iceprog -S bin/Murax_iCE40_hx8k_breakout_board_xip.bin -sudo-prog : bin/toplevel.bin - sudo iceprog -S bin/toplevel.bin +sudo-prog : bin/Murax_iCE40_hx8k_breakout_board_xip.bin + sudo iceprog -S bin/Murax_iCE40_hx8k_breakout_board_xip.bin clean : rm -rf bin - rm -f Murax.v*.bin + rm -f Murax_iCE40_hx8k_breakout_board_xip.v*.bin diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.pcf b/scripts/Murax/iCE40-hx8k_breakout_board_xip/Murax_iCE40_hx8k_breakout_board_xip.pcf similarity index 100% rename from scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.pcf rename to scripts/Murax/iCE40-hx8k_breakout_board_xip/Murax_iCE40_hx8k_breakout_board_xip.pcf diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v b/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v index 659d024..d08bddb 100644 --- a/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v +++ b/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v @@ -9,8 +9,9 @@ module toplevel( output io_B12, input io_B10, - output io_P12, - input io_P11, + //p12 as output mean flash config + input io_P12, + output io_P11, output io_R11, output io_R12, @@ -36,22 +37,6 @@ module toplevel( assign io_led = io_gpioA_write[7 : 0]; - - wire [1:0] io_xip_sclk_write; - wire io_xip_data_0_writeEnable; - wire [1:0] io_xip_data_0_read; - wire [1:0] io_xip_data_0_write; - wire io_xip_data_1_writeEnable; - wire [1:0] io_xip_data_1_read; - wire [1:0] io_xip_data_1_write; - wire [0:0] io_xip_ss; - - assign io_P12 = io_xip_data_0_write[0]; - assign io_xip_data_1_read[0] = io_P11; - assign io_xip_data_1_read[1] = io_P11; - assign io_R11 = io_xip_sclk_write[0]; - assign io_R12 = io_xip_ss[0]; - Murax murax ( .io_asyncReset(0), .io_mainClk (io_mainClk ), @@ -64,13 +49,9 @@ module toplevel( .io_gpioA_writeEnable(io_gpioA_writeEnable), .io_uart_txd(io_B12), .io_uart_rxd(io_B10), - .io_xip_sclk_write(io_xip_sclk_write), - .io_xip_data_0_writeEnable(io_xip_data_0_writeEnable), - .io_xip_data_0_read(io_xip_data_0_read), - .io_xip_data_0_write(io_xip_data_0_write), - .io_xip_data_1_writeEnable(io_xip_data_1_writeEnable), - .io_xip_data_1_read(io_xip_data_1_read), - .io_xip_data_1_write(io_xip_data_1_write), - .io_xip_ss(io_xip_ss) + .io_xip_ss(io_R12), + .io_xip_sclk(io_R11), + .io_xip_data_0(io_P11), + .io_xip_data_1(io_P12) ); endmodule \ No newline at end of file diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 89859e5..81db2ce 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -332,9 +332,148 @@ object Murax{ } } -object MuraxWithXip{ +object Murax_iCE40_hx8k_breakout_board_xip{ + + case class SB_GB() extends BlackBox{ + val USER_SIGNAL_TO_GLOBAL_BUFFER = in Bool() + val GLOBAL_BUFFER_OUTPUT = out Bool() + } + + case class SB_IO_SCLK() extends BlackBox{ + addGeneric("PIN_TYPE", B"010000") + val PACKAGE_PIN = out Bool() + val OUTPUT_CLK = in Bool() + val CLOCK_ENABLE = in Bool() + val D_OUT_0 = in Bool() + val D_OUT_1 = in Bool() + setDefinitionName("SB_IO") + } + + case class SB_IO_DATA() extends BlackBox{ + addGeneric("PIN_TYPE", B"110000") + val PACKAGE_PIN = inout(Analog(Bool)) + val CLOCK_ENABLE = in Bool() + val INPUT_CLK = in Bool() + val OUTPUT_CLK = in Bool() + val OUTPUT_ENABLE = in Bool() + val D_OUT_0 = in Bool() + val D_OUT_1 = in Bool() + val D_IN_0 = out Bool() + val D_IN_1 = out Bool() + setDefinitionName("SB_IO") + } + + case class Murax_iCE40_hx8k_breakout_board_xip() extends Component{ + val io = new Bundle { + val J3 = in Bool() + val H16 = in Bool() + val G15 = in Bool() + val G16 = out Bool() + val F15 = in Bool() + val B12 = out Bool() + val B10 = in Bool() + + + //p12 as mosi mean flash config + val P12 = inout(Analog(Bool)) + val P11 = inout(Analog(Bool)) + val R11 = out Bool() + val R12 = out Bool() + + val led = out Bits(8 bits) + } + val murax = Murax(MuraxConfig.default(withXip = true)) + murax.io.asyncReset := False + + val mainClkBuffer = SB_GB() + mainClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.J3 + mainClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.mainClk + + val jtagClkBuffer = SB_GB() + jtagClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.H16 + jtagClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.jtag.tck + + io.led <> murax.io.gpioA.write(7 downto 0) + + murax.io.jtag.tdi <> io.G15 + murax.io.jtag.tdo <> io.G16 + murax.io.jtag.tms <> io.F15 + murax.io.gpioA.read <> 0 + murax.io.uart.txd <> io.B12 + murax.io.uart.rxd <> io.B10 + + + + val xip = new ClockingArea(murax.systemClockDomain) { + RegNext(murax.io.xip.ss.asBool) <> io.R12 + + val sclkIo = SB_IO_SCLK() + sclkIo.PACKAGE_PIN <> io.R11 + sclkIo.CLOCK_ENABLE := True + + sclkIo.OUTPUT_CLK := ClockDomain.current.readClockWire + sclkIo.D_OUT_0 <> murax.io.xip.sclk.write(0) + sclkIo.D_OUT_1 <> RegNext(murax.io.xip.sclk.write(1)) + + val datas = for ((data, pin) <- (murax.io.xip.data, List(io.P12, io.P11).reverse).zipped) yield new Area { + val dataIo = SB_IO_DATA() + dataIo.PACKAGE_PIN := pin + dataIo.CLOCK_ENABLE := True + + dataIo.OUTPUT_CLK := ClockDomain.current.readClockWire + dataIo.OUTPUT_ENABLE <> data.writeEnable + dataIo.D_OUT_0 <> data.write(0) + dataIo.D_OUT_1 <> RegNext(data.write(1)) + + dataIo.INPUT_CLK := ClockDomain.current.readClockWire + data.read(0) := dataIo.D_IN_0 + data.read(1) := RegNext(dataIo.D_IN_1) + } + } + + } + def main(args: Array[String]) { - SpinalVerilog(Murax(MuraxConfig.default(withXip = true))) + SpinalVerilog(Murax_iCE40_hx8k_breakout_board_xip()) + /*SpinalVerilog{ + val c = Murax(MuraxConfig.default(withXip = true)) + + + + + c.rework { + c.resetCtrlClockDomain { + c.io.xip.setAsDirectionLess.allowDirectionLessIo.flattenForeach(_.unsetName()) + + out(RegNext(c.io.xip.ss)).setName("io_xip_ss") + + val sclk = SB_IO_SCLK() + sclk.PACKAGE_PIN := inout(Analog(Bool)).setName("io_xip_sclk") + sclk.CLOCK_ENABLE := True + + sclk.OUTPUT_CLK := ClockDomain.current.readClockWire + sclk.D_OUT_0 <> c.io.xip.sclk.write(0) + sclk.D_OUT_1 <> RegNext(c.io.xip.sclk.write(1)) + + for (i <- 0 until c.io.xip.p.dataWidth) { + val data = c.io.xip.data(i) + val bb = SB_IO_DATA() + bb.PACKAGE_PIN := inout(Analog(Bool)).setName(s"io_xip_data_$i" ) + bb.CLOCK_ENABLE := True + + bb.OUTPUT_CLK := ClockDomain.current.readClockWire + bb.OUTPUT_ENABLE <> data.writeEnable + bb.D_OUT_0 <> data.write(0) + bb.D_OUT_1 <> RegNext(data.write(1)) + + bb.INPUT_CLK := ClockDomain.current.readClockWire + data.read(0) := bb.D_IN_0 + data.read(1) := RegNext(bb.D_IN_1) + } + } + } + c + }*/ } } From a2d3cfbfc1b83666f244c957ff726bb1b28ebfd5 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 27 Sep 2018 00:56:20 +0200 Subject: [PATCH 11/56] Remove unused file --- .../iCE40-hx8k_breakout_board_xip/toplevel.v | 57 ------------------- 1 file changed, 57 deletions(-) delete mode 100644 scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v diff --git a/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v b/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v deleted file mode 100644 index d08bddb..0000000 --- a/scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v +++ /dev/null @@ -1,57 +0,0 @@ -`timescale 1ns / 1ps - -module toplevel( - input io_J3, - input io_H16, - input io_G15, - output io_G16, - input io_F15, - output io_B12, - input io_B10, - - //p12 as output mean flash config - input io_P12, - output io_P11, - output io_R11, - output io_R12, - - output [7:0] io_led - - ); - - wire [31:0] io_gpioA_read; - wire [31:0] io_gpioA_write; - wire [31:0] io_gpioA_writeEnable; - wire io_mainClk; - wire io_jtag_tck; - - SB_GB mainClkBuffer ( - .USER_SIGNAL_TO_GLOBAL_BUFFER (io_J3), - .GLOBAL_BUFFER_OUTPUT ( io_mainClk) - ); - - SB_GB jtagClkBuffer ( - .USER_SIGNAL_TO_GLOBAL_BUFFER (io_H16), - .GLOBAL_BUFFER_OUTPUT ( io_jtag_tck) - ); - - assign io_led = io_gpioA_write[7 : 0]; - - Murax murax ( - .io_asyncReset(0), - .io_mainClk (io_mainClk ), - .io_jtag_tck(io_jtag_tck), - .io_jtag_tdi(io_G15), - .io_jtag_tdo(io_G16), - .io_jtag_tms(io_F15), - .io_gpioA_read (io_gpioA_read), - .io_gpioA_write (io_gpioA_write), - .io_gpioA_writeEnable(io_gpioA_writeEnable), - .io_uart_txd(io_B12), - .io_uart_rxd(io_B10), - .io_xip_ss(io_R12), - .io_xip_sclk(io_R11), - .io_xip_data_0(io_P11), - .io_xip_data_1(io_P12) - ); -endmodule \ No newline at end of file From acd1ca422a7008ea876d5248a8aaf1d0d13c232b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 27 Sep 2018 18:24:40 +0200 Subject: [PATCH 12/56] wip --- .../scala/vexriscv/plugin/CsrPlugin.scala | 43 ++++++++++++++++--- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 065c306..81f8531 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -50,6 +50,7 @@ case class CsrPluginConfig( ucycleAccess : CsrAccess, wfiGen : Boolean, ecallGen : Boolean, + sscratchGen : Boolean = false, deterministicInteruptionEntry : Boolean = false //Only used for simulatation purposes ){ @@ -195,8 +196,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio var jumpInterface : Flow[UInt] = null var pluginExceptionPort : Flow[ExceptionCause] = null - var timerInterrupt : Bool = null - var externalInterrupt : Bool = null + var timerInterrupt, externalInterrupt : Bool = null + var timerInterruptS, externalInterruptS : Bool = null var privilege : Bits = null var selfException : Flow[ExceptionCause] = null var contextSwitching : Bool = null @@ -310,6 +311,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio //Define CSR registers + // Status => MXR, SUM, TVM, TW, TSE ? val misa = new Area{ val base = Reg(UInt(2 bits)) init(U"01") allowUnsetRegToAvoidLatch val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) allowUnsetRegToAvoidLatch @@ -334,12 +336,43 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val interrupt = Reg(Bool) val exceptionCode = Reg(UInt(exceptionCodeWidth bits)) } - val mbadaddr = Reg(UInt(xlen bits)) + val mtval = Reg(UInt(xlen bits)) val mcycle = Reg(UInt(64 bits)) randBoot() val minstret = Reg(UInt(64 bits)) randBoot() + val medeleg = Reg(Bits(32 bits)) init(0) + val mideleg = Reg(Bits(32 bits)) init(0) + + val sstatus = new Area{ + val SIE, SPIE = RegInit(False) + val SPP = RegInit(B"1") + } + + val sip = new Area{ + val SEIP = RegNext(externalInterruptS) init(False) + val STIP = RegNext(timerInterruptS) init(False) + val SSIP = RegInit(False) + } + val sie = new Area{ + val SEIE, STIE, SSIE = RegInit(False) + } + val stvec = Reg(UInt(xlen bits)).allowUnsetRegToAvoidLatch + val sscratch = if(sscratchGen) Reg(Bits(xlen bits)) else null + + val scause = new Area{ + val interrupt = Reg(Bool) + val exceptionCode = Reg(UInt(exceptionCodeWidth bits)) + } + val stval = Reg(UInt(xlen bits)) + val sepc = Reg(UInt(xlen bits)) + val satp = new Area{ + val PPN = Reg(Bits(22 bits)) + val ASID = Reg(Bits(9 bits)) + val MODE = Reg(Bits(1 bits)) + } + //Define CSR registers accessibility if(mvendorid != null) READ_ONLY(CSR.MVENDORID, U(mvendorid)) if(marchid != null) READ_ONLY(CSR.MARCHID , U(marchid )) @@ -357,7 +390,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio READ_WRITE(CSR.MSTATUS,11 -> mstatus.MPP, 7 -> mstatus.MPIE, 3 -> mstatus.MIE) if(mscratchGen) READ_WRITE(CSR.MSCRATCH, mscratch) mcauseAccess(CSR.MCAUSE, xlen-1 -> mcause.interrupt, 0 -> mcause.exceptionCode) - mbadaddrAccess(CSR.MBADADDR, mbadaddr) + mbadaddrAccess(CSR.MBADADDR, mtval) mcycleAccess(CSR.MCYCLE, mcycle(31 downto 0)) mcycleAccess(CSR.MCYCLEH, mcycle(63 downto 32)) minstretAccess(CSR.MINSTRET, minstret(31 downto 0)) @@ -490,7 +523,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } when(RegNext(exception)){ - mbadaddr := (if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionContext.badAddr else U(0)) + mtval := (if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionContext.badAddr else U(0)) mcause.exceptionCode := (if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionContext.code else U(0)) } From 9a3510f63df421d8abe0a09b842a0226d6a033f8 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 27 Sep 2018 19:03:57 +0200 Subject: [PATCH 13/56] Map all supervisor registers --- src/main/scala/vexriscv/Riscv.scala | 12 ++++++++++ .../scala/vexriscv/plugin/CsrPlugin.scala | 22 +++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/src/main/scala/vexriscv/Riscv.scala b/src/main/scala/vexriscv/Riscv.scala index 57251a4..f41e2c2 100644 --- a/src/main/scala/vexriscv/Riscv.scala +++ b/src/main/scala/vexriscv/Riscv.scala @@ -131,6 +131,18 @@ object Riscv{ def MCYCLEH = 0xB80 // MRW Upper 32 bits of mcycle, RV32I only. def MINSTRETH = 0xB82 // MRW Upper 32 bits of minstret, RV32I only. + val SSTATUS = 0x100 + val SIE = 0x104 + val STVEC = 0x105 + val SCOUNTEREN = 0x106 + val SSCRATCH = 0x140 + val SEPC = 0x141 + val SCAUSE = 0x142 + val SBADADDR = 0x143 + val SIP = 0x144 + val SATP = 0x180 + + def UCYCLE = 0xC00 // UR Machine ucycle counter. } diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 81f8531..276fb53 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -51,6 +51,13 @@ case class CsrPluginConfig( wfiGen : Boolean, ecallGen : Boolean, sscratchGen : Boolean = false, + stvecAccess : CsrAccess = CsrAccess.NONE, + sepcAccess : CsrAccess = CsrAccess.NONE, + scauseAccess : CsrAccess = CsrAccess.NONE, + sbadaddrAccess : CsrAccess = CsrAccess.NONE, + scycleAccess : CsrAccess = CsrAccess.NONE, + sinstretAccess : CsrAccess = CsrAccess.NONE, + satpAccess : CsrAccess = CsrAccess.NONE, deterministicInteruptionEntry : Boolean = false //Only used for simulatation purposes ){ @@ -380,6 +387,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio if(mhartid != null) READ_ONLY(CSR.MHARTID , U(mhartid )) //Machine CSR + //TODO machine mode shadow supervisor misaAccess(CSR.MISA, xlen-2 -> misa.base , 0 -> misa.extensions) READ_ONLY(CSR.MIP, 11 -> mip.MEIP, 7 -> mip.MTIP) READ_WRITE(CSR.MIP, 3 -> mip.MSIP) @@ -396,6 +404,20 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio minstretAccess(CSR.MINSTRET, minstret(31 downto 0)) minstretAccess(CSR.MINSTRETH, minstret(63 downto 32)) + //Supervisor CSR + READ_ONLY(CSR.SIP, 9 -> sip.SEIP, 5 -> sip.STIP) + READ_WRITE(CSR.SIP, 1 -> sip.SSIP) + READ_WRITE(CSR.SIE, 9 -> sie.SEIE, 5 -> sie.STIE, 1 -> sie.SSIE) + + stvecAccess(CSR.STVEC, stvec) + sepcAccess(CSR.SEPC, sepc) + READ_WRITE(CSR.SSTATUS,9 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE) + if(sscratchGen) READ_WRITE(CSR.SSCRATCH, sscratch) + scauseAccess(CSR.SCAUSE, xlen-1 -> scause.interrupt, 0 -> scause.exceptionCode) + sbadaddrAccess(CSR.SBADADDR, stval) + satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN) + + //User CSR ucycleAccess(CSR.UCYCLE, mcycle(31 downto 0)) From 992c21ddd1752624b3040afd4925983bca8f5dd0 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 27 Sep 2018 19:06:33 +0200 Subject: [PATCH 14/56] fix travis --- .travis.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis.yml b/.travis.yml index 7214425..87447ea 100644 --- a/.travis.yml +++ b/.travis.yml @@ -45,6 +45,8 @@ before_install: - sudo make install - cd .. + - git clone https://github.com/SpinalHDL/SpinalHDL.git + - cd VexRiscv #- curl -T README.md -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/README.md #- curl -X POST -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/publish From 37a1970ad68e23aa144bef0eda2737d9bfc97727 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 28 Sep 2018 16:02:33 +0200 Subject: [PATCH 15/56] wip --- src/main/scala/vexriscv/Riscv.scala | 1 + .../scala/vexriscv/plugin/CsrPlugin.scala | 141 +++++++++++++----- 2 files changed, 106 insertions(+), 36 deletions(-) diff --git a/src/main/scala/vexriscv/Riscv.scala b/src/main/scala/vexriscv/Riscv.scala index f41e2c2..7b28ad8 100644 --- a/src/main/scala/vexriscv/Riscv.scala +++ b/src/main/scala/vexriscv/Riscv.scala @@ -99,6 +99,7 @@ object Riscv{ def ECALL = M"00000000000000000000000001110011" def EBREAK = M"00000000000100000000000001110011" def MRET = M"00110000001000000000000001110011" + def SRET = M"00010000001000000000000001110011" def WFI = M"00010000010100000000000001110011" def FENCE = M"-----------------000-----0001111" diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 276fb53..bd8f112 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -205,13 +205,13 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio var pluginExceptionPort : Flow[ExceptionCause] = null var timerInterrupt, externalInterrupt : Bool = null var timerInterruptS, externalInterruptS : Bool = null - var privilege : Bits = null + var privilege : UInt = null var selfException : Flow[ExceptionCause] = null var contextSwitching : Bool = null override def isContextSwitching = contextSwitching object EnvCtrlEnum extends SpinalEnum(binarySequential){ - val NONE, EBREAK, MRET= newElement() + val NONE, EBREAK, XRET = newElement() val WFI = if(wfiGen) newElement() else null val ECALL = if(ecallGen) newElement() else null } @@ -263,8 +263,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio CSRRWI -> immediatActions, CSRRSI -> immediatActions, CSRRCI -> immediatActions, - // EBREAK -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.EBREAK)), //TODO - MRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.MRET)) + MRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.XRET)), + SRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.XRET)) )) if(wfiGen) decoderService.add(WFI, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.WFI)) if(ecallGen) decoderService.add(ECALL, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.ECALL)) @@ -284,7 +284,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio externalInterrupt = in Bool() setName("externalInterrupt") contextSwitching = Bool().setName("contextSwitching") - privilege = RegInit(B"11") + privilege = RegInit(U"11") if(catchIllegalAccess) selfException = newExceptionPort(pipeline.execute) @@ -328,7 +328,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val mepc = Reg(UInt(xlen bits)) val mstatus = new Area{ val MIE, MPIE = RegInit(False) - val MPP = RegInit(B"11") + val MPP = RegInit(U"11") } val mip = new Area{ val MEIP = RegNext(externalInterrupt) init(False) @@ -354,7 +354,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val sstatus = new Area{ val SIE, SPIE = RegInit(False) - val SPP = RegInit(B"1") + val SPP = RegInit(U"1") } val sip = new Area{ @@ -429,6 +429,50 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio minstret := minstret + 1 } + case class InterruptSource(cond : Bool, id : Int) + case class InterruptModel(privilege : Int, privilegeCond : Bool, sources : ArrayBuffer[InterruptSource]) + val interruptModel = ArrayBuffer[InterruptModel]() + interruptModel += InterruptModel(1, sstatus.SIE && privilege <= "01", ArrayBuffer( + InterruptSource(sip.STIP && sie.STIE, 5), + InterruptSource(sip.SSIP && sie.SSIE, 1), + InterruptSource(sip.SEIP && sie.SEIE, 9) + )) + + interruptModel += InterruptModel(3, mstatus.MIE , ArrayBuffer( + InterruptSource(mip.MTIP && mie.MTIE, 7), + InterruptSource(mip.MSIP && mie.MSIE, 3), + InterruptSource(mip.MEIP && mie.MEIE, 11) + )) + + case class DelegatorModel(value : Bits, source : Int, target : Int) + def solveDelegators(delegators : Seq[DelegatorModel], id : Int, upTo : Int): UInt = { + val filtredDelegators = delegators.filter(_.target <= upTo) + val ret = U(filtredDelegators.last.target, 2 bits) + for(d <- filtredDelegators){ + when(!d.value(id)){ + ret := d.source + } + } + ret + } + + def solveDelegators(delegators : Seq[DelegatorModel], id : UInt, upTo : UInt): UInt = { + val ret = U(delegators.last.target, 2 bits) + for(d <- delegators){ + when(!d.value(id) || d.target > upTo){ + ret := d.source + } + } + ret + } + + val interruptDelegators = ArrayBuffer[DelegatorModel]() + interruptDelegators += DelegatorModel(mideleg,0, 2) + + val exceptionDelegators = ArrayBuffer[DelegatorModel]() + exceptionDelegators += DelegatorModel(medeleg,0, 2) + + val mepcCaptureStage = if(exceptionPortsInfos.nonEmpty) writeBack else decode @@ -438,6 +482,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val exceptionValids = Vec(stages.map(s => Bool().setPartialName(s.getName()))) val exceptionValidsRegs = Vec(stages.map(s => Reg(Bool).init(False).setPartialName(s.getName()))).allowUnsetRegToAvoidLatch val exceptionContext = Reg(ExceptionCause()) + val exceptionTargetPrivilege = solveDelegators(exceptionDelegators, exceptionContext.code, privilege) val groupedByStage = exceptionPortsInfos.map(_.stage).distinct.map(s => { val stagePortsInfos = exceptionPortsInfos.filter(_.stage == s).sortWith(_.priority > _.priority) @@ -490,30 +535,31 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio - val interruptRequest = ((mip.MSIP && mie.MSIE) || (mip.MEIP && mie.MEIE) || (mip.MTIP && mie.MTIE)) && mstatus.MIE - val interrupt = interruptRequest && allowInterrupts - val exception = if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionValids.last && allowException else False - val writeBackWasWfi = if(wfiGen) RegNext(writeBack.arbitration.isFiring && writeBack.input(ENV_CTRL) === EnvCtrlEnum.WFI) init(False) else False + val interrupt = False + val interruptCode = UInt(4 bits).assignDontCare().addTag(Verilator.public) + val interruptTargetPrivilege = UInt(2 bits).assignDontCare() - val deteriministicLogic = if(deterministicInteruptionEntry) new Area{ - val counter = Reg(UInt(4 bits)) init(0) - when(!interruptRequest || !mstatus.MIE){ - counter := 0 - } otherwise { - when(counter < 6){ - when(writeBack.arbitration.isFiring){ - counter := counter + 1 - } + for(model <- interruptModel){ + when(model.privilegeCond){ + when(model.sources.map(_.cond).orR){ + interrupt := True } - val counterPlusPending = counter + CountOne(stages.tail.map(_.arbitration.isValid)) - when(counterPlusPending < 6){ - inhibateInterrupts() + for(source <- model.sources){ + when(source.cond){ + interruptCode := source.id + interruptTargetPrivilege := solveDelegators(interruptDelegators, source.id, model.privilege) + } } } } + interrupt.clearWhen(!allowInterrupts) + + val exception = if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionValids.last && allowException else False + val writeBackWasWfi = if(wfiGen) RegNext(writeBack.arbitration.isFiring && writeBack.input(ENV_CTRL) === EnvCtrlEnum.WFI) init(False) else False + //Used to make the pipeline empty softly (for interrupts) @@ -527,37 +573,60 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } //Interrupt/Exception entry logic - val interruptCode = ((mip.MEIP && mie.MEIE) ? U(11) | ((mip.MSIP && mie.MSIE) ? U(3) | U(7))).addTag(Verilator.public) val interruptJump = Bool.addTag(Verilator.public) interruptJump := interrupt && pipelineLiberator.done - when(exception || interruptJump){ + val hadException = RegNext(exception) init(False) + writeBack.arbitration.haltItself setWhen(exception) + + + val targetPrivilege = CombInit(interruptTargetPrivilege) + if(exceptionPortCtrl != null) when(hadException) { + targetPrivilege := exceptionPortCtrl.exceptionTargetPrivilege + } + + when(hadException || (interruptJump && !exception)){ jumpInterface.valid := True jumpInterface.payload := mtvec memory.arbitration.flushAll := True if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionValidsRegs.last := False - mstatus.MIE := False - mstatus.MPIE := mstatus.MIE - mstatus.MPP := privilege + + switch(targetPrivilege){ + is(1){ + sstatus.SIE := False + sstatus.SPIE := sstatus.SIE + sstatus.SPP := privilege + if(exceptionPortCtrl != null) { + stval := exceptionPortCtrl.exceptionContext.badAddr + scause.exceptionCode := exceptionPortCtrl.exceptionContext.code + } + } + is(3){ + mstatus.MIE := False + mstatus.MPIE := mstatus.MIE + mstatus.MPP := privilege + if(exceptionPortCtrl != null) { + mtval := exceptionPortCtrl.exceptionContext.badAddr + mcause.exceptionCode := exceptionPortCtrl.exceptionContext.code + } + } + } + mepc := mepcCaptureStage.input(PC) mcause.interrupt := interruptJump mcause.exceptionCode := interruptCode } - when(RegNext(exception)){ - mtval := (if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionContext.badAddr else U(0)) - mcause.exceptionCode := (if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionContext.code else U(0)) - } - - //Manage MRET instructions - when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.MRET) { + //Manage MRET / SRET instructions + when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.XRET) { when(memory.arbitration.isValid || writeBack.arbitration.isValid){ execute.arbitration.haltItself := True } otherwise { jumpInterface.valid := True jumpInterface.payload := mepc decode.arbitration.flushAll := True + //TODO mstatus.MIE := mstatus.MPIE privilege := mstatus.MPP } @@ -663,7 +732,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } } } - illegalAccess setWhen(privilege.asUInt < csrAddress(9 downto 8).asUInt) + illegalAccess setWhen(privilege < csrAddress(9 downto 8).asUInt) }) } } From 5ad7c39f472d95fa92e43cbb46f6482850c5f834 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 29 Sep 2018 12:04:58 +0200 Subject: [PATCH 16/56] wip --- .../scala/vexriscv/plugin/CsrPlugin.scala | 85 +++++++++++-------- 1 file changed, 51 insertions(+), 34 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index bd8f112..de80f76 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -211,7 +211,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio override def isContextSwitching = contextSwitching object EnvCtrlEnum extends SpinalEnum(binarySequential){ - val NONE, EBREAK, XRET = newElement() + val NONE, XRET = newElement() val WFI = if(wfiGen) newElement() else null val ECALL = if(ecallGen) newElement() else null } @@ -385,17 +385,16 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio if(marchid != null) READ_ONLY(CSR.MARCHID , U(marchid )) if(mimpid != null) READ_ONLY(CSR.MIMPID , U(mimpid )) if(mhartid != null) READ_ONLY(CSR.MHARTID , U(mhartid )) + misaAccess(CSR.MISA, xlen-2 -> misa.base , 0 -> misa.extensions) //Machine CSR - //TODO machine mode shadow supervisor - misaAccess(CSR.MISA, xlen-2 -> misa.base , 0 -> misa.extensions) + READ_WRITE(CSR.MSTATUS,11 -> mstatus.MPP, 7 -> mstatus.MPIE, 3 -> mstatus.MIE) READ_ONLY(CSR.MIP, 11 -> mip.MEIP, 7 -> mip.MTIP) READ_WRITE(CSR.MIP, 3 -> mip.MSIP) READ_WRITE(CSR.MIE, 11 -> mie.MEIE, 7 -> mie.MTIE, 3 -> mie.MSIE) mtvecAccess(CSR.MTVEC, mtvec) mepcAccess(CSR.MEPC, mepc) - READ_WRITE(CSR.MSTATUS,11 -> mstatus.MPP, 7 -> mstatus.MPIE, 3 -> mstatus.MIE) if(mscratchGen) READ_WRITE(CSR.MSCRATCH, mscratch) mcauseAccess(CSR.MCAUSE, xlen-1 -> mcause.interrupt, 0 -> mcause.exceptionCode) mbadaddrAccess(CSR.MBADADDR, mtval) @@ -405,13 +404,15 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio minstretAccess(CSR.MINSTRETH, minstret(63 downto 32)) //Supervisor CSR + for(offset <- List(0, 0x200)) { + READ_WRITE(CSR.SSTATUS,8 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE) + } READ_ONLY(CSR.SIP, 9 -> sip.SEIP, 5 -> sip.STIP) READ_WRITE(CSR.SIP, 1 -> sip.SSIP) READ_WRITE(CSR.SIE, 9 -> sie.SEIE, 5 -> sie.STIE, 1 -> sie.SSIE) stvecAccess(CSR.STVEC, stvec) sepcAccess(CSR.SEPC, sepc) - READ_WRITE(CSR.SSTATUS,9 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE) if(sscratchGen) READ_WRITE(CSR.SSCRATCH, sscratch) scauseAccess(CSR.SCAUSE, xlen-1 -> scause.interrupt, 0 -> scause.exceptionCode) sbadaddrAccess(CSR.SBADADDR, stval) @@ -577,7 +578,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio interruptJump := interrupt && pipelineLiberator.done val hadException = RegNext(exception) init(False) - writeBack.arbitration.haltItself setWhen(exception) + writeBack.arbitration.haltItself setWhen(exception && !hadException) val targetPrivilege = CombInit(interruptTargetPrivilege) @@ -618,32 +619,6 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } - //Manage MRET / SRET instructions - when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.XRET) { - when(memory.arbitration.isValid || writeBack.arbitration.isValid){ - execute.arbitration.haltItself := True - } otherwise { - jumpInterface.valid := True - jumpInterface.payload := mepc - decode.arbitration.flushAll := True - //TODO - mstatus.MIE := mstatus.MPIE - privilege := mstatus.MPP - } - } - - //Manage ECALL instructions - if(ecallGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.ECALL){ - pluginExceptionPort.valid := True - pluginExceptionPort.code := 11 - } - - //Manage WFI instructions - if(wfiGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.WFI){ - when(!interrupt){ - execute.arbitration.haltItself := True - } - } contextSwitching := jumpInterface.valid @@ -664,14 +639,56 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio import execute._ val illegalAccess = arbitration.isValid && input(IS_CSR) + val illegalInstruction = False if(catchIllegalAccess) { - val illegalInstruction = arbitration.isValid && privilege === 0 && (input(ENV_CTRL) === EnvCtrlEnum.EBREAK || input(ENV_CTRL) === EnvCtrlEnum.MRET) - selfException.valid := illegalAccess || illegalInstruction selfException.code := 2 selfException.badAddr.assignDontCare() } + //TODO jump interface logic change to avoid combinatorial path on the valid ? + + //Manage MRET / SRET instructions + when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.XRET) { + illegalInstruction setWhen(execute.input(INSTRUCTION)(29 downto 28).asUInt =/= privilege) + jumpInterface.payload := mepc + when(memory.arbitration.isValid || writeBack.arbitration.isValid){ + execute.arbitration.haltItself := True + } elsewhen (execute.arbitration.isFiring) { + jumpInterface.valid := True + decode.arbitration.flushAll := True + switch(execute.input(INSTRUCTION)(29 downto 28)){ + is(3){ + mstatus.MIE := mstatus.MPIE + mstatus.MPP := U"00" + mstatus.MPIE := True + privilege := mstatus.MPP + } + is(1){ + sstatus.SIE := sstatus.SPIE + sstatus.SPP := U"00" + sstatus.SPIE := True + privilege := sstatus.SPP + } + } + } + } + + //Manage ECALL instructions + if(ecallGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.ECALL){ + pluginExceptionPort.valid := True + pluginExceptionPort.code := 11 + } + + //Manage WFI instructions + if(wfiGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.WFI){ + when(!interrupt){ + execute.arbitration.haltItself := True + } + } + + + val imm = IMM(input(INSTRUCTION)) val writeSrc = input(INSTRUCTION)(14) ? imm.z.asBits.resized | input(SRC1) val readData = B(0, 32 bits) From 39c6bc11d6a0f3ca692a154eb2f0c4295b18795d Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 29 Sep 2018 19:04:20 +0200 Subject: [PATCH 17/56] Pass basic regression again --- src/main/scala/vexriscv/TestsWorkspace.scala | 2 +- src/main/scala/vexriscv/VexRiscv.scala | 6 +- .../scala/vexriscv/plugin/BranchPlugin.scala | 2 +- .../scala/vexriscv/plugin/CsrPlugin.scala | 163 +++++++++++------- .../scala/vexriscv/plugin/SrcPlugin.scala | 3 +- 5 files changed, 110 insertions(+), 66 deletions(-) diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index 8d50ad9..ac19f96 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -129,7 +129,7 @@ object TestsWorkspace { divUnrollFactor = 1 ), // new DivPlugin, - new CsrPlugin(CsrPluginConfig.all(0x80000020l).copy(deterministicInteruptionEntry = false)), + new CsrPlugin(CsrPluginConfig.all2(0x80000020l).copy(deterministicInteruptionEntry = false)), new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( earlyBranch = true, diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index afd29bb..bd1ef1c 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -44,6 +44,10 @@ case class VexRiscvConfig(){ object SRC_USE_SUB_LESS extends Stageable(Bool) object SRC_LESS_UNSIGNED extends Stageable(Bool) + + object DISRUPT_IN_MEMORY_STAGE extends Stageable(Bool) + object DISRUPT_IN_WRITEBACK_STAGE extends Stageable(Bool) + //Formal verification purposes object FORMAL_HALT extends Stageable(Bool) object FORMAL_PC_NEXT extends Stageable(UInt(32 bits)) @@ -56,7 +60,7 @@ case class VexRiscvConfig(){ object Src1CtrlEnum extends SpinalEnum(binarySequential){ - val RS, IMU, PC_INCREMENT = newElement() //IMU, IMZ IMJB + val RS, IMU, PC_INCREMENT, URS1 = newElement() //IMU, IMZ IMJB } object Src2CtrlEnum extends SpinalEnum(binarySequential){ diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index eff2f09..55e69ad 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -178,7 +178,7 @@ class BranchPlugin(earlyBranch : Boolean, stages(indexOf(branchStage) - 1).arbitration.flushAll := True } - if(catchAddressMisaligned) { //TODO conflict with instruction cache two stage + if(catchAddressMisaligned) { branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && (if(pipeline(RVC_GEN)) jumpInterface.payload(0 downto 0) =/= 0 else jumpInterface.payload(1 downto 0) =/= 0) branchExceptionPort.code := 0 branchExceptionPort.badAddr := jumpInterface.payload diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index de80f76..5ca5eae 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -4,6 +4,7 @@ import spinal.core._ import spinal.lib._ import vexriscv._ import vexriscv.Riscv._ +import vexriscv.plugin.IntAluPlugin.{ALU_BITWISE_CTRL, ALU_CTRL, AluBitwiseCtrlEnum, AluCtrlEnum} import scala.collection.mutable.ArrayBuffer import scala.collection.mutable @@ -50,6 +51,7 @@ case class CsrPluginConfig( ucycleAccess : CsrAccess, wfiGen : Boolean, ecallGen : Boolean, + supervisorGen : Boolean = false, sscratchGen : Boolean = false, stvecAccess : CsrAccess = CsrAccess.NONE, sepcAccess : CsrAccess = CsrAccess.NONE, @@ -92,6 +94,36 @@ object CsrPluginConfig{ ucycleAccess = CsrAccess.READ_ONLY ) + def all2(mtvecInit : BigInt) : CsrPluginConfig = CsrPluginConfig( + catchIllegalAccess = true, + mvendorid = 11, + marchid = 22, + mimpid = 33, + mhartid = 0, + misaExtensionsInit = 66, + misaAccess = CsrAccess.READ_WRITE, + mtvecAccess = CsrAccess.READ_WRITE, + mtvecInit = mtvecInit, + mepcAccess = CsrAccess.READ_WRITE, + mscratchGen = true, + mcauseAccess = CsrAccess.READ_WRITE, + mbadaddrAccess = CsrAccess.READ_WRITE, + mcycleAccess = CsrAccess.READ_WRITE, + minstretAccess = CsrAccess.READ_WRITE, + ecallGen = true, + wfiGen = true, + ucycleAccess = CsrAccess.READ_ONLY, + supervisorGen = true, + sscratchGen = true, + stvecAccess = CsrAccess.READ_WRITE, + sepcAccess = CsrAccess.READ_WRITE, + scauseAccess = CsrAccess.READ_WRITE, + sbadaddrAccess = CsrAccess.READ_WRITE, + scycleAccess = CsrAccess.READ_WRITE, + sinstretAccess = CsrAccess.READ_WRITE, + satpAccess = CsrAccess.READ_WRITE + ) + def small(mtvecInit : BigInt) = CsrPluginConfig( catchIllegalAccess = false, mvendorid = null, @@ -202,7 +234,6 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } var jumpInterface : Flow[UInt] = null - var pluginExceptionPort : Flow[ExceptionCause] = null var timerInterrupt, externalInterrupt : Bool = null var timerInterruptS, externalInterruptS : Bool = null var privilege : UInt = null @@ -241,8 +272,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val defaultCsrActions = List[(Stageable[_ <: BaseType],Any)]( IS_CSR -> True, REGFILE_WRITE_VALID -> True, - BYPASSABLE_EXECUTE_STAGE -> True, - BYPASSABLE_MEMORY_STAGE -> True + ALU_BITWISE_CTRL -> AluBitwiseCtrlEnum.SRC1, + ALU_CTRL -> AluCtrlEnum.BITWISE ) val nonImmediatActions = defaultCsrActions ++ List( @@ -250,7 +281,9 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio RS1_USE -> True ) - val immediatActions = defaultCsrActions + val immediatActions = defaultCsrActions ++ List( + SRC1_CTRL -> Src1CtrlEnum.URS1 + ) val decoderService = pipeline.service(classOf[DecoderService]) @@ -274,20 +307,19 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio jumpInterface.valid := False jumpInterface.payload.assignDontCare() - if(ecallGen) { - pluginExceptionPort = newExceptionPort(pipeline.execute) - pluginExceptionPort.valid := False - pluginExceptionPort.payload.assignDontCare() - } timerInterrupt = in Bool() setName("timerInterrupt") externalInterrupt = in Bool() setName("externalInterrupt") + if(supervisorGen){ + timerInterruptS = in Bool() setName("timerInterruptS") + externalInterruptS = in Bool() setName("externalInterruptS") + } contextSwitching = Bool().setName("contextSwitching") - privilege = RegInit(U"11") + privilege = RegInit(U"11").setName("CsrPlugin_privilege") - if(catchIllegalAccess) - selfException = newExceptionPort(pipeline.execute) + if(catchIllegalAccess || ecallGen) + selfException = newExceptionPort(pipeline.writeBack) allowInterrupts = True allowException = True @@ -404,8 +436,9 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio minstretAccess(CSR.MINSTRETH, minstret(63 downto 32)) //Supervisor CSR + WRITE_ONLY(CSR.SSTATUS,8 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE) for(offset <- List(0, 0x200)) { - READ_WRITE(CSR.SSTATUS,8 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE) + READ_ONLY(CSR.SSTATUS,8 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE) } READ_ONLY(CSR.SIP, 9 -> sip.SEIP, 5 -> sip.STIP) READ_WRITE(CSR.SIP, 1 -> sip.SSIP) @@ -446,9 +479,9 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio )) case class DelegatorModel(value : Bits, source : Int, target : Int) - def solveDelegators(delegators : Seq[DelegatorModel], id : Int, upTo : Int): UInt = { - val filtredDelegators = delegators.filter(_.target <= upTo) - val ret = U(filtredDelegators.last.target, 2 bits) + def solveDelegators(delegators : Seq[DelegatorModel], id : Int, lowerBound : Int): UInt = { + val filtredDelegators = delegators.filter(_.target >= lowerBound) + val ret = U(lowerBound, 2 bits) for(d <- filtredDelegators){ when(!d.value(id)){ ret := d.source @@ -457,10 +490,10 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio ret } - def solveDelegators(delegators : Seq[DelegatorModel], id : UInt, upTo : UInt): UInt = { + def solveDelegators(delegators : Seq[DelegatorModel], id : UInt, lowerBound : UInt): UInt = { val ret = U(delegators.last.target, 2 bits) for(d <- delegators){ - when(!d.value(id) || d.target > upTo){ + when(!d.value(id) || d.target < lowerBound){ ret := d.source } } @@ -468,10 +501,10 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } val interruptDelegators = ArrayBuffer[DelegatorModel]() - interruptDelegators += DelegatorModel(mideleg,0, 2) + interruptDelegators += DelegatorModel(mideleg,3, 1) val exceptionDelegators = ArrayBuffer[DelegatorModel]() - exceptionDelegators += DelegatorModel(medeleg,0, 2) + exceptionDelegators += DelegatorModel(medeleg,3, 1) val mepcCaptureStage = if(exceptionPortsInfos.nonEmpty) writeBack else decode @@ -578,7 +611,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio interruptJump := interrupt && pipelineLiberator.done val hadException = RegNext(exception) init(False) - writeBack.arbitration.haltItself setWhen(exception && !hadException) + exception clearWhen(hadException) + writeBack.arbitration.haltItself setWhen(exception) val targetPrivilege = CombInit(interruptTargetPrivilege) @@ -586,6 +620,11 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio targetPrivilege := exceptionPortCtrl.exceptionTargetPrivilege } + val trapCause = CombInit(interruptCode) + if(exceptionPortCtrl != null) when( hadException){ + trapCause := exceptionPortCtrl.exceptionContext.code + } + when(hadException || (interruptJump && !exception)){ jumpInterface.valid := True jumpInterface.payload := mtvec @@ -596,30 +635,30 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio is(1){ sstatus.SIE := False sstatus.SPIE := sstatus.SIE - sstatus.SPP := privilege + sstatus.SPP := privilege(0 downto 0) + scause.interrupt := !hadException + scause.exceptionCode := trapCause + sepc := mepcCaptureStage.input(PC) if(exceptionPortCtrl != null) { stval := exceptionPortCtrl.exceptionContext.badAddr - scause.exceptionCode := exceptionPortCtrl.exceptionContext.code } } is(3){ mstatus.MIE := False mstatus.MPIE := mstatus.MIE mstatus.MPP := privilege + mcause.interrupt := !hadException + mcause.exceptionCode := trapCause + mepc := mepcCaptureStage.input(PC) if(exceptionPortCtrl != null) { mtval := exceptionPortCtrl.exceptionContext.badAddr - mcause.exceptionCode := exceptionPortCtrl.exceptionContext.code } } } - mepc := mepcCaptureStage.input(PC) - mcause.interrupt := interruptJump - mcause.exceptionCode := interruptCode } - contextSwitching := jumpInterface.valid //CSR read/write instructions management @@ -632,79 +671,79 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio || (input(INSTRUCTION)(14 downto 13) === "11" && imm.z === 0) ) insert(CSR_READ_OPCODE) := input(INSTRUCTION)(13 downto 7) =/= B"0100000" - //Assure that the CSR access are in the execute stage when there is nothing left in memory/writeback stages to avoid exception hazard - arbitration.haltItself setWhen(arbitration.isValid && input(IS_CSR) && (execute.arbitration.isValid || memory.arbitration.isValid)) } - execute plug new Area { + + + execute plug new Area{ import execute._ + //Manage WFI instructions + if(wfiGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){ + when(!interrupt){ + arbitration.haltItself := True + } + } + } + + writeBack plug new Area { + import writeBack._ + def previousStage = memory val illegalAccess = arbitration.isValid && input(IS_CSR) val illegalInstruction = False - if(catchIllegalAccess) { + if(selfException != null) { selfException.valid := illegalAccess || illegalInstruction selfException.code := 2 selfException.badAddr.assignDontCare() } - //TODO jump interface logic change to avoid combinatorial path on the valid ? - //Manage MRET / SRET instructions - when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.XRET) { - illegalInstruction setWhen(execute.input(INSTRUCTION)(29 downto 28).asUInt =/= privilege) + when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.XRET) { jumpInterface.payload := mepc - when(memory.arbitration.isValid || writeBack.arbitration.isValid){ - execute.arbitration.haltItself := True - } elsewhen (execute.arbitration.isFiring) { + when(input(INSTRUCTION)(29 downto 28).asUInt =/= privilege) { + illegalInstruction := True + } otherwise{ jumpInterface.valid := True - decode.arbitration.flushAll := True - switch(execute.input(INSTRUCTION)(29 downto 28)){ + previousStage.arbitration.flushAll := True + switch(input(INSTRUCTION)(29 downto 28)){ is(3){ mstatus.MIE := mstatus.MPIE mstatus.MPP := U"00" mstatus.MPIE := True - privilege := mstatus.MPP + privilege := mstatus.MPP //TODO check MPP value } is(1){ sstatus.SIE := sstatus.SPIE - sstatus.SPP := U"00" + sstatus.SPP := U"0" sstatus.SPIE := True - privilege := sstatus.SPP + privilege := U"0" @@ sstatus.SPP } } } } //Manage ECALL instructions - if(ecallGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.ECALL){ - pluginExceptionPort.valid := True - pluginExceptionPort.code := 11 + if(ecallGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.ECALL){ + selfException.valid := True + selfException.code := 11 } - //Manage WFI instructions - if(wfiGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.WFI){ - when(!interrupt){ - execute.arbitration.haltItself := True - } - } - - val imm = IMM(input(INSTRUCTION)) - val writeSrc = input(INSTRUCTION)(14) ? imm.z.asBits.resized | input(SRC1) + val writeSrc = input(REGFILE_WRITE_DATA) val readData = B(0, 32 bits) - def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT - val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck) +// def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT +// val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck) val writeData = input(INSTRUCTION)(13).mux( False -> writeSrc, - True -> Mux(input(INSTRUCTION)(12), readDataReg & ~writeSrc, readDataReg | writeSrc) + True -> Mux(input(INSTRUCTION)(12), readData & ~writeSrc, readData | writeSrc) ) val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) - arbitration.haltItself setWhen(writeInstruction && !readDataRegValid) - val writeEnable = writeInstruction && readDataRegValid - val readEnable = readInstruction && !readDataRegValid +// arbitration.haltItself setWhen(writeInstruction && !readDataRegValid) + val writeEnable = writeInstruction// && readDataRegValid + val readEnable = readInstruction// && !readDataRegValid when(arbitration.isValid && input(IS_CSR)) { output(REGFILE_WRITE_DATA) := readData diff --git a/src/main/scala/vexriscv/plugin/SrcPlugin.scala b/src/main/scala/vexriscv/plugin/SrcPlugin.scala index da9b151..d319b9b 100644 --- a/src/main/scala/vexriscv/plugin/SrcPlugin.scala +++ b/src/main/scala/vexriscv/plugin/SrcPlugin.scala @@ -16,7 +16,8 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = insert(SRC1) := input(SRC1_CTRL).mux( Src1CtrlEnum.RS -> output(RS1), Src1CtrlEnum.PC_INCREMENT -> (if(pipeline(RVC_GEN)) Mux(input(IS_RVC), B(2), B(4)) else B(4)).resized, - Src1CtrlEnum.IMU -> imm.u.resized + Src1CtrlEnum.IMU -> imm.u.resized, + Src1CtrlEnum.URS1 -> input(INSTRUCTION)(Riscv.rs1Range).resized ) insert(SRC2) := input(SRC2_CTRL).mux( Src2CtrlEnum.RS -> output(RS2), From 7770eefa3ba83b773ac2af883d8f651ae415ce5c Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 30 Sep 2018 12:57:08 +0200 Subject: [PATCH 18/56] wip --- src/main/scala/vexriscv/Riscv.scala | 1 + .../scala/vexriscv/demo/SynthesisBench.scala | 10 +- .../scala/vexriscv/plugin/CsrPlugin.scala | 158 ++++++++++-------- src/test/scala/vexriscv/DhrystoneBench.scala | 3 + 4 files changed, 98 insertions(+), 74 deletions(-) diff --git a/src/main/scala/vexriscv/Riscv.scala b/src/main/scala/vexriscv/Riscv.scala index 7b28ad8..a7bc86a 100644 --- a/src/main/scala/vexriscv/Riscv.scala +++ b/src/main/scala/vexriscv/Riscv.scala @@ -146,5 +146,6 @@ object Riscv{ def UCYCLE = 0xC00 // UR Machine ucycle counter. + def UCYCLEH = 0xC80 } } diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index f908586..7b2bdd9 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -101,20 +101,20 @@ object VexRiscvSynthesisBench { } - val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) -//val rtls = List(smallestNoCsr) +// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) + val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallAndProductive, full) - val targets = XilinxStdTargets( + val targets =/* XilinxStdTargets( vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" ) ++ AlteraStdTargets( quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" - ) ++ IcestormStdTargets() + ) ++ */IcestormStdTargets().take(1) // val targets = IcestormStdTargets() - Bench(rtls, targets, "/eda/tmp/") + Bench(rtls, targets, "/home/spinalvm/tmp/") } } diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 5ca5eae..43f6754 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -60,8 +60,9 @@ case class CsrPluginConfig( scycleAccess : CsrAccess = CsrAccess.NONE, sinstretAccess : CsrAccess = CsrAccess.NONE, satpAccess : CsrAccess = CsrAccess.NONE, + medelegAccess : CsrAccess = CsrAccess.NONE, + midelegAccess : CsrAccess = CsrAccess.NONE, deterministicInteruptionEntry : Boolean = false //Only used for simulatation purposes - ){ assert(!ucycleAccess.canWrite) @@ -121,7 +122,9 @@ object CsrPluginConfig{ sbadaddrAccess = CsrAccess.READ_WRITE, scycleAccess = CsrAccess.READ_WRITE, sinstretAccess = CsrAccess.READ_WRITE, - satpAccess = CsrAccess.READ_WRITE + satpAccess = CsrAccess.READ_WRITE, + medelegAccess = CsrAccess.READ_WRITE, + midelegAccess = CsrAccess.READ_WRITE ) def small(mtvecInit : BigInt) = CsrPluginConfig( @@ -335,20 +338,20 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio import pipeline.config._ val fetcher = service(classOf[IBusFetcher]) - pipeline plug new Area{ - //Define CSR mapping utilities - implicit class CsrAccessPimper(csrAccess : CsrAccess){ - def apply(csrAddress : Int, thats : (Int, Data)*) : Unit = { - if(csrAccess == `WRITE_ONLY` || csrAccess == `READ_WRITE`) for(that <- thats) csrMapping.w(csrAddress,that._1, that._2) - if(csrAccess == `READ_ONLY` || csrAccess == `READ_WRITE`) for(that <- thats) csrMapping.r(csrAddress,that._1, that._2) - } - def apply(csrAddress : Int, that : Data) : Unit = { - if(csrAccess == `WRITE_ONLY` || csrAccess == `READ_WRITE`) csrMapping.w(csrAddress, 0, that) - if(csrAccess == `READ_ONLY` || csrAccess == `READ_WRITE`) csrMapping.r(csrAddress, 0, that) - } + //Define CSR mapping utilities + implicit class CsrAccessPimper(csrAccess : CsrAccess){ + def apply(csrAddress : Int, thats : (Int, Data)*) : Unit = { + if(csrAccess == `WRITE_ONLY` || csrAccess == `READ_WRITE`) for(that <- thats) csrMapping.w(csrAddress,that._1, that._2) + if(csrAccess == `READ_ONLY` || csrAccess == `READ_WRITE`) for(that <- thats) csrMapping.r(csrAddress,that._1, that._2) } + def apply(csrAddress : Int, that : Data) : Unit = { + if(csrAccess == `WRITE_ONLY` || csrAccess == `READ_WRITE`) csrMapping.w(csrAddress, 0, that) + if(csrAccess == `READ_ONLY` || csrAccess == `READ_WRITE`) csrMapping.r(csrAddress, 0, that) + } + } + val machineCsr = pipeline plug new Area{ //Define CSR registers // Status => MXR, SUM, TVM, TW, TSE ? val misa = new Area{ @@ -384,35 +387,6 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val medeleg = Reg(Bits(32 bits)) init(0) val mideleg = Reg(Bits(32 bits)) init(0) - val sstatus = new Area{ - val SIE, SPIE = RegInit(False) - val SPP = RegInit(U"1") - } - - val sip = new Area{ - val SEIP = RegNext(externalInterruptS) init(False) - val STIP = RegNext(timerInterruptS) init(False) - val SSIP = RegInit(False) - } - val sie = new Area{ - val SEIE, STIE, SSIE = RegInit(False) - } - val stvec = Reg(UInt(xlen bits)).allowUnsetRegToAvoidLatch - val sscratch = if(sscratchGen) Reg(Bits(xlen bits)) else null - - val scause = new Area{ - val interrupt = Reg(Bool) - val exceptionCode = Reg(UInt(exceptionCodeWidth bits)) - } - val stval = Reg(UInt(xlen bits)) - val sepc = Reg(UInt(xlen bits)) - val satp = new Area{ - val PPN = Reg(Bits(22 bits)) - val ASID = Reg(Bits(9 bits)) - val MODE = Reg(Bits(1 bits)) - } - - //Define CSR registers accessibility if(mvendorid != null) READ_ONLY(CSR.MVENDORID, U(mvendorid)) if(marchid != null) READ_ONLY(CSR.MARCHID , U(marchid )) if(mimpid != null) READ_ONLY(CSR.MIMPID , U(mimpid )) @@ -435,26 +409,67 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio minstretAccess(CSR.MINSTRET, minstret(31 downto 0)) minstretAccess(CSR.MINSTRETH, minstret(63 downto 32)) - //Supervisor CSR - WRITE_ONLY(CSR.SSTATUS,8 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE) - for(offset <- List(0, 0x200)) { - READ_ONLY(CSR.SSTATUS,8 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE) - } - READ_ONLY(CSR.SIP, 9 -> sip.SEIP, 5 -> sip.STIP) - READ_WRITE(CSR.SIP, 1 -> sip.SSIP) - READ_WRITE(CSR.SIE, 9 -> sie.SEIE, 5 -> sie.STIE, 1 -> sie.SSIE) - - stvecAccess(CSR.STVEC, stvec) - sepcAccess(CSR.SEPC, sepc) - if(sscratchGen) READ_WRITE(CSR.SSCRATCH, sscratch) - scauseAccess(CSR.SCAUSE, xlen-1 -> scause.interrupt, 0 -> scause.exceptionCode) - sbadaddrAccess(CSR.SBADADDR, stval) - satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN) - + medelegAccess(CSR.MEDELEG, medeleg) + midelegAccess(CSR.MIDELEG, mideleg) //User CSR ucycleAccess(CSR.UCYCLE, mcycle(31 downto 0)) + ucycleAccess(CSR.UCYCLEH, mcycle(31 downto 0)) + } + val supervisorCsr = ifGen(supervisorGen) { + pipeline plug new Area { + val sstatus = new Area { + val SIE, SPIE = RegInit(False) + val SPP = RegInit(U"1") + } + + val sip = new Area { + val SEIP = RegNext(externalInterruptS) init (False) + val STIP = RegNext(timerInterruptS) init (False) + val SSIP = RegInit(False) + } + val sie = new Area { + val SEIE, STIE, SSIE = RegInit(False) + } + val stvec = Reg(UInt(xlen bits)).allowUnsetRegToAvoidLatch + val sscratch = if (sscratchGen) Reg(Bits(xlen bits)) else null + + val scause = new Area { + val interrupt = Reg(Bool) + val exceptionCode = Reg(UInt(exceptionCodeWidth bits)) + } + val stval = Reg(UInt(xlen bits)) + val sepc = Reg(UInt(xlen bits)) + val satp = new Area { + val PPN = Reg(Bits(22 bits)) + val ASID = Reg(Bits(9 bits)) + val MODE = Reg(Bits(1 bits)) + } + + //Supervisor CSR + WRITE_ONLY(CSR.SSTATUS,8 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE) + for(offset <- List(0, 0x200)) { + READ_ONLY(CSR.SSTATUS,8 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE) + } + READ_ONLY(CSR.SIP, 9 -> sip.SEIP, 5 -> sip.STIP) + READ_WRITE(CSR.SIP, 1 -> sip.SSIP) + READ_WRITE(CSR.SIE, 9 -> sie.SEIE, 5 -> sie.STIE, 1 -> sie.SSIE) + + stvecAccess(CSR.STVEC, stvec) + sepcAccess(CSR.SEPC, sepc) + if(sscratchGen) READ_WRITE(CSR.SSCRATCH, sscratch) + scauseAccess(CSR.SCAUSE, xlen-1 -> scause.interrupt, 0 -> scause.exceptionCode) + sbadaddrAccess(CSR.SBADADDR, stval) + satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN) + } + } + + + + pipeline plug new Area{ + import machineCsr._ + import supervisorCsr._ //Manage counters @@ -466,7 +481,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio case class InterruptSource(cond : Bool, id : Int) case class InterruptModel(privilege : Int, privilegeCond : Bool, sources : ArrayBuffer[InterruptSource]) val interruptModel = ArrayBuffer[InterruptModel]() - interruptModel += InterruptModel(1, sstatus.SIE && privilege <= "01", ArrayBuffer( + if(supervisorGen) interruptModel += InterruptModel(1, sstatus.SIE && privilege <= "01", ArrayBuffer( InterruptSource(sip.STIP && sie.STIE, 5), InterruptSource(sip.SSIP && sie.SSIE, 1), InterruptSource(sip.SEIP && sie.SEIE, 9) @@ -491,6 +506,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } def solveDelegators(delegators : Seq[DelegatorModel], id : UInt, lowerBound : UInt): UInt = { + if(delegators.isEmpty) return CombInit(lowerBound) val ret = U(delegators.last.target, 2 bits) for(d <- delegators){ when(!d.value(id) || d.target < lowerBound){ @@ -501,10 +517,10 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } val interruptDelegators = ArrayBuffer[DelegatorModel]() - interruptDelegators += DelegatorModel(mideleg,3, 1) + if(midelegAccess.canWrite) interruptDelegators += DelegatorModel(mideleg,3, 1) val exceptionDelegators = ArrayBuffer[DelegatorModel]() - exceptionDelegators += DelegatorModel(medeleg,3, 1) + if(medelegAccess.canWrite) exceptionDelegators += DelegatorModel(medeleg,3, 1) val mepcCaptureStage = if(exceptionPortsInfos.nonEmpty) writeBack else decode @@ -632,17 +648,18 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionValidsRegs.last := False switch(targetPrivilege){ - is(1){ - sstatus.SIE := False + if(supervisorGen) is(1) { + sstatus.SIE := False sstatus.SPIE := sstatus.SIE - sstatus.SPP := privilege(0 downto 0) + sstatus.SPP := privilege(0 downto 0) scause.interrupt := !hadException scause.exceptionCode := trapCause sepc := mepcCaptureStage.input(PC) - if(exceptionPortCtrl != null) { + if (exceptionPortCtrl != null) { stval := exceptionPortCtrl.exceptionContext.badAddr } } + is(3){ mstatus.MIE := False mstatus.MPIE := mstatus.MIE @@ -684,9 +701,12 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } } - writeBack plug new Area { - import writeBack._ - def previousStage = memory +// writeBack plug new Area { +// import writeBack._ +// def previousStage = memory + execute plug new Area { + import execute._ + def previousStage = decode val illegalAccess = arbitration.isValid && input(IS_CSR) val illegalInstruction = False @@ -711,7 +731,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio mstatus.MPIE := True privilege := mstatus.MPP //TODO check MPP value } - is(1){ + if(supervisorGen) is(1){ sstatus.SIE := sstatus.SPIE sstatus.SPP := U"0" sstatus.SPIE := True diff --git a/src/test/scala/vexriscv/DhrystoneBench.scala b/src/test/scala/vexriscv/DhrystoneBench.scala index 7358574..0302b94 100644 --- a/src/test/scala/vexriscv/DhrystoneBench.scala +++ b/src/test/scala/vexriscv/DhrystoneBench.scala @@ -22,10 +22,13 @@ class DhrystoneBench extends FunSuite{ } val report = new StringBuilder() def getDmips(name : String, gen : => Unit, testCmd : String): Unit = { + var genPassed = false test(name + "_gen") { gen + genPassed = true } test(name + "_test"){ + assert(genPassed) val str = doCmd(testCmd) assert(!str.contains("FAIL")) val intFind = "(\\d+\\.?)+".r From 65a8d84d30a4ddae2e732edc3e0cfb8d89f19ed9 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 1 Oct 2018 12:13:05 +0200 Subject: [PATCH 19/56] Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling (uncached DBus TODO) --- src/main/scala/vexriscv/VexRiscv.scala | 3 +- .../scala/vexriscv/demo/SynthesisBench.scala | 8 +- .../scala/vexriscv/plugin/BranchPlugin.scala | 6 +- .../scala/vexriscv/plugin/CsrPlugin.scala | 106 ++++++++++-------- .../vexriscv/plugin/DBusCachedPlugin.scala | 2 +- .../vexriscv/plugin/DBusSimplePlugin.scala | 2 +- .../scala/vexriscv/plugin/DebugPlugin.scala | 4 +- .../vexriscv/plugin/HazardSimplePlugin.scala | 9 +- 8 files changed, 81 insertions(+), 59 deletions(-) diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index bd1ef1c..7077096 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -45,8 +45,7 @@ case class VexRiscvConfig(){ object SRC_LESS_UNSIGNED extends Stageable(Bool) - object DISRUPT_IN_MEMORY_STAGE extends Stageable(Bool) - object DISRUPT_IN_WRITEBACK_STAGE extends Stageable(Bool) + object HAS_SIDE_EFFECT extends Stageable(Bool) //Formal verification purposes object FORMAL_HALT extends Stageable(Bool) diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index 7b2bdd9..07f22fb 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -104,17 +104,17 @@ object VexRiscvSynthesisBench { // val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) -// val rtls = List(smallAndProductive, full) +// val rtls = List(smallestNoCsr) - val targets =/* XilinxStdTargets( + val targets = XilinxStdTargets( vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" ) ++ AlteraStdTargets( quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" - ) ++ */IcestormStdTargets().take(1) + ) ++ IcestormStdTargets().take(1) // val targets = IcestormStdTargets() - Bench(rtls, targets, "/home/spinalvm/tmp/") + Bench(rtls, targets, "/eda/tmp/") } } diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index 55e69ad..50df75a 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -90,14 +90,16 @@ class BranchPlugin(earlyBranch : Boolean, SRC2_CTRL -> Src2CtrlEnum.RS, SRC_USE_SUB_LESS -> True, RS1_USE -> True, - RS2_USE -> True + RS2_USE -> True, + HAS_SIDE_EFFECT -> True ) val jActions = List[(Stageable[_ <: BaseType],Any)]( SRC1_CTRL -> Src1CtrlEnum.PC_INCREMENT, SRC2_CTRL -> Src2CtrlEnum.PC, SRC_USE_SUB_LESS -> False, - REGFILE_WRITE_VALID -> True + REGFILE_WRITE_VALID -> True, + HAS_SIDE_EFFECT -> True ) import IntAluPlugin._ diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 43f6754..e047a20 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -277,7 +277,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio REGFILE_WRITE_VALID -> True, ALU_BITWISE_CTRL -> AluBitwiseCtrlEnum.SRC1, ALU_CTRL -> AluCtrlEnum.BITWISE - ) + ) ++ (if(catchIllegalAccess) List(HAS_SIDE_EFFECT -> True) else Nil) val nonImmediatActions = defaultCsrActions ++ List( SRC1_CTRL -> Src1CtrlEnum.RS, @@ -299,11 +299,11 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio CSRRWI -> immediatActions, CSRRSI -> immediatActions, CSRRCI -> immediatActions, - MRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.XRET)), - SRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.XRET)) + MRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.XRET, HAS_SIDE_EFFECT -> True)), + SRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.XRET, HAS_SIDE_EFFECT -> True)) )) if(wfiGen) decoderService.add(WFI, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.WFI)) - if(ecallGen) decoderService.add(ECALL, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.ECALL)) + if(ecallGen) decoderService.add(ECALL, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.ECALL, HAS_SIDE_EFFECT -> True)) val pcManagerService = pipeline.service(classOf[JumpService]) jumpInterface = pcManagerService.createJumpInterface(pipeline.writeBack) @@ -322,7 +322,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio privilege = RegInit(U"11").setName("CsrPlugin_privilege") if(catchIllegalAccess || ecallGen) - selfException = newExceptionPort(pipeline.writeBack) + selfException = newExceptionPort(pipeline.execute) allowInterrupts = True allowException = True @@ -555,31 +555,31 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio exceptionValids := exceptionValidsRegs for(portInfo <- sortedByStage; port = portInfo.port ; stage = portInfo.stage; stageId = indexOf(portInfo.stage)) { when(port.valid) { -// if(indexOf(stage) != 0) stages(indexOf(stage) - 1).arbitration.flushAll := True + if(indexOf(stage) != 0) stages(indexOf(stage) - 1).arbitration.flushAll := True stage.arbitration.removeIt := True exceptionValids(stageId) := True - when(!exceptionValidsRegs.takeRight(stages.length-stageId-1).fold(False)(_ || _)) { - exceptionContext := port.payload - } + exceptionContext := port.payload } } for(stageId <- firstStageIndexWithExceptionPort until stages.length; stage = stages(stageId) ){ - when(stage.arbitration.isFlushed){ - exceptionValids(stageId) := False - } val previousStage = if(stageId == firstStageIndexWithExceptionPort) stage else stages(stageId-1) when(!stage.arbitration.isStuck){ exceptionValidsRegs(stageId) := (if(stageId != firstStageIndexWithExceptionPort) exceptionValids(stageId-1) && !previousStage.arbitration.isStuck else False) }otherwise{ - exceptionValidsRegs(stageId) := exceptionValids(stageId) + if(stage != stages.last) + exceptionValidsRegs(stageId) := exceptionValids(stageId) + else + exceptionValidsRegs(stageId) := False } + if(stage != stages.last) when(stage.arbitration.isFlushed){ + exceptionValids(stageId) := False + } + } - if(stageId != 0){ - when(exceptionValidsRegs(stageId)){ - stages(stageId-1).arbitration.haltByOther := True - } - } + when(exceptionValids.orR){ + fetcher.haltIt() + fetcher.flushIt() } } else null @@ -627,8 +627,6 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio interruptJump := interrupt && pipelineLiberator.done val hadException = RegNext(exception) init(False) - exception clearWhen(hadException) - writeBack.arbitration.haltItself setWhen(exception) val targetPrivilege = CombInit(interruptTargetPrivilege) @@ -641,11 +639,21 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio trapCause := exceptionPortCtrl.exceptionContext.code } + when(exception || interruptJump){ + switch(privilege){ + if(supervisorGen) is(1) { + sepc := mepcCaptureStage.input(PC) + } + is(3){ + mepc := mepcCaptureStage.input(PC) + } + } + } + when(hadException || (interruptJump && !exception)){ jumpInterface.valid := True jumpInterface.payload := mtvec memory.arbitration.flushAll := True - if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionValidsRegs.last := False switch(targetPrivilege){ if(supervisorGen) is(1) { @@ -654,7 +662,6 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio sstatus.SPP := privilege(0 downto 0) scause.interrupt := !hadException scause.exceptionCode := trapCause - sepc := mepcCaptureStage.input(PC) if (exceptionPortCtrl != null) { stval := exceptionPortCtrl.exceptionContext.badAddr } @@ -666,13 +673,36 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio mstatus.MPP := privilege mcause.interrupt := !hadException mcause.exceptionCode := trapCause - mepc := mepcCaptureStage.input(PC) if(exceptionPortCtrl != null) { mtval := exceptionPortCtrl.exceptionContext.badAddr } } } + } + writeBack plug new Area{ + import writeBack._ + def previousStage = memory + //Manage MRET / SRET instructions + when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.XRET) { + jumpInterface.payload := mepc + jumpInterface.valid := True + previousStage.arbitration.flushAll := True + switch(input(INSTRUCTION)(29 downto 28)){ + is(3){ + mstatus.MIE := mstatus.MPIE + mstatus.MPP := U"00" + mstatus.MPIE := True + privilege := mstatus.MPP + } + if(supervisorGen) is(1){ + sstatus.SIE := sstatus.SPIE + sstatus.SPP := U"0" + sstatus.SPIE := True + privilege := U"0" @@ sstatus.SPP + } + } + } } @@ -701,12 +731,11 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } } -// writeBack plug new Area { -// import writeBack._ -// def previousStage = memory + execute plug new Area { import execute._ def previousStage = decode + val blockedBySideEffects = List(memory, writeBack).map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR val illegalAccess = arbitration.isValid && input(IS_CSR) val illegalInstruction = False @@ -718,29 +747,13 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio //Manage MRET / SRET instructions when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.XRET) { - jumpInterface.payload := mepc + //TODO check MPP value too when(input(INSTRUCTION)(29 downto 28).asUInt =/= privilege) { illegalInstruction := True - } otherwise{ - jumpInterface.valid := True - previousStage.arbitration.flushAll := True - switch(input(INSTRUCTION)(29 downto 28)){ - is(3){ - mstatus.MIE := mstatus.MPIE - mstatus.MPP := U"00" - mstatus.MPIE := True - privilege := mstatus.MPP //TODO check MPP value - } - if(supervisorGen) is(1){ - sstatus.SIE := sstatus.SPIE - sstatus.SPP := U"0" - sstatus.SPIE := True - privilege := U"0" @@ sstatus.SPP - } - } } } + //Manage ECALL instructions if(ecallGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.ECALL){ selfException.valid := True @@ -762,11 +775,12 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) // arbitration.haltItself setWhen(writeInstruction && !readDataRegValid) - val writeEnable = writeInstruction// && readDataRegValid - val readEnable = readInstruction// && !readDataRegValid + val writeEnable = writeInstruction && ! arbitration.isStuck// && readDataRegValid + val readEnable = readInstruction && ! arbitration.isStuck// && !readDataRegValid when(arbitration.isValid && input(IS_CSR)) { output(REGFILE_WRITE_DATA) := readData + arbitration.haltItself setWhen(blockedBySideEffects) } //Translation of the csrMapping into real logic diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index 02f47eb..752552a 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -53,7 +53,7 @@ class DBusCachedPlugin(config : DataCacheConfig, BYPASSABLE_MEMORY_STAGE -> False, MEMORY_WR -> False, MEMORY_MANAGMENT -> False - ) + ) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil) val storeActions = stdActions ++ List( SRC2_CTRL -> Src2CtrlEnum.IMS, diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 102bbe9..f86fcc6 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -211,7 +211,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFaul REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection) - ) + ) ++ (if(catchAccessFault || catchAddressMisaligned) List(HAS_SIDE_EFFECT -> True) else Nil) val storeActions = stdActions ++ List( SRC2_CTRL -> Src2CtrlEnum.IMS, diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala index 70aef22..7d28b24 100644 --- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala @@ -197,11 +197,11 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : decode.insert(DO_EBREAK) := !haltIt && (decode.input(IS_EBREAK) || hardwareBreakpoints.map(hb => hb.valid && hb.pc === (execute.input(PC) >> 1)).foldLeft(False)(_ || _)) when(execute.arbitration.isValid && execute.input(DO_EBREAK)){ - iBusFetcher.flushIt() - iBusFetcher.haltIt() execute.arbitration.haltByOther := True busReadDataReg := execute.input(PC).asBits when(List(memory, writeBack).map(_.arbitration.isValid).orR === False){ + iBusFetcher.flushIt() + iBusFetcher.haltIt() execute.arbitration.flushAll := True haltIt := True haltedByBreak := True diff --git a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala index cb013b8..b18ae8e 100644 --- a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala @@ -4,7 +4,6 @@ import vexriscv._ import spinal.core._ import spinal.lib._ - class HazardSimplePlugin(bypassExecute : Boolean = false, bypassMemory: Boolean = false, bypassWriteBack: Boolean = false, @@ -13,6 +12,14 @@ class HazardSimplePlugin(bypassExecute : Boolean = false, pessimisticWriteRegFile : Boolean = false, pessimisticAddressMatch : Boolean = false) extends Plugin[VexRiscv] { import Riscv._ + + + override def setup(pipeline: VexRiscv): Unit = { + import pipeline.config._ + val decoderService = pipeline.service(classOf[DecoderService]) + decoderService.addDefault(HAS_SIDE_EFFECT, False) //TODO implement it in each plugin + } + override def build(pipeline: VexRiscv): Unit = { import pipeline._ import pipeline.config._ From 0ada869b2d5d623423fa7cb809d3b3fc1a35b87e Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 1 Oct 2018 16:14:21 +0200 Subject: [PATCH 20/56] regression golden ref regfile is now sync with trl boot's random values wip --- src/main/scala/vexriscv/demo/GenFull.scala | 2 +- src/main/scala/vexriscv/demo/GenFullNoMmu.scala | 2 +- .../scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala | 2 +- .../scala/vexriscv/demo/GenFullNoMmuNoCache.scala | 2 +- .../vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala | 2 +- .../vexriscv/demo/GenSmallAndPerformant.scala | 2 +- .../demo/GenSmallAndPerformantICache.scala | 2 +- src/main/scala/vexriscv/demo/GenSmallest.scala | 2 +- .../scala/vexriscv/demo/GenSmallestNoCsr.scala | 2 +- src/main/scala/vexriscv/demo/SynthesisBench.scala | 14 ++++++++++---- .../scala/vexriscv/demo/VexRiscvAvalonForSim.scala | 2 +- .../demo/VexRiscvAvalonWithIntegratedJtag.scala | 2 +- .../demo/VexRiscvCachedWishboneForSim.scala | 2 +- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 2 +- .../scala/vexriscv/plugin/DBusSimplePlugin.scala | 2 +- src/test/cpp/regression/main.cpp | 5 +++++ 16 files changed, 29 insertions(+), 18 deletions(-) diff --git a/src/main/scala/vexriscv/demo/GenFull.scala b/src/main/scala/vexriscv/demo/GenFull.scala index 36b0b4d..5f45df2 100644 --- a/src/main/scala/vexriscv/demo/GenFull.scala +++ b/src/main/scala/vexriscv/demo/GenFull.scala @@ -63,7 +63,7 @@ object GenFull extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmu.scala b/src/main/scala/vexriscv/demo/GenFullNoMmu.scala index 62c8e58..e1aa722 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmu.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmu.scala @@ -55,7 +55,7 @@ object GenFullNoMmu extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala b/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala index 7a4d2b0..e675aa0 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala @@ -56,7 +56,7 @@ object GenFullNoMmuMaxPerf extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala index 24cb45c..b110a9d 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala @@ -28,7 +28,7 @@ object GenFullNoMmuNoCache extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala index c63efe6..32bf99f 100644 --- a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala +++ b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala @@ -33,7 +33,7 @@ object GenNoCacheNoMmuMaxPerf extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala index d5a2f77..f38ca85 100644 --- a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala @@ -28,7 +28,7 @@ object GenSmallAndProductive extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala b/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala index b6eb53f..29d179d 100644 --- a/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala @@ -42,7 +42,7 @@ object GenSmallAndProductiveICache extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallest.scala b/src/main/scala/vexriscv/demo/GenSmallest.scala index bd5b78f..1626ddb 100644 --- a/src/main/scala/vexriscv/demo/GenSmallest.scala +++ b/src/main/scala/vexriscv/demo/GenSmallest.scala @@ -28,7 +28,7 @@ object GenSmallest extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala index f8f571e..a1e9455 100644 --- a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala +++ b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala @@ -33,7 +33,7 @@ object GenSmallestNoCsr extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true, + zeroBoot = false, writeRfInMemoryStage = false ), new IntAluPlugin, diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index 07f22fb..31a929c 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -101,8 +101,8 @@ object VexRiscvSynthesisBench { } -// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) - val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) + val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) +// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallestNoCsr) @@ -113,8 +113,14 @@ object VexRiscvSynthesisBench { quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" ) ++ IcestormStdTargets().take(1) -// val targets = IcestormStdTargets() - Bench(rtls, targets, "/eda/tmp/") +// val targets = AlteraStdTargets( +// quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", +// quartusCycloneVPath = null +// ) + + + // val targets = IcestormStdTargets() + Bench(rtls, targets, "/eda/tmp") } } diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala index fb872aa..e1adf95 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala @@ -82,7 +82,7 @@ object VexRiscvAvalonForSim{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala index ebaabba..6ec2fd9 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala @@ -80,7 +80,7 @@ object VexRiscvAvalonWithIntegratedJtag{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala index 20254b6..ebf5e82 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala @@ -79,7 +79,7 @@ object VexRiscvCachedWishboneForSim{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index e047a20..afa9b24 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -735,7 +735,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio execute plug new Area { import execute._ def previousStage = decode - val blockedBySideEffects = List(memory, writeBack).map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR + val blockedBySideEffects = List(memory, writeBack).map(s => s.arbitration.isValid).orR // && s.input(HAS_SIDE_EFFECT) to improve be less pessimistic val illegalAccess = arbitration.isValid && input(IS_CSR) val illegalInstruction = False diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index f86fcc6..9ef683b 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -182,7 +182,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ } -class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{ +class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, earlyInjection : Boolean = false/*, idempotentRegions : (UInt) => Bool = (x) => False*/) extends Plugin[VexRiscv]{ var dBus : DBusSimpleBus = null diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 40478de..721c588 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -718,6 +718,11 @@ public: logTraces.open (name + ".logTrace"); fillSimELements(); clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &start_time); + + //Sync register file initial content + for(int i = 1;i < 32;i++){ + riscvRef.regs[i] = top->VexRiscv->RegFilePlugin_regFile[i]; + } } virtual ~Workspace(){ From c61f17aea370816851239a51e9622ef6a5a1bcf3 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 3 Oct 2018 01:02:22 +0200 Subject: [PATCH 21/56] Fetcher/IBusSimplePlugin wip --- src/main/scala/vexriscv/plugin/Fetcher.scala | 30 ++++++---- .../vexriscv/plugin/IBusSimplePlugin.scala | 56 ++++++------------- src/test/cpp/regression/main.cpp | 9 ++- 3 files changed, 42 insertions(+), 53 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 986502e..8e9fbdc 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -114,10 +114,22 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, //PC calculation without Jump val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public) val inc = RegInit(False) + val propagatePc = False val pc = pcReg + (inc ## B"00").asUInt val samplePcNext = False + if(compressedGen) { + when(inc) { + pc(1) := False + } + } + + when(propagatePc){ + samplePcNext := True + inc := False + } + if(predictionPcLoad != null) { when(predictionPcLoad.valid) { inc := False @@ -142,14 +154,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, pcReg := pc } - if(compressedGen) { - when(preOutput.fire) { - pcReg(1 downto 0) := 0 - when(pc(1)){ - inc := True - } - } - } preOutput.valid := RegNext(True) init (False) preOutput.payload := pc @@ -217,7 +221,13 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, } for((s,sNext) <- (stages, stages.tail).zipped) { - sNext.input << s.output.m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false) + if(s == stages.head) { + sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false)) + sNext.input.payload := fetchPc.pcReg + fetchPc.propagatePc setWhen(sNext.input.fire) + } else { + sNext.input << s.output.m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false) + } } // @@ -310,7 +320,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, }).tail } - val nextPcCalc = if (decodePcGen) { + val nextPcCalc = if (decodePcGen) new Area{ val valids = pcUpdatedGen(True, False :: List(execute, memory, writeBack).map(_.arbitration.isStuck), true) pcValids := Vec(valids.takeRight(4)) } else new Area{ diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 6e415c0..e63ec98 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -151,8 +151,7 @@ class IBusSimplePlugin(resetVector : BigInt, compressedGen : Boolean = false, busLatencyMin : Int = 1, pendingMax : Int = 7, - injectorStage : Boolean = true, - relaxedBusCmdValid : Boolean = false + injectorStage : Boolean = true ) extends IBusFetcherImpl( catchAccessFault = catchAccessFault, resetVector = resetVector, @@ -164,8 +163,6 @@ class IBusSimplePlugin(resetVector : BigInt, prediction = prediction, historyRamSizeLog2 = historyRamSizeLog2, injectorStage = injectorStage){ - assert(!(prediction == DYNAMIC_TARGET && relaxedBusCmdValid), "IBusSimplePlugin doesn't allow dynamic_target prediction and relaxedBusCmdValid together") - assert(!relaxedBusCmdValid) var iBus : IBusSimpleBus = null var decodeExceptionPort : Flow[ExceptionCause] = null @@ -185,44 +182,23 @@ class IBusSimplePlugin(resetVector : BigInt, import pipeline.config._ pipeline plug new FetchArea(pipeline) { - - - //Avoid sending to many iBus cmd val pendingCmd = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0) val pendingCmdNext = pendingCmd + iBus.cmd.fire.asUInt - iBus.rsp.fire.asUInt pendingCmd := pendingCmdNext - val cmd = if(relaxedBusCmdValid) new Area { - ??? - /* def inputStage = iBusRsp.stages(0) - val busFork = Stream(UInt(32 bits)) - val busForkedReg = RegInit(False) - if(!relaxedPcCalculation) busForkedReg clearWhen(flush) - busForkedReg setWhen(iBus.cmd.fire) - busForkedReg clearWhen(inputStage.output.ready) - if(relaxedPcCalculation) busForkedReg clearWhen(flush) - val busForked = Bool - busForked := (if(!relaxedPcCalculation) (busForkedReg && !flush) else (busForkedReg)) - - - busFork.valid := inputStage.input.valid && !busForkedReg - busFork.payload := inputStage.input.payload - - inputStage.halt setWhen() - output.valid := (inputStage.input.valid && iBus.cmd.fire) || busForked - output.payload := input.payload - input.ready := output.fire - - - val okBus = pendingCmd =/= pendingMax - iBus.cmd.valid := busFork.valid && okBus - iBus.cmd.pc := busFork.payload(31 downto 2) @@ "00" - busFork.ready := iBus.cmd.ready && okBus*/ - } else new Area { + val cmd = /*if(relaxedPcCalculation) new Area { + //This implementation keep the iBus.cmd on the bus until it's executed, even if the pipeline is flushed + def stage = iBusRsp.stages(1) + stage.halt setWhen(iBus.cmd.isStall) + val cmdKeep = RegInit(False) setWhen(iBus.cmd.valid) clearWhen(iBus.cmd.ready) + val cmdFired = RegInit(False) setWhen(iBus.cmd.fire) clearWhen(stage.input.ready) + iBus.cmd.valid := (stage.input.valid || cmdKeep) && pendingCmd =/= pendingMax && !cmdFired + iBus.cmd.pc := stage.input.payload(31 downto 2) @@ "00" + } else */new Area { + //This implementation keep the iBus.cmd on the bus until it's executed or the the pipeline is flushed (not "safe") def stage = iBusRsp.stages(if(relaxedPcCalculation) 1 else 0) stage.halt setWhen(stage.input.valid && (!iBus.cmd.valid || !iBus.cmd.ready)) - iBus.cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax iBus.cmd.pc := stage.input.payload(31 downto 2) @@ "00" } @@ -235,10 +211,11 @@ class IBusSimplePlugin(resetVector : BigInt, val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0) discardCounter := discardCounter - (iBus.rsp.fire && discardCounter =/= 0).asUInt when(flush) { +// discardCounter := (if(relaxedPcCalculation) pendingCmd + iBus.cmd.valid.asUInt - iBus.rsp.fire.asUInt else pendingCmd - iBus.rsp.fire.asUInt) discardCounter := (if(relaxedPcCalculation) pendingCmdNext else pendingCmd - iBus.rsp.fire.asUInt) } - val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), cmdToRspStageCount - (if(relaxedPcCalculation) 0 else 0)) + val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin) rspBuffer.io.push << iBus.rsp.throwWhen(discardCounter =/= 0).toStream rspBuffer.io.flush := flush @@ -249,8 +226,11 @@ class IBusSimplePlugin(resetVector : BigInt, var issueDetected = False - val join = StreamJoin(Seq(stages.last.output, rspBuffer.io.pop), fetchRsp) - stages.last.output.ready setWhen(!stages.last.output.valid) + val join = Stream(FetchRsp()) + join.valid := stages.last.output.valid && rspBuffer.io.pop.valid + join.payload := fetchRsp + stages.last.output.ready := stages.last.output.valid ? join.fire | join.ready + rspBuffer.io.pop.ready := join.fire output << join.haltWhen(issueDetected) if(catchAccessFault){ diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 721c588..012680c 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -718,11 +718,6 @@ public: logTraces.open (name + ".logTrace"); fillSimELements(); clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &start_time); - - //Sync register file initial content - for(int i = 1;i < 32;i++){ - riscvRef.regs[i] = top->VexRiscv->RegFilePlugin_regFile[i]; - } } virtual ~Workspace(){ @@ -921,6 +916,10 @@ public: postReset(); + //Sync register file initial content + for(int i = 1;i < 32;i++){ + riscvRef.regs[i] = top->VexRiscv->RegFilePlugin_regFile[i]; + } resetDone = true; #ifdef REF From 48bff80653184919a56ba7db6876096ae92c79a6 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 3 Oct 2018 16:24:10 +0200 Subject: [PATCH 22/56] rework fetchPc to optionaly share the pcReg with the stage(1) IBusSimplePlugin now implement cmdForkPersistence option --- README.md | 25 +++----- src/main/scala/vexriscv/TestsWorkspace.scala | 62 +++++++++---------- .../scala/vexriscv/demo/FormalSimple.scala | 2 +- .../scala/vexriscv/demo/GenCustomCsr.scala | 2 +- .../vexriscv/demo/GenCustomSimdAdd.scala | 2 +- .../vexriscv/demo/GenDeterministicVex.scala | 2 +- .../vexriscv/demo/GenFullNoMmuNoCache.scala | 2 +- .../demo/GenNoCacheNoMmuMaxPerf.scala | 2 +- .../vexriscv/demo/GenSmallAndPerformant.scala | 2 +- .../scala/vexriscv/demo/GenSmallest.scala | 2 +- .../vexriscv/demo/GenSmallestNoCsr.scala | 2 +- src/main/scala/vexriscv/demo/Murax.scala | 7 ++- .../scala/vexriscv/demo/SynthesisBench.scala | 2 +- .../vexriscv/demo/VexRiscvAvalonForSim.scala | 2 +- .../scala/vexriscv/plugin/CsrPlugin.scala | 1 + src/main/scala/vexriscv/plugin/Fetcher.scala | 3 +- .../vexriscv/plugin/IBusCachedPlugin.scala | 1 + .../vexriscv/plugin/IBusSimplePlugin.scala | 50 ++++++++------- .../vexriscv/TestIndividualFeatures.scala | 17 ++--- 19 files changed, 95 insertions(+), 93 deletions(-) diff --git a/README.md b/README.md index c4196b1..a5f64d8 100644 --- a/README.md +++ b/README.md @@ -422,7 +422,8 @@ val cpu = new VexRiscv( plugins = List( new IBusSimplePlugin( resetVector = 0x00000000l, - relaxedPcCalculation = true + cmdForkOnSecondStage = true, + cmdForkPersistence = true ), new DBusSimplePlugin( catchAddressMisaligned = false, @@ -643,19 +644,6 @@ This chapter describes plugins currently implemented. - [DebugPlugin](#debugplugin) - [YamlPlugin](#yamlplugin) -#### PcManagerSimplePlugin - -This plugin implements the program counter and a jump service to all plugins. - - -| Parameters | type | description | -| ------ | ----------- | ------ | -| resetVector | BigInt | Address of the program counter after the reset | -| relaxedPcCalculation | Boolean | By default jump have an asynchronous immediate effect on the program counter, which allow to reduce the branch penalties by one cycle but could reduce the FMax as it will combinatorialy drive the instruction bus address signal. To avoid this you can set this parameter to true, which will make the jump affecting the programm counter in a sequancial way, which will cut the combinatorial path but add one additional cycle of penalty when a jump occur. | - - - -This plugin operates on the prefetch stage. #### IBusSimplePlugin @@ -665,8 +653,8 @@ This plugin implement the CPU frontend (instruction fetch) via a very simple and | ------ | ----------- | ------ | | catchAccessFault | Boolean | If an the read response specify an read error and this parameter is true, it will generate an CPU exception trap | | resetVector | BigInt | Address of the program counter after the reset | -| relaxedPcCalculation | Boolean | By default jump have an asynchronous immediate effect on the program counter, which allow to reduce the branch penalties by one cycle but could reduce the FMax as it will combinatorialy drive the instruction bus address signal. To avoid this you can set this parameter to true, which will make the jump affecting the programm counter in a sequancial way, which will cut the combinatorial path but add one additional cycle of penalty when a jump occur. | -| relaxedBusCmdValid | Boolean | Same than relaxedPcCalculation, but for the iBus.cmd.valid pin. | +| cmdForkOnSecondStage | Boolean | By default jump have an asynchronous immediate effect on the program counter, which allow to reduce the branch penalties by one cycle but could reduce the FMax as it will combinatorialy drive the instruction bus address signal. To avoid this you can set this parameter to true, which will make the jump affecting the programm counter in a sequancial way, which will cut the combinatorial path but add one additional cycle of penalty when a jump occur. | +| cmdForkPersistence | Boolean | If this parameter is false, then request on the iBus can disappear/change before their completion. Which reduce area but isn't safe/supported by many arbitration/slaves. If you set this parameter to true, then the iBus cmd will stay until they are completed. | compressedGen | Boolean | Enable RVC support | | busLatencyMin | Int | Specify the minimal latency between the iBus.cmd and iBus.rsp, which will add the corresponding number of stages into the frontend to keep the IPC to 1.| | injectorStage | Boolean | Add a stage between the frontend and the decode stage of the CPU to improve FMax. (busLatencyMin + injectorStage) should be at least two. | @@ -700,8 +688,9 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste } ``` -**Important** : There should be at least one cycle latency between que cmd and the rsp. The IBus.cmd can remove request when a CPU jump occure or when the CPU is halted by someting in the pipeline. As many arbitration aren't made for this behaviour, it is important to add a buffer to the iBus.cmd to avoid this. Ex : iBus.cmd.s2mPipe, which add a zero latency buffer and cut the iBus.cmd.ready path. -You can also do iBus.cmd.s2mPipe.m2sPipe, which will cut all combinatorial path of the bus but then as a latency of 1 cycle. which mean you should probably set the busLatencyMin to 2. +**Important** : Checkout the cmdForkPersistence parameter, because if it's not set, it can break the iBus compatibility with your memory system (unless you externaly add some buffers) + +Setting cmdForkPersistence and cmdForkOnSecondStage improves iBus cmd timings. Note that bridges are implemented to convert this interface into AXI4 and Avalon diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index ac19f96..f6839d9 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -31,40 +31,40 @@ object TestsWorkspace { SpinalConfig(mergeAsyncProcess = false, anonymSignalPrefix = "zz_").generateVerilog { val configFull = VexRiscvConfig( plugins = List( -// new IBusSimplePlugin( -// resetVector = 0x80000000l, -// relaxedPcCalculation = false, -// relaxedBusCmdValid = false, -// prediction = NONE, -// historyRamSizeLog2 = 10, -// catchAccessFault = true, -// compressedGen = true, -// busLatencyMin = 1, -// injectorStage = true -// ), - new IBusCachedPlugin( + new IBusSimplePlugin( resetVector = 0x80000000l, - compressedGen = false, + cmdForkOnSecondStage = true, + cmdForkPersistence = true, prediction = NONE, - injectorStage = true, - config = InstructionCacheConfig( - cacheSize = 4096, - bytePerLine = 32, - wayCount = 1, - addressWidth = 32, - cpuDataWidth = 32, - memDataWidth = 32, - catchIllegalAccess = true, - catchAccessFault = true, - catchMemoryTranslationMiss = true, - asyncTagMemory = false, - twoCycleRam = false, - twoCycleCache = true - ), - memoryTranslatorPortConfig = MemoryTranslatorPortConfig( - portTlbSize = 4 - ) + historyRamSizeLog2 = 10, + catchAccessFault = true, + compressedGen = false, + busLatencyMin = 1, + injectorStage = true ), +// new IBusCachedPlugin( +// resetVector = 0x80000000l, +// compressedGen = false, +// prediction = NONE, +// injectorStage = true, +// config = InstructionCacheConfig( +// cacheSize = 4096, +// bytePerLine = 32, +// wayCount = 1, +// addressWidth = 32, +// cpuDataWidth = 32, +// memDataWidth = 32, +// catchIllegalAccess = true, +// catchAccessFault = true, +// catchMemoryTranslationMiss = true, +// asyncTagMemory = false, +// twoCycleRam = false, +// twoCycleCache = true +// ), +// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( +// portTlbSize = 4 +// ) +// ), // new DBusSimplePlugin( // catchAddressMisaligned = true, // catchAccessFault = true, diff --git a/src/main/scala/vexriscv/demo/FormalSimple.scala b/src/main/scala/vexriscv/demo/FormalSimple.scala index e540b20..7c6aa4f 100644 --- a/src/main/scala/vexriscv/demo/FormalSimple.scala +++ b/src/main/scala/vexriscv/demo/FormalSimple.scala @@ -15,7 +15,7 @@ object FormalSimple extends App{ new HaltOnExceptionPlugin, new IBusSimplePlugin( resetVector = 0x00000000l, - relaxedPcCalculation = false, + cmdForkOnSecondStage = false, prediction = DYNAMIC_TARGET, catchAccessFault = false, compressedGen = true diff --git a/src/main/scala/vexriscv/demo/GenCustomCsr.scala b/src/main/scala/vexriscv/demo/GenCustomCsr.scala index 5eae5d0..4ee5546 100644 --- a/src/main/scala/vexriscv/demo/GenCustomCsr.scala +++ b/src/main/scala/vexriscv/demo/GenCustomCsr.scala @@ -18,7 +18,7 @@ object GenCustomCsr extends App{ new CustomCsrDemoGpioPlugin, new IBusSimplePlugin( resetVector = 0x00000000l, - relaxedPcCalculation = false, + cmdForkOnSecondStage = false, prediction = NONE, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala index 0b4c854..3321a9d 100644 --- a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala +++ b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala @@ -14,7 +14,7 @@ object GenCustomSimdAdd extends App{ new SimdAddPlugin, new IBusSimplePlugin( resetVector = 0x00000000l, - relaxedPcCalculation = false, + cmdForkOnSecondStage = false, prediction = NONE, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenDeterministicVex.scala b/src/main/scala/vexriscv/demo/GenDeterministicVex.scala index b4b5745..6e3ec39 100644 --- a/src/main/scala/vexriscv/demo/GenDeterministicVex.scala +++ b/src/main/scala/vexriscv/demo/GenDeterministicVex.scala @@ -13,7 +13,7 @@ object GenDeterministicVex extends App{ plugins = List( new IBusSimplePlugin( resetVector = 0x80000000l, - relaxedPcCalculation = false, + cmdForkOnSecondStage = false, prediction = STATIC, catchAccessFault = true, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala index b110a9d..a69c024 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala @@ -14,7 +14,7 @@ object GenFullNoMmuNoCache extends App{ plugins = List( new IBusSimplePlugin( resetVector = 0x80000000l, - relaxedPcCalculation = false, + cmdForkOnSecondStage = false, prediction = STATIC, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala index 32bf99f..0def2a8 100644 --- a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala +++ b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala @@ -14,7 +14,7 @@ object GenNoCacheNoMmuMaxPerf extends App{ plugins = List( new IBusSimplePlugin( resetVector = 0x80000000l, - relaxedPcCalculation = false, + cmdForkOnSecondStage = false, prediction = DYNAMIC_TARGET, historyRamSizeLog2 = 8, catchAccessFault = true, diff --git a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala index f38ca85..f0d7c6d 100644 --- a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala @@ -13,7 +13,7 @@ object GenSmallAndProductive extends App{ plugins = List( new IBusSimplePlugin( resetVector = 0x80000000l, - relaxedPcCalculation = false, + cmdForkOnSecondStage = false, prediction = NONE, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenSmallest.scala b/src/main/scala/vexriscv/demo/GenSmallest.scala index 1626ddb..e4131d0 100644 --- a/src/main/scala/vexriscv/demo/GenSmallest.scala +++ b/src/main/scala/vexriscv/demo/GenSmallest.scala @@ -13,7 +13,7 @@ object GenSmallest extends App{ plugins = List( new IBusSimplePlugin( resetVector = 0x80000000l, - relaxedPcCalculation = false, + cmdForkOnSecondStage = false, prediction = NONE, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala index a1e9455..f5acf98 100644 --- a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala +++ b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala @@ -18,7 +18,7 @@ object GenSmallestNoCsr extends App{ new IBusSimplePlugin( resetVector = 0x80000000l, - relaxedPcCalculation = false, + cmdForkOnSecondStage = false, prediction = NONE, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 81db2ce..8bbd57a 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -69,7 +69,8 @@ object MuraxConfig{ cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel new IBusSimplePlugin( resetVector = if(withXip) 0xF001E000l else 0x80000000l, - relaxedPcCalculation = true, + cmdForkOnSecondStage = true, + cmdForkPersistence = withXip, //Required by the Xip controller prediction = NONE, catchAccessFault = false, compressedGen = false @@ -227,7 +228,7 @@ case class Murax(config : MuraxConfig) extends Component{ val externalInterrupt = False for(plugin <- cpu.plugins) plugin match{ case plugin : IBusSimplePlugin => - mainBusArbiter.io.iBus.cmd <> plugin.iBus.cmd.halfPipe() //TODO !! + mainBusArbiter.io.iBus.cmd <> plugin.iBus.cmd mainBusArbiter.io.iBus.rsp <> plugin.iBus.rsp case plugin : DBusSimplePlugin => { if(!pipelineDBus) @@ -496,7 +497,7 @@ object MuraxDhrystoneReadyMulDivStatic{ ) config.cpuPlugins += new IBusSimplePlugin( resetVector = 0x80000000l, - relaxedPcCalculation = true, + cmdForkOnSecondStage = true, prediction = STATIC, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index 31a929c..695fd56 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -179,7 +179,7 @@ object MuraxSynthesisBench { val rtls = List(murax, muraxFast) - val targets = IcestormStdTargets() ++ XilinxStdTargets( + val targets = IcestormStdTargets().take(1) ++ XilinxStdTargets( vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" ) ++ AlteraStdTargets( quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/", diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala index e1adf95..0aacae6 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala @@ -28,7 +28,7 @@ object VexRiscvAvalonForSim{ plugins = List( new IBusSimplePlugin( resetVector = 0x00000000l, - relaxedPcCalculation = false, + cmdForkOnSecondStage = false, prediction = STATIC, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index afa9b24..dc306e3 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -731,6 +731,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } } + decode.arbitration.haltByOther setWhen(List(execute,memory).map(s => s.arbitration.isValid && s.input(ENV_CTRL) === EnvCtrlEnum.XRET).orR) execute plug new Area { import execute._ diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 8e9fbdc..572270b 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -17,6 +17,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, val decodePcGen : Boolean, val compressedGen : Boolean, val cmdToRspStageCount : Int, + val pcRegReusedForSecondStage : Boolean, val injectorReadyCutGen : Boolean, val prediction : BranchPrediction, val historyRamSizeLog2 : Int, @@ -221,7 +222,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, } for((s,sNext) <- (stages, stages.tail).zipped) { - if(s == stages.head) { + if(s == stages.head && pcRegReusedForSecondStage) { sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false)) sNext.input.payload := fetchPc.pcReg fetchPc.propagatePc setWhen(sNext.input.fire) diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index 405c277..2d57d23 100644 --- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -24,6 +24,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, decodePcGen = compressedGen, compressedGen = compressedGen, cmdToRspStageCount = (if(config.twoCycleCache) 2 else 1) + (if(relaxedPcCalculation) 1 else 0), + pcRegReusedForSecondStage = true, injectorReadyCutGen = false, prediction = prediction, historyRamSizeLog2 = historyRamSizeLog2, diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index e63ec98..fa985cb 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -144,7 +144,8 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste class IBusSimplePlugin(resetVector : BigInt, catchAccessFault : Boolean = false, - relaxedPcCalculation : Boolean = false, + cmdForkOnSecondStage : Boolean = false, + cmdForkPersistence : Boolean = false, prediction : BranchPrediction = NONE, historyRamSizeLog2 : Int = 10, keepPcPlus4 : Boolean = false, @@ -158,7 +159,8 @@ class IBusSimplePlugin(resetVector : BigInt, keepPcPlus4 = keepPcPlus4, decodePcGen = compressedGen, compressedGen = compressedGen, - cmdToRspStageCount = busLatencyMin + (if(relaxedPcCalculation) 1 else 0), + cmdToRspStageCount = busLatencyMin + (if(cmdForkOnSecondStage) 1 else 0), + pcRegReusedForSecondStage = !(cmdForkOnSecondStage && cmdForkPersistence), injectorReadyCutGen = false, prediction = prediction, historyRamSizeLog2 = historyRamSizeLog2, @@ -182,40 +184,44 @@ class IBusSimplePlugin(resetVector : BigInt, import pipeline.config._ pipeline plug new FetchArea(pipeline) { + var cmd = Stream(IBusSimpleCmd()) + iBus.cmd << (if(cmdForkPersistence && !cmdForkOnSecondStage) cmd.s2mPipe() else cmd) + //Avoid sending to many iBus cmd val pendingCmd = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0) - val pendingCmdNext = pendingCmd + iBus.cmd.fire.asUInt - iBus.rsp.fire.asUInt + val pendingCmdNext = pendingCmd + cmd.fire.asUInt - iBus.rsp.fire.asUInt pendingCmd := pendingCmdNext - val cmd = /*if(relaxedPcCalculation) new Area { - //This implementation keep the iBus.cmd on the bus until it's executed, even if the pipeline is flushed + val cmdFork = if(!cmdForkPersistence || !cmdForkOnSecondStage) new Area { + //This implementation keep the cmd on the bus until it's executed or the the pipeline is flushed + def stage = iBusRsp.stages(if(cmdForkOnSecondStage) 1 else 0) + stage.halt setWhen(stage.input.valid && (!cmd.valid || !cmd.ready)) + cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax + cmd.pc := stage.input.payload(31 downto 2) @@ "00" + } else new Area{ + //This implementation keep the cmd on the bus until it's executed, even if the pipeline is flushed def stage = iBusRsp.stages(1) - stage.halt setWhen(iBus.cmd.isStall) - val cmdKeep = RegInit(False) setWhen(iBus.cmd.valid) clearWhen(iBus.cmd.ready) - val cmdFired = RegInit(False) setWhen(iBus.cmd.fire) clearWhen(stage.input.ready) - iBus.cmd.valid := (stage.input.valid || cmdKeep) && pendingCmd =/= pendingMax && !cmdFired - iBus.cmd.pc := stage.input.payload(31 downto 2) @@ "00" - } else */new Area { - //This implementation keep the iBus.cmd on the bus until it's executed or the the pipeline is flushed (not "safe") - def stage = iBusRsp.stages(if(relaxedPcCalculation) 1 else 0) - stage.halt setWhen(stage.input.valid && (!iBus.cmd.valid || !iBus.cmd.ready)) - iBus.cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax - iBus.cmd.pc := stage.input.payload(31 downto 2) @@ "00" + val pendingFull = pendingCmd === pendingMax + val cmdKeep = RegInit(False) setWhen(cmd.valid) clearWhen(cmd.ready) + val cmdFired = RegInit(False) setWhen(cmd.fire) clearWhen(stage.input.ready) + stage.halt setWhen(cmd.isStall || (pendingFull && !cmdFired)) + cmd.valid := (stage.input.valid || cmdKeep) && !pendingFull && !cmdFired + cmd.pc := stage.input.payload(31 downto 2) @@ "00" } - - - val rsp = new Area { + val rspJoin = new Area { import iBusRsp._ //Manage flush for iBus transactions in flight val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0) discardCounter := discardCounter - (iBus.rsp.fire && discardCounter =/= 0).asUInt when(flush) { -// discardCounter := (if(relaxedPcCalculation) pendingCmd + iBus.cmd.valid.asUInt - iBus.rsp.fire.asUInt else pendingCmd - iBus.rsp.fire.asUInt) - discardCounter := (if(relaxedPcCalculation) pendingCmdNext else pendingCmd - iBus.rsp.fire.asUInt) + if(cmdForkOnSecondStage && cmdForkPersistence) + discardCounter := pendingCmd + cmd.valid.asUInt - iBus.rsp.fire.asUInt + else + discardCounter := (if(cmdForkOnSecondStage) pendingCmdNext else pendingCmd - iBus.rsp.fire.asUInt) } - val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin) + val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0)) rspBuffer.io.push << iBus.rsp.throwWhen(discardCounter =/= 0).toStream rspBuffer.io.flush := flush diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala index d7eae7e..b1ce354 100644 --- a/src/test/scala/vexriscv/TestIndividualFeatures.scala +++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala @@ -266,14 +266,15 @@ class IBusDimension extends VexRiscvDimension("IBus") { val injectorStage = r.nextBoolean() || latency == 1 val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET)) val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL) - val relaxedPcCalculation = r.nextBoolean() - val relaxedBusCmdValid =false // r.nextBoolean() && relaxedPcCalculation && prediction != DYNAMIC_TARGET - new VexRiscvPosition("Simple" + latency + (if(relaxedPcCalculation) "Relax" else "") + (if(relaxedBusCmdValid) "Valid" else "") + (if(injectorStage) "InjStage" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{ + val cmdForkOnSecondStage = r.nextBoolean() + val cmdForkPersistence = r.nextBoolean() + val relaxedBusCmdValid = false // r.nextBoolean() && relaxedPcCalculation && prediction != DYNAMIC_TARGET + new VexRiscvPosition("Simple" + latency + (if(cmdForkOnSecondStage) "S2" else "") + (if(cmdForkPersistence) "P" else "") + (if(relaxedBusCmdValid) "Valid" else "") + (if(injectorStage) "InjStage" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{ override def testParam = "IBUS=SIMPLE" + (if(compressed) " COMPRESSED=yes" else "") override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin( resetVector = 0x80000000l, - relaxedPcCalculation = relaxedPcCalculation, - relaxedBusCmdValid = relaxedBusCmdValid, + cmdForkOnSecondStage = cmdForkOnSecondStage, + cmdForkPersistence = cmdForkPersistence, prediction = prediction, catchAccessFault = catchAll, compressedGen = compressed, @@ -522,8 +523,10 @@ class TestIndividualFeatures extends FunSuite { // val seed = -2412372746600605141l -// val testId = Some(mutable.HashSet[Int](1,6,11,17,23,24)) -// val seed = -7309275932954927463l +// val testId = Some(mutable.HashSet[Int](6,11,31,32,53,55,56,64,82)) +// val testId = Some(mutable.HashSet[Int](31)) +// val seed = 971825313472546699l + val rand = new Random(seed) From 0662cc279736fc499d5468f66fc689eda8df3bcd Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 3 Oct 2018 22:08:57 +0200 Subject: [PATCH 23/56] Add GenMicro experiment to reduce ice40 area usage. IBusSimplePlugin now require cmdFork parameters to be set (no default) --- src/main/scala/vexriscv/TestsWorkspace.scala | 6 +- .../scala/vexriscv/demo/FormalSimple.scala | 1 + .../scala/vexriscv/demo/GenCustomCsr.scala | 1 + .../vexriscv/demo/GenCustomSimdAdd.scala | 1 + .../vexriscv/demo/GenDeterministicVex.scala | 1 + .../vexriscv/demo/GenFullNoMmuNoCache.scala | 1 + .../demo/GenNoCacheNoMmuMaxPerf.scala | 1 + .../vexriscv/demo/GenSmallAndPerformant.scala | 1 + .../scala/vexriscv/demo/GenSmallest.scala | 1 + .../vexriscv/demo/GenSmallestNoCsr.scala | 1 + src/main/scala/vexriscv/demo/Murax.scala | 1 + .../vexriscv/demo/VexRiscvAvalonForSim.scala | 1 + .../vexriscv/plugin/DBusSimplePlugin.scala | 9 +- src/main/scala/vexriscv/plugin/Fetcher.scala | 2 +- .../plugin/HazardPessimisticPlugin.scala | 7 ++ .../vexriscv/plugin/IBusSimplePlugin.scala | 29 +++-- .../scala/vexriscv/plugin/RegFilePlugin.scala | 31 +++-- .../vexriscv/experimental/GenMicro.scala | 113 ++++++++++++++++++ .../scala/vexriscv/experimental/config.scala | 2 +- 19 files changed, 180 insertions(+), 30 deletions(-) create mode 100644 src/test/scala/vexriscv/experimental/GenMicro.scala diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index f6839d9..80836e4 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -33,14 +33,14 @@ object TestsWorkspace { plugins = List( new IBusSimplePlugin( resetVector = 0x80000000l, - cmdForkOnSecondStage = true, - cmdForkPersistence = true, + cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = NONE, historyRamSizeLog2 = 10, catchAccessFault = true, compressedGen = false, busLatencyMin = 1, - injectorStage = true + injectorStage = false ), // new IBusCachedPlugin( // resetVector = 0x80000000l, diff --git a/src/main/scala/vexriscv/demo/FormalSimple.scala b/src/main/scala/vexriscv/demo/FormalSimple.scala index 7c6aa4f..9a4167e 100644 --- a/src/main/scala/vexriscv/demo/FormalSimple.scala +++ b/src/main/scala/vexriscv/demo/FormalSimple.scala @@ -16,6 +16,7 @@ object FormalSimple extends App{ new IBusSimplePlugin( resetVector = 0x00000000l, cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = DYNAMIC_TARGET, catchAccessFault = false, compressedGen = true diff --git a/src/main/scala/vexriscv/demo/GenCustomCsr.scala b/src/main/scala/vexriscv/demo/GenCustomCsr.scala index 4ee5546..11db86d 100644 --- a/src/main/scala/vexriscv/demo/GenCustomCsr.scala +++ b/src/main/scala/vexriscv/demo/GenCustomCsr.scala @@ -19,6 +19,7 @@ object GenCustomCsr extends App{ new IBusSimplePlugin( resetVector = 0x00000000l, cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = NONE, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala index 3321a9d..8b137f5 100644 --- a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala +++ b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala @@ -15,6 +15,7 @@ object GenCustomSimdAdd extends App{ new IBusSimplePlugin( resetVector = 0x00000000l, cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = NONE, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenDeterministicVex.scala b/src/main/scala/vexriscv/demo/GenDeterministicVex.scala index 6e3ec39..943ba16 100644 --- a/src/main/scala/vexriscv/demo/GenDeterministicVex.scala +++ b/src/main/scala/vexriscv/demo/GenDeterministicVex.scala @@ -14,6 +14,7 @@ object GenDeterministicVex extends App{ new IBusSimplePlugin( resetVector = 0x80000000l, cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = STATIC, catchAccessFault = true, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala index a69c024..77ed87a 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala @@ -15,6 +15,7 @@ object GenFullNoMmuNoCache extends App{ new IBusSimplePlugin( resetVector = 0x80000000l, cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = STATIC, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala index 0def2a8..b727b37 100644 --- a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala +++ b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala @@ -15,6 +15,7 @@ object GenNoCacheNoMmuMaxPerf extends App{ new IBusSimplePlugin( resetVector = 0x80000000l, cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = DYNAMIC_TARGET, historyRamSizeLog2 = 8, catchAccessFault = true, diff --git a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala index f0d7c6d..9bd6f72 100644 --- a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala @@ -14,6 +14,7 @@ object GenSmallAndProductive extends App{ new IBusSimplePlugin( resetVector = 0x80000000l, cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = NONE, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenSmallest.scala b/src/main/scala/vexriscv/demo/GenSmallest.scala index e4131d0..9813ccf 100644 --- a/src/main/scala/vexriscv/demo/GenSmallest.scala +++ b/src/main/scala/vexriscv/demo/GenSmallest.scala @@ -14,6 +14,7 @@ object GenSmallest extends App{ new IBusSimplePlugin( resetVector = 0x80000000l, cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = NONE, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala index f5acf98..cd1ee31 100644 --- a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala +++ b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala @@ -19,6 +19,7 @@ object GenSmallestNoCsr extends App{ new IBusSimplePlugin( resetVector = 0x80000000l, cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = NONE, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 8bbd57a..63023ec 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -498,6 +498,7 @@ object MuraxDhrystoneReadyMulDivStatic{ config.cpuPlugins += new IBusSimplePlugin( resetVector = 0x80000000l, cmdForkOnSecondStage = true, + cmdForkPersistence = false, prediction = STATIC, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala index 0aacae6..304a360 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala @@ -29,6 +29,7 @@ object VexRiscvAvalonForSim{ new IBusSimplePlugin( resetVector = 0x00000000l, cmdForkOnSecondStage = false, + cmdForkPersistence = false, prediction = STATIC, catchAccessFault = false, compressedGen = false diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 9ef683b..1df4272 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -182,7 +182,10 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ } -class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, earlyInjection : Boolean = false/*, idempotentRegions : (UInt) => Bool = (x) => False*/) extends Plugin[VexRiscv]{ +class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, + catchAccessFault : Boolean = false, + earlyInjection : Boolean = false,/*, idempotentRegions : (UInt) => Bool = (x) => False*/ + onlyLoadWords : Boolean = false) extends Plugin[VexRiscv]{ var dBus : DBusSimpleBus = null @@ -220,7 +223,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFaul decoderService.addDefault(MEMORY_ENABLE, False) decoderService.add( - List(LB, LH, LW, LBU, LHU, LWU).map(_ -> loadActions) ++ + (if(onlyLoadWords) List(LW) else List(LB, LH, LW, LBU, LHU, LWU)).map(_ -> loadActions) ++ List(SB, SH, SW).map(_ -> storeActions) ) @@ -329,7 +332,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFaul ) when(arbitration.isValid && input(MEMORY_ENABLE)) { - output(REGFILE_WRITE_DATA) := rspFormated + output(REGFILE_WRITE_DATA) := (if(!onlyLoadWords) rspFormated else input(MEMORY_READ_DATA)) } if(!earlyInjection) diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 572270b..13c8742 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -28,7 +28,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, var dynamicTargetFailureCorrection : Flow[UInt] = null var externalResetVector : UInt = null assert(cmdToRspStageCount >= 1) - assert(!(cmdToRspStageCount == 1 && !injectorStage)) +// assert(!(cmdToRspStageCount == 1 && !injectorStage)) assert(!(compressedGen && !decodePcGen)) var fetcherHalt : Bool = null var fetcherflushIt : Bool = null diff --git a/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala b/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala index e65aaec..9fb11a6 100644 --- a/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala @@ -7,6 +7,13 @@ import spinal.lib._ class HazardPessimisticPlugin() extends Plugin[VexRiscv] { import Riscv._ + + override def setup(pipeline: VexRiscv): Unit = { + import pipeline.config._ + val decoderService = pipeline.service(classOf[DecoderService]) + decoderService.addDefault(HAS_SIDE_EFFECT, False) + } + override def build(pipeline: VexRiscv): Unit = { import pipeline._ import pipeline.config._ diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index fa985cb..5c4b476 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -143,16 +143,17 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste class IBusSimplePlugin(resetVector : BigInt, + cmdForkOnSecondStage : Boolean, + cmdForkPersistence : Boolean, catchAccessFault : Boolean = false, - cmdForkOnSecondStage : Boolean = false, - cmdForkPersistence : Boolean = false, prediction : BranchPrediction = NONE, historyRamSizeLog2 : Int = 10, keepPcPlus4 : Boolean = false, compressedGen : Boolean = false, busLatencyMin : Int = 1, pendingMax : Int = 7, - injectorStage : Boolean = true + injectorStage : Boolean = true, + rspHoldValue : Boolean = false ) extends IBusFetcherImpl( catchAccessFault = catchAccessFault, resetVector = resetVector, @@ -168,6 +169,7 @@ class IBusSimplePlugin(resetVector : BigInt, var iBus : IBusSimpleBus = null var decodeExceptionPort : Flow[ExceptionCause] = null + if(rspHoldValue) assert(busLatencyMin == 1) override def setup(pipeline: VexRiscv): Unit = { super.setup(pipeline) @@ -221,22 +223,29 @@ class IBusSimplePlugin(resetVector : BigInt, discardCounter := (if(cmdForkOnSecondStage) pendingCmdNext else pendingCmd - iBus.rsp.fire.asUInt) } - val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0)) - rspBuffer.io.push << iBus.rsp.throwWhen(discardCounter =/= 0).toStream - rspBuffer.io.flush := flush + val rspBufferOutput = Stream(IBusSimpleRsp()) + + val rspBuffer = if(!rspHoldValue) new Area{ + val c = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0)) + c.io.push << iBus.rsp.throwWhen(discardCounter =/= 0).toStream + c.io.flush := flush + rspBufferOutput << c.io.pop + } else new Area{ + rspBufferOutput << iBus.rsp.throwWhen(discardCounter =/= 0).toStream + } val fetchRsp = FetchRsp() fetchRsp.pc := stages.last.output.payload - fetchRsp.rsp := rspBuffer.io.pop.payload - fetchRsp.rsp.error.clearWhen(!rspBuffer.io.pop.valid) //Avoid interference with instruction injection from the debug plugin + fetchRsp.rsp := rspBufferOutput.payload + fetchRsp.rsp.error.clearWhen(!rspBufferOutput.valid) //Avoid interference with instruction injection from the debug plugin var issueDetected = False val join = Stream(FetchRsp()) - join.valid := stages.last.output.valid && rspBuffer.io.pop.valid + join.valid := stages.last.output.valid && rspBufferOutput.valid join.payload := fetchRsp stages.last.output.ready := stages.last.output.valid ? join.fire | join.ready - rspBuffer.io.pop.ready := join.fire + rspBufferOutput.ready := join.fire output << join.haltWhen(issueDetected) if(catchAccessFault){ diff --git a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala index c1a4409..12793b9 100644 --- a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala +++ b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala @@ -11,10 +11,14 @@ trait RegFileReadKind object ASYNC extends RegFileReadKind object SYNC extends RegFileReadKind -class RegFilePlugin(regFileReadyKind : RegFileReadKind,zeroBoot : Boolean = false, writeRfInMemoryStage : Boolean = false) extends Plugin[VexRiscv]{ +class RegFilePlugin(regFileReadyKind : RegFileReadKind, + zeroBoot : Boolean = false, + writeRfInMemoryStage : Boolean = false, + readInExecute : Boolean = false) extends Plugin[VexRiscv]{ import Riscv._ - assert(!writeRfInMemoryStage) +// assert(!writeRfInMemoryStage) + override def setup(pipeline: VexRiscv): Unit = { import pipeline.config._ @@ -33,19 +37,21 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,zeroBoot : Boolean = fals if(zeroBoot) regFile.init(List.fill(32)(B(0, 32 bits))) } - //Read register file - decode plug new Area{ - import decode._ + //Disable rd0 write in decoding stage + when(decode.input(INSTRUCTION)(rdRange) === 0) { + decode.input(REGFILE_WRITE_VALID) := False + } - //Disable rd0 write in decoding stage - when(decode.input(INSTRUCTION)(rdRange) === 0) { - decode.input(REGFILE_WRITE_VALID) := False - } + //Read register file + val readStage = if(readInExecute) execute else decode + readStage plug new Area{ + import readStage._ //read register file val srcInstruction = regFileReadyKind match{ case `ASYNC` => input(INSTRUCTION) - case `SYNC` => input(INSTRUCTION_ANTICIPATED) + case `SYNC` if !readInExecute => input(INSTRUCTION_ANTICIPATED) + case `SYNC` if readInExecute => Mux(execute.arbitration.isStuck, execute.input(INSTRUCTION), decode.input(INSTRUCTION)) } val regFileReadAddress1 = srcInstruction(Riscv.rs1Range).asUInt @@ -61,8 +67,9 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,zeroBoot : Boolean = fals } //Write register file - (if(writeRfInMemoryStage) memory else writeBack) plug new Area { - import writeBack._ + val writeStage = if(writeRfInMemoryStage) memory else writeBack + writeStage plug new Area { + import writeStage._ val regFileWrite = global.regFile.writePort.addAttribute(Verilator.public) regFileWrite.valid := output(REGFILE_WRITE_VALID) && arbitration.isFiring diff --git a/src/test/scala/vexriscv/experimental/GenMicro.scala b/src/test/scala/vexriscv/experimental/GenMicro.scala new file mode 100644 index 0000000..e5a9eaf --- /dev/null +++ b/src/test/scala/vexriscv/experimental/GenMicro.scala @@ -0,0 +1,113 @@ +package vexriscv.experimental + +import spinal.core._ +import spinal.lib.eda.bench.{AlteraStdTargets, Bench, Rtl, XilinxStdTargets} +import spinal.lib.eda.icestorm.IcestormStdTargets +import vexriscv.demo.{GenSmallestNoCsr, Murax, MuraxConfig} +import vexriscv.plugin._ +import vexriscv.{VexRiscv, VexRiscvConfig, plugin} + +/** + * Created by spinalvm on 15.06.17. + */ +object GenMicro extends App{ + def cpu() = { + val removeOneFetchStage = true + val writeBackOpt = true + val onlyLoadWords = true + val rspHoldValue = true + val earlyBranch = false + val noShifter = true + val pessimisticHazard = true + new VexRiscv( + config = VexRiscvConfig( + plugins = List( + // new PcManagerSimplePlugin( + // resetVector = 0x00000000l, + // relaxedPcCalculation = false + // ), + + new IBusSimplePlugin( + resetVector = 0x80000000l, + cmdForkOnSecondStage = false, + cmdForkPersistence = false, + prediction = NONE, + catchAccessFault = false, + compressedGen = false, + injectorStage = !removeOneFetchStage, + rspHoldValue = rspHoldValue + ), + new DBusSimplePlugin( + catchAddressMisaligned = false, + catchAccessFault = false, + earlyInjection = writeBackOpt, + onlyLoadWords = onlyLoadWords + ), + new DecoderSimplePlugin( + catchIllegalInstruction = false + ), + new RegFilePlugin( + regFileReadyKind = plugin.SYNC, + zeroBoot = false, + readInExecute = removeOneFetchStage, + writeRfInMemoryStage = writeBackOpt + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false, + executeInsertion = removeOneFetchStage + ), + if(!pessimisticHazard) + new HazardSimplePlugin( + bypassExecute = false, + bypassMemory = false, + bypassWriteBack = false, + bypassWriteBackBuffer = false, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ) + else + new HazardPessimisticPlugin(), + new BranchPlugin( + earlyBranch = earlyBranch, + catchAddressMisaligned = false + ), + new YamlPlugin("cpu0.yaml") + ) ++ (if(noShifter) Nil else List(new LightShifterPlugin)) + ) + ) + } + SpinalConfig(mergeAsyncProcess = false).generateVerilog(cpu()) +} + + + +object GenMicroSynthesis { + def main(args: Array[String]) { + val microNoCsr = new Rtl { + override def getName(): String = "MicroNoCsr" + override def getRtlPath(): String = "MicroNoCsr.v" + SpinalVerilog(GenMicro.cpu().setDefinitionName(getRtlPath().split("\\.").head)) + } + + val smallestNoCsr = new Rtl { + override def getName(): String = "SmallestNoCsr" + override def getRtlPath(): String = "SmallestNoCsr.v" + SpinalVerilog(GenSmallestNoCsr.cpu().setDefinitionName(getRtlPath().split("\\.").head)) + } + + val rtls = List(microNoCsr) +// val rtls = List(smallestNoCsr) + + val targets = IcestormStdTargets().take(1) ++ XilinxStdTargets( + vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" + ) ++ AlteraStdTargets( + quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/", + quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/" + ) + + + Bench(rtls, targets, "/eda/tmp/") + } +} \ No newline at end of file diff --git a/src/test/scala/vexriscv/experimental/config.scala b/src/test/scala/vexriscv/experimental/config.scala index b44e662..d6eca55 100644 --- a/src/test/scala/vexriscv/experimental/config.scala +++ b/src/test/scala/vexriscv/experimental/config.scala @@ -12,7 +12,7 @@ object Presentation extends App{ val config = VexRiscvConfig() config.plugins ++= List( - new IBusSimplePlugin(resetVector = 0x80000000l), +// new IBusSimplePlugin(resetVector = 0x80000000l), new DBusSimplePlugin, new CsrPlugin(CsrPluginConfig.smallest), new DecoderSimplePlugin, From 68f1ff322278a0cd3859d04db0519abe061dd94a Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 10 Oct 2018 19:23:04 +0200 Subject: [PATCH 24/56] Add CsrPlugin ebreak support --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index dc306e3..d96e935 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -51,6 +51,7 @@ case class CsrPluginConfig( ucycleAccess : CsrAccess, wfiGen : Boolean, ecallGen : Boolean, + ebreakGen : Boolean = false, supervisorGen : Boolean = false, sscratchGen : Boolean = false, stvecAccess : CsrAccess = CsrAccess.NONE, @@ -66,7 +67,7 @@ case class CsrPluginConfig( ){ assert(!ucycleAccess.canWrite) - def noException = this.copy(ecallGen = false, catchIllegalAccess = false) + def noException = this.copy(ecallGen = false, ebreakGen = false, catchIllegalAccess = false) } object CsrPluginConfig{ @@ -248,6 +249,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val NONE, XRET = newElement() val WFI = if(wfiGen) newElement() else null val ECALL = if(ecallGen) newElement() else null + val EBREAK = if(ebreakGen) newElement() else null } object ENV_CTRL extends Stageable(EnvCtrlEnum()) @@ -304,6 +306,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio )) if(wfiGen) decoderService.add(WFI, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.WFI)) if(ecallGen) decoderService.add(ECALL, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.ECALL, HAS_SIDE_EFFECT -> True)) + if(ebreakGen) decoderService.add(EBREAK, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.EBREAK, HAS_SIDE_EFFECT -> True)) val pcManagerService = pipeline.service(classOf[JumpService]) jumpInterface = pcManagerService.createJumpInterface(pipeline.writeBack) @@ -321,7 +324,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio privilege = RegInit(U"11").setName("CsrPlugin_privilege") - if(catchIllegalAccess || ecallGen) + if(catchIllegalAccess || ecallGen || ebreakGen) selfException = newExceptionPort(pipeline.execute) allowInterrupts = True @@ -762,6 +765,12 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } + if(ebreakGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.EBREAK){ + selfException.valid := True + selfException.code := 3 + } + + val imm = IMM(input(INSTRUCTION)) val writeSrc = input(REGFILE_WRITE_DATA) val readData = B(0, 32 bits) From 40d85b8c70e6f5ca40b702140d8cb1cb56b68350 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 10 Oct 2018 21:13:21 +0200 Subject: [PATCH 25/56] Add fenceiGenAsAJump into BranchPlugin --- .../scala/vexriscv/plugin/BranchPlugin.scala | 41 ++++++++++++++----- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index 50df75a..2ce64a1 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -48,8 +48,11 @@ trait PredictionInterface{ def askDecodePrediction() : DecodePredictionBus } + + class BranchPlugin(earlyBranch : Boolean, - catchAddressMisaligned : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{ + catchAddressMisaligned : Boolean = false, + fenceiGenAsAJump : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{ lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory @@ -57,7 +60,7 @@ class BranchPlugin(earlyBranch : Boolean, object BRANCH_CALC extends Stageable(UInt(32 bits)) object BRANCH_DO extends Stageable(Bool) object BRANCH_COND_RESULT extends Stageable(Bool) -// object PREDICTION_HAD_BRANCHED extends Stageable(Bool) + object IS_FENCEI extends Stageable(Bool) var jumpInterface : Flow[UInt] = null var predictionJumpInterface : Flow[UInt] = null @@ -82,8 +85,7 @@ class BranchPlugin(earlyBranch : Boolean, override def setup(pipeline: VexRiscv): Unit = { import Riscv._ import pipeline.config._ - - val decoderService = pipeline.service(classOf[DecoderService]) + import IntAluPlugin._ val bActions = List[(Stageable[_ <: BaseType],Any)]( SRC1_CTRL -> Src1CtrlEnum.RS, @@ -102,7 +104,8 @@ class BranchPlugin(earlyBranch : Boolean, HAS_SIDE_EFFECT -> True ) - import IntAluPlugin._ + val decoderService = pipeline.service(classOf[DecoderService]) + decoderService.addDefault(BRANCH_CTRL, BranchCtrlEnum.INC) val rvc = pipeline(RVC_GEN) @@ -117,6 +120,13 @@ class BranchPlugin(earlyBranch : Boolean, BGEU(rvc) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> True)) )) + if(fenceiGenAsAJump) { + decoderService.addDefault(IS_FENCEI, False) + decoderService.add(List( + FENCEI -> (List(IS_FENCEI -> True,HAS_SIDE_EFFECT -> True, BRANCH_CTRL -> BranchCtrlEnum.JAL)) + )) + } + val pcManagerService = pipeline.service(classOf[JumpService]) jumpInterface = pcManagerService.createJumpInterface(branchStage) @@ -127,12 +137,21 @@ class BranchPlugin(earlyBranch : Boolean, } } - override def build(pipeline: VexRiscv): Unit = (fetchPrediction,decodePrediction) match { - case (null, null) => buildWithoutPrediction(pipeline) - case (_ , null) => buildFetchPrediction(pipeline) - case (null, _) => buildDecodePrediction(pipeline) -// case `DYNAMIC` => buildWithPrediction(pipeline) -// case `DYNAMIC_TARGET` => buildDynamicTargetPrediction(pipeline) + override def build(pipeline: VexRiscv): Unit = { + (fetchPrediction,decodePrediction) match { + case (null, null) => buildWithoutPrediction(pipeline) + case (_ , null) => buildFetchPrediction(pipeline) + case (null, _) => buildDecodePrediction(pipeline) + } + if(fenceiGenAsAJump) { + import pipeline._ + import pipeline.config._ + when(decode.input(IS_FENCEI)) { + decode.output(INSTRUCTION)(12) := False + decode.output(INSTRUCTION)(22) := True + } + execute.arbitration.haltByOther setWhen(execute.arbitration.isValid && execute.input(IS_FENCEI) && List(memory,writeBack).map(_.arbitration.isValid).orR) + } } def buildWithoutPrediction(pipeline: VexRiscv): Unit = { From 8b1a4a2717c266297c5d525af420e5abe4c609eb Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 11 Oct 2018 00:25:39 +0200 Subject: [PATCH 26/56] Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval --- src/main/scala/vexriscv/Riscv.scala | 1 + src/main/scala/vexriscv/TestsWorkspace.scala | 55 +-- src/main/scala/vexriscv/demo/Murax.scala | 2 +- .../scala/vexriscv/demo/SynthesisBench.scala | 17 +- src/test/cpp/regression/.cproject | 233 ++++++++++-- src/test/cpp/regression/I-ADD-01.out32 | 11 + src/test/cpp/regression/I-ADDI-01.out32 | 11 + src/test/cpp/regression/I-AND-01.out32 | 11 + src/test/cpp/regression/I-ANDI-01.out32 | 11 + src/test/cpp/regression/I-AUIPC-01.out32 | 4 + src/test/cpp/regression/I-BEQ-01.out32 | 10 + src/test/cpp/regression/I-BGE-01.out32 | 10 + src/test/cpp/regression/I-BGEU-01.out32 | 10 + src/test/cpp/regression/I-BLT-01.out32 | 10 + src/test/cpp/regression/I-BLTU-01.out32 | 10 + src/test/cpp/regression/I-BNE-01.out32 | 10 + src/test/cpp/regression/I-CSRRC-01.out32 | 6 + src/test/cpp/regression/I-CSRRCI-01.out32 | 4 + src/test/cpp/regression/I-CSRRS-01.out32 | 6 + src/test/cpp/regression/I-CSRRSI-01.out32 | 4 + src/test/cpp/regression/I-CSRRW-01.out32 | 4 + src/test/cpp/regression/I-CSRRWI-01.out32 | 2 + .../cpp/regression/I-DELAY_SLOTS-01.out32 | 2 + src/test/cpp/regression/I-EBREAK-01.out32 | 1 + src/test/cpp/regression/I-ECALL-01.out32 | 1 + src/test/cpp/regression/I-ENDIANESS-01.out32 | 2 + src/test/cpp/regression/I-FENCE.I-01.out32 | 1 + src/test/cpp/regression/I-IO.out32 | 11 + src/test/cpp/regression/I-JAL-01.out32 | 5 + src/test/cpp/regression/I-JALR-01.out32 | 6 + src/test/cpp/regression/I-LB-01.out32 | 9 + src/test/cpp/regression/I-LBU-01.out32 | 9 + src/test/cpp/regression/I-LH-01.out32 | 5 + src/test/cpp/regression/I-LHU-01.out32 | 5 + src/test/cpp/regression/I-LUI-01.out32 | 4 + src/test/cpp/regression/I-LW-01.out32 | 3 + .../cpp/regression/I-MISALIGN_JMP-01.out32 | 0 .../cpp/regression/I-MISALIGN_LDST-01.out32 | 11 + src/test/cpp/regression/I-NOP-01.out32 | 8 + src/test/cpp/regression/I-OR-01.out32 | 11 + src/test/cpp/regression/I-ORI-01.out32 | 11 + src/test/cpp/regression/I-RF_size-01.out32 | 9 + src/test/cpp/regression/I-RF_width-01.out32 | 8 + src/test/cpp/regression/I-RF_x0-01.out32 | 3 + src/test/cpp/regression/I-SB-01.out32 | 4 + src/test/cpp/regression/I-SH-01.out32 | 4 + src/test/cpp/regression/I-SLL-01.out32 | 11 + src/test/cpp/regression/I-SLLI-01.out32 | 10 + src/test/cpp/regression/I-SLT-01.out32 | 12 + src/test/cpp/regression/I-SLTI-01.out32 | 11 + src/test/cpp/regression/I-SLTIU-01.out32 | 11 + src/test/cpp/regression/I-SLTU-01.out32 | 12 + src/test/cpp/regression/I-SRA-01.out32 | 11 + src/test/cpp/regression/I-SRAI-01.out32 | 10 + src/test/cpp/regression/I-SRL-01.out32 | 11 + src/test/cpp/regression/I-SRLI-01.out32 | 10 + src/test/cpp/regression/I-SUB-01.out32 | 11 + src/test/cpp/regression/I-SW-01.out32 | 4 + src/test/cpp/regression/I-XOR-01.out32 | 11 + src/test/cpp/regression/I-XORI-01.out32 | 11 + src/test/cpp/regression/main.cpp | 129 ++++++- src/test/cpp/regression/makefile | 2 +- src/test/resources/asm/I-ADD-01.elf.objdump | 344 +++++++++++++++++ src/test/resources/asm/I-ADDI-01.elf.objdump | 310 +++++++++++++++ src/test/resources/asm/I-AND-01.elf.objdump | 349 +++++++++++++++++ src/test/resources/asm/I-ANDI-01.elf.objdump | 310 +++++++++++++++ src/test/resources/asm/I-AUIPC-01.elf.objdump | 205 ++++++++++ src/test/resources/asm/I-BEQ-01.elf.objdump | 356 +++++++++++++++++ src/test/resources/asm/I-BGE-01.elf.objdump | 357 +++++++++++++++++ src/test/resources/asm/I-BGEU-01.elf.objdump | 357 +++++++++++++++++ src/test/resources/asm/I-BLT-01.elf.objdump | 358 ++++++++++++++++++ src/test/resources/asm/I-BLTU-01.elf.objdump | 357 +++++++++++++++++ src/test/resources/asm/I-BNE-01.elf.objdump | 358 ++++++++++++++++++ src/test/resources/asm/I-CSRRC-01.elf.objdump | 188 +++++++++ .../resources/asm/I-CSRRCI-01.elf.objdump | 119 ++++++ src/test/resources/asm/I-CSRRS-01.elf.objdump | 187 +++++++++ .../resources/asm/I-CSRRSI-01.elf.objdump | 116 ++++++ src/test/resources/asm/I-CSRRW-01.elf.objdump | 145 +++++++ .../resources/asm/I-CSRRWI-01.elf.objdump | 74 ++++ .../asm/I-DELAY_SLOTS-01.elf.objdump | 136 +++++++ .../resources/asm/I-EBREAK-01.elf.objdump | 69 ++++ src/test/resources/asm/I-ECALL-01.elf.objdump | 69 ++++ .../resources/asm/I-ENDIANESS-01.elf.objdump | 80 ++++ .../resources/asm/I-FENCE.I-01.elf.objdump | 76 ++++ src/test/resources/asm/I-IO.elf.objdump | 344 +++++++++++++++++ src/test/resources/asm/I-JAL-01.elf.objdump | 227 +++++++++++ src/test/resources/asm/I-JALR-01.elf.objdump | 289 ++++++++++++++ src/test/resources/asm/I-LB-01.elf.objdump | 289 ++++++++++++++ src/test/resources/asm/I-LBU-01.elf.objdump | 289 ++++++++++++++ src/test/resources/asm/I-LH-01.elf.objdump | 225 +++++++++++ src/test/resources/asm/I-LHU-01.elf.objdump | 225 +++++++++++ src/test/resources/asm/I-LUI-01.elf.objdump | 128 +++++++ src/test/resources/asm/I-LW-01.elf.objdump | 193 ++++++++++ .../asm/I-MISALIGN_JMP-01.elf.objdump | 268 +++++++++++++ .../asm/I-MISALIGN_LDST-01.elf.objdump | 242 ++++++++++++ src/test/resources/asm/I-NOP-01.elf.objdump | 183 +++++++++ src/test/resources/asm/I-OR-01.elf.objdump | 350 +++++++++++++++++ src/test/resources/asm/I-ORI-01.elf.objdump | 310 +++++++++++++++ .../resources/asm/I-RF_size-01.elf.objdump | 218 +++++++++++ .../resources/asm/I-RF_width-01.elf.objdump | 262 +++++++++++++ src/test/resources/asm/I-RF_x0-01.elf.objdump | 135 +++++++ src/test/resources/asm/I-SB-01.elf.objdump | 225 +++++++++++ src/test/resources/asm/I-SH-01.elf.objdump | 208 ++++++++++ src/test/resources/asm/I-SLL-01.elf.objdump | 340 +++++++++++++++++ src/test/resources/asm/I-SLLI-01.elf.objdump | 276 ++++++++++++++ src/test/resources/asm/I-SLT-01.elf.objdump | 332 ++++++++++++++++ src/test/resources/asm/I-SLTI-01.elf.objdump | 277 ++++++++++++++ src/test/resources/asm/I-SLTIU-01.elf.objdump | 276 ++++++++++++++ src/test/resources/asm/I-SLTU-01.elf.objdump | 331 ++++++++++++++++ src/test/resources/asm/I-SRA-01.elf.objdump | 340 +++++++++++++++++ src/test/resources/asm/I-SRAI-01.elf.objdump | 276 ++++++++++++++ src/test/resources/asm/I-SRL-01.elf.objdump | 340 +++++++++++++++++ src/test/resources/asm/I-SRLI-01.elf.objdump | 276 ++++++++++++++ src/test/resources/asm/I-SUB-01.elf.objdump | 344 +++++++++++++++++ src/test/resources/asm/I-SW-01.elf.objdump | 182 +++++++++ src/test/resources/asm/I-XOR-01.elf.objdump | 350 +++++++++++++++++ src/test/resources/asm/I-XORI-01.elf.objdump | 310 +++++++++++++++ src/test/resources/hex/I-ADD-01.elf.hex | 65 ++++ src/test/resources/hex/I-ADDI-01.elf.hex | 56 +++ src/test/resources/hex/I-AND-01.elf.hex | 66 ++++ src/test/resources/hex/I-ANDI-01.elf.hex | 56 +++ src/test/resources/hex/I-AUIPC-01.elf.hex | 42 ++ src/test/resources/hex/I-BEQ-01.elf.hex | 72 ++++ src/test/resources/hex/I-BGE-01.elf.hex | 72 ++++ src/test/resources/hex/I-BGEU-01.elf.hex | 72 ++++ src/test/resources/hex/I-BLT-01.elf.hex | 72 ++++ src/test/resources/hex/I-BLTU-01.elf.hex | 72 ++++ src/test/resources/hex/I-BNE-01.elf.hex | 72 ++++ src/test/resources/hex/I-CSRRC-01.elf.hex | 39 ++ src/test/resources/hex/I-CSRRCI-01.elf.hex | 25 ++ src/test/resources/hex/I-CSRRS-01.elf.hex | 38 ++ src/test/resources/hex/I-CSRRSI-01.elf.hex | 24 ++ src/test/resources/hex/I-CSRRW-01.elf.hex | 30 ++ src/test/resources/hex/I-CSRRWI-01.elf.hex | 16 + .../resources/hex/I-DELAY_SLOTS-01.elf.hex | 29 ++ src/test/resources/hex/I-EBREAK-01.elf.hex | 15 + src/test/resources/hex/I-ECALL-01.elf.hex | 15 + src/test/resources/hex/I-ENDIANESS-01.elf.hex | 17 + src/test/resources/hex/I-FENCE.I-01.elf.hex | 16 + src/test/resources/hex/I-IO.elf.hex | 65 ++++ src/test/resources/hex/I-JAL-01.elf.hex | 46 +++ src/test/resources/hex/I-JALR-01.elf.hex | 60 +++ src/test/resources/hex/I-LB-01.elf.hex | 51 +++ src/test/resources/hex/I-LBU-01.elf.hex | 51 +++ src/test/resources/hex/I-LH-01.elf.hex | 39 ++ src/test/resources/hex/I-LHU-01.elf.hex | 39 ++ src/test/resources/hex/I-LUI-01.elf.hex | 27 ++ src/test/resources/hex/I-LW-01.elf.hex | 33 ++ .../resources/hex/I-MISALIGN_JMP-01.elf.hex | 53 +++ .../resources/hex/I-MISALIGN_LDST-01.elf.hex | 44 +++ src/test/resources/hex/I-NOP-01.elf.hex | 37 ++ src/test/resources/hex/I-OR-01.elf.hex | 66 ++++ src/test/resources/hex/I-ORI-01.elf.hex | 56 +++ src/test/resources/hex/I-RF_size-01.elf.hex | 45 +++ src/test/resources/hex/I-RF_width-01.elf.hex | 57 +++ src/test/resources/hex/I-RF_x0-01.elf.hex | 29 ++ src/test/resources/hex/I-SB-01.elf.hex | 45 +++ src/test/resources/hex/I-SH-01.elf.hex | 41 ++ src/test/resources/hex/I-SLL-01.elf.hex | 64 ++++ src/test/resources/hex/I-SLLI-01.elf.hex | 50 +++ src/test/resources/hex/I-SLT-01.elf.hex | 63 +++ src/test/resources/hex/I-SLTI-01.elf.hex | 51 +++ src/test/resources/hex/I-SLTIU-01.elf.hex | 51 +++ src/test/resources/hex/I-SLTU-01.elf.hex | 63 +++ src/test/resources/hex/I-SRA-01.elf.hex | 64 ++++ src/test/resources/hex/I-SRAI-01.elf.hex | 50 +++ src/test/resources/hex/I-SRL-01.elf.hex | 64 ++++ src/test/resources/hex/I-SRLI-01.elf.hex | 50 +++ src/test/resources/hex/I-SUB-01.elf.hex | 65 ++++ src/test/resources/hex/I-SW-01.elf.hex | 34 ++ src/test/resources/hex/I-XOR-01.elf.hex | 66 ++++ src/test/resources/hex/I-XORI-01.elf.hex | 56 +++ .../resources/ref/I-ADD-01.reference_output | 11 + .../resources/ref/I-ADDI-01.reference_output | 11 + .../resources/ref/I-AND-01.reference_output | 11 + .../resources/ref/I-ANDI-01.reference_output | 11 + .../resources/ref/I-AUIPC-01.reference_output | 4 + .../resources/ref/I-BEQ-01.reference_output | 10 + .../resources/ref/I-BGE-01.reference_output | 10 + .../resources/ref/I-BGEU-01.reference_output | 10 + .../resources/ref/I-BLT-01.reference_output | 10 + .../resources/ref/I-BLTU-01.reference_output | 10 + .../resources/ref/I-BNE-01.reference_output | 10 + .../resources/ref/I-CSRRC-01.reference_output | 6 + .../ref/I-CSRRCI-01.reference_output | 4 + .../resources/ref/I-CSRRS-01.reference_output | 6 + .../ref/I-CSRRSI-01.reference_output | 4 + .../resources/ref/I-CSRRW-01.reference_output | 4 + .../ref/I-CSRRWI-01.reference_output | 2 + .../ref/I-DELAY_SLOTS-01.reference_output | 2 + .../ref/I-EBREAK-01.reference_output | 1 + .../resources/ref/I-ECALL-01.reference_output | 1 + .../ref/I-ENDIANESS-01.reference_output | 2 + .../ref/I-FENCE.I-01.reference_output | 1 + src/test/resources/ref/I-IO.reference_output | 11 + .../resources/ref/I-JAL-01.reference_output | 5 + .../resources/ref/I-JALR-01.reference_output | 6 + .../resources/ref/I-LB-01.reference_output | 9 + .../resources/ref/I-LBU-01.reference_output | 9 + .../resources/ref/I-LH-01.reference_output | 5 + .../resources/ref/I-LHU-01.reference_output | 5 + .../resources/ref/I-LUI-01.reference_output | 4 + .../resources/ref/I-LW-01.reference_output | 3 + .../ref/I-MISALIGN_JMP-01.reference_output | 9 + .../ref/I-MISALIGN_LDST-01.reference_output | 11 + .../resources/ref/I-NOP-01.reference_output | 8 + .../resources/ref/I-OR-01.reference_output | 11 + .../resources/ref/I-ORI-01.reference_output | 11 + .../ref/I-RF_size-01.reference_output | 9 + .../ref/I-RF_width-01.reference_output | 8 + .../resources/ref/I-RF_x0-01.reference_output | 3 + .../resources/ref/I-SB-01.reference_output | 4 + .../resources/ref/I-SH-01.reference_output | 4 + .../resources/ref/I-SLL-01.reference_output | 11 + .../resources/ref/I-SLLI-01.reference_output | 10 + .../resources/ref/I-SLT-01.reference_output | 12 + .../resources/ref/I-SLTI-01.reference_output | 11 + .../resources/ref/I-SLTIU-01.reference_output | 11 + .../resources/ref/I-SLTU-01.reference_output | 12 + .../resources/ref/I-SRA-01.reference_output | 11 + .../resources/ref/I-SRAI-01.reference_output | 10 + .../resources/ref/I-SRL-01.reference_output | 11 + .../resources/ref/I-SRLI-01.reference_output | 10 + .../resources/ref/I-SUB-01.reference_output | 11 + .../resources/ref/I-SW-01.reference_output | 4 + .../resources/ref/I-XOR-01.reference_output | 11 + .../resources/ref/I-XORI-01.reference_output | 11 + .../vexriscv/experimental/GenMicro.scala | 4 +- 228 files changed, 17639 insertions(+), 75 deletions(-) create mode 100644 src/test/cpp/regression/I-ADD-01.out32 create mode 100644 src/test/cpp/regression/I-ADDI-01.out32 create mode 100644 src/test/cpp/regression/I-AND-01.out32 create mode 100644 src/test/cpp/regression/I-ANDI-01.out32 create mode 100644 src/test/cpp/regression/I-AUIPC-01.out32 create mode 100644 src/test/cpp/regression/I-BEQ-01.out32 create mode 100644 src/test/cpp/regression/I-BGE-01.out32 create mode 100644 src/test/cpp/regression/I-BGEU-01.out32 create mode 100644 src/test/cpp/regression/I-BLT-01.out32 create mode 100644 src/test/cpp/regression/I-BLTU-01.out32 create mode 100644 src/test/cpp/regression/I-BNE-01.out32 create mode 100644 src/test/cpp/regression/I-CSRRC-01.out32 create mode 100644 src/test/cpp/regression/I-CSRRCI-01.out32 create mode 100644 src/test/cpp/regression/I-CSRRS-01.out32 create mode 100644 src/test/cpp/regression/I-CSRRSI-01.out32 create mode 100644 src/test/cpp/regression/I-CSRRW-01.out32 create mode 100644 src/test/cpp/regression/I-CSRRWI-01.out32 create mode 100644 src/test/cpp/regression/I-DELAY_SLOTS-01.out32 create mode 100644 src/test/cpp/regression/I-EBREAK-01.out32 create mode 100644 src/test/cpp/regression/I-ECALL-01.out32 create mode 100644 src/test/cpp/regression/I-ENDIANESS-01.out32 create mode 100644 src/test/cpp/regression/I-FENCE.I-01.out32 create mode 100644 src/test/cpp/regression/I-IO.out32 create mode 100644 src/test/cpp/regression/I-JAL-01.out32 create mode 100644 src/test/cpp/regression/I-JALR-01.out32 create mode 100644 src/test/cpp/regression/I-LB-01.out32 create mode 100644 src/test/cpp/regression/I-LBU-01.out32 create mode 100644 src/test/cpp/regression/I-LH-01.out32 create mode 100644 src/test/cpp/regression/I-LHU-01.out32 create mode 100644 src/test/cpp/regression/I-LUI-01.out32 create mode 100644 src/test/cpp/regression/I-LW-01.out32 create mode 100644 src/test/cpp/regression/I-MISALIGN_JMP-01.out32 create mode 100644 src/test/cpp/regression/I-MISALIGN_LDST-01.out32 create mode 100644 src/test/cpp/regression/I-NOP-01.out32 create mode 100644 src/test/cpp/regression/I-OR-01.out32 create mode 100644 src/test/cpp/regression/I-ORI-01.out32 create mode 100644 src/test/cpp/regression/I-RF_size-01.out32 create mode 100644 src/test/cpp/regression/I-RF_width-01.out32 create mode 100644 src/test/cpp/regression/I-RF_x0-01.out32 create mode 100644 src/test/cpp/regression/I-SB-01.out32 create mode 100644 src/test/cpp/regression/I-SH-01.out32 create mode 100644 src/test/cpp/regression/I-SLL-01.out32 create mode 100644 src/test/cpp/regression/I-SLLI-01.out32 create mode 100644 src/test/cpp/regression/I-SLT-01.out32 create mode 100644 src/test/cpp/regression/I-SLTI-01.out32 create mode 100644 src/test/cpp/regression/I-SLTIU-01.out32 create mode 100644 src/test/cpp/regression/I-SLTU-01.out32 create mode 100644 src/test/cpp/regression/I-SRA-01.out32 create mode 100644 src/test/cpp/regression/I-SRAI-01.out32 create mode 100644 src/test/cpp/regression/I-SRL-01.out32 create mode 100644 src/test/cpp/regression/I-SRLI-01.out32 create mode 100644 src/test/cpp/regression/I-SUB-01.out32 create mode 100644 src/test/cpp/regression/I-SW-01.out32 create mode 100644 src/test/cpp/regression/I-XOR-01.out32 create mode 100644 src/test/cpp/regression/I-XORI-01.out32 create mode 100644 src/test/resources/asm/I-ADD-01.elf.objdump create mode 100644 src/test/resources/asm/I-ADDI-01.elf.objdump create mode 100644 src/test/resources/asm/I-AND-01.elf.objdump create mode 100644 src/test/resources/asm/I-ANDI-01.elf.objdump create mode 100644 src/test/resources/asm/I-AUIPC-01.elf.objdump create mode 100644 src/test/resources/asm/I-BEQ-01.elf.objdump create mode 100644 src/test/resources/asm/I-BGE-01.elf.objdump create mode 100644 src/test/resources/asm/I-BGEU-01.elf.objdump create mode 100644 src/test/resources/asm/I-BLT-01.elf.objdump create mode 100644 src/test/resources/asm/I-BLTU-01.elf.objdump create mode 100644 src/test/resources/asm/I-BNE-01.elf.objdump create mode 100644 src/test/resources/asm/I-CSRRC-01.elf.objdump create mode 100644 src/test/resources/asm/I-CSRRCI-01.elf.objdump create mode 100644 src/test/resources/asm/I-CSRRS-01.elf.objdump create mode 100644 src/test/resources/asm/I-CSRRSI-01.elf.objdump create mode 100644 src/test/resources/asm/I-CSRRW-01.elf.objdump create mode 100644 src/test/resources/asm/I-CSRRWI-01.elf.objdump create mode 100644 src/test/resources/asm/I-DELAY_SLOTS-01.elf.objdump create mode 100644 src/test/resources/asm/I-EBREAK-01.elf.objdump create mode 100644 src/test/resources/asm/I-ECALL-01.elf.objdump create mode 100644 src/test/resources/asm/I-ENDIANESS-01.elf.objdump create mode 100644 src/test/resources/asm/I-FENCE.I-01.elf.objdump create mode 100644 src/test/resources/asm/I-IO.elf.objdump create mode 100644 src/test/resources/asm/I-JAL-01.elf.objdump create mode 100644 src/test/resources/asm/I-JALR-01.elf.objdump create mode 100644 src/test/resources/asm/I-LB-01.elf.objdump create mode 100644 src/test/resources/asm/I-LBU-01.elf.objdump create mode 100644 src/test/resources/asm/I-LH-01.elf.objdump create mode 100644 src/test/resources/asm/I-LHU-01.elf.objdump create mode 100644 src/test/resources/asm/I-LUI-01.elf.objdump create mode 100644 src/test/resources/asm/I-LW-01.elf.objdump create mode 100644 src/test/resources/asm/I-MISALIGN_JMP-01.elf.objdump create mode 100644 src/test/resources/asm/I-MISALIGN_LDST-01.elf.objdump create mode 100644 src/test/resources/asm/I-NOP-01.elf.objdump create mode 100644 src/test/resources/asm/I-OR-01.elf.objdump create mode 100644 src/test/resources/asm/I-ORI-01.elf.objdump create mode 100644 src/test/resources/asm/I-RF_size-01.elf.objdump create mode 100644 src/test/resources/asm/I-RF_width-01.elf.objdump create mode 100644 src/test/resources/asm/I-RF_x0-01.elf.objdump create mode 100644 src/test/resources/asm/I-SB-01.elf.objdump create mode 100644 src/test/resources/asm/I-SH-01.elf.objdump create mode 100644 src/test/resources/asm/I-SLL-01.elf.objdump create mode 100644 src/test/resources/asm/I-SLLI-01.elf.objdump create mode 100644 src/test/resources/asm/I-SLT-01.elf.objdump create mode 100644 src/test/resources/asm/I-SLTI-01.elf.objdump create mode 100644 src/test/resources/asm/I-SLTIU-01.elf.objdump create mode 100644 src/test/resources/asm/I-SLTU-01.elf.objdump create mode 100644 src/test/resources/asm/I-SRA-01.elf.objdump create mode 100644 src/test/resources/asm/I-SRAI-01.elf.objdump create mode 100644 src/test/resources/asm/I-SRL-01.elf.objdump create mode 100644 src/test/resources/asm/I-SRLI-01.elf.objdump create mode 100644 src/test/resources/asm/I-SUB-01.elf.objdump create mode 100644 src/test/resources/asm/I-SW-01.elf.objdump create mode 100644 src/test/resources/asm/I-XOR-01.elf.objdump create mode 100644 src/test/resources/asm/I-XORI-01.elf.objdump create mode 100644 src/test/resources/hex/I-ADD-01.elf.hex create mode 100644 src/test/resources/hex/I-ADDI-01.elf.hex create mode 100644 src/test/resources/hex/I-AND-01.elf.hex create mode 100644 src/test/resources/hex/I-ANDI-01.elf.hex create mode 100644 src/test/resources/hex/I-AUIPC-01.elf.hex create mode 100644 src/test/resources/hex/I-BEQ-01.elf.hex create mode 100644 src/test/resources/hex/I-BGE-01.elf.hex create mode 100644 src/test/resources/hex/I-BGEU-01.elf.hex create mode 100644 src/test/resources/hex/I-BLT-01.elf.hex create mode 100644 src/test/resources/hex/I-BLTU-01.elf.hex create mode 100644 src/test/resources/hex/I-BNE-01.elf.hex create mode 100644 src/test/resources/hex/I-CSRRC-01.elf.hex create mode 100644 src/test/resources/hex/I-CSRRCI-01.elf.hex create mode 100644 src/test/resources/hex/I-CSRRS-01.elf.hex create mode 100644 src/test/resources/hex/I-CSRRSI-01.elf.hex create mode 100644 src/test/resources/hex/I-CSRRW-01.elf.hex create mode 100644 src/test/resources/hex/I-CSRRWI-01.elf.hex create mode 100644 src/test/resources/hex/I-DELAY_SLOTS-01.elf.hex create mode 100644 src/test/resources/hex/I-EBREAK-01.elf.hex create mode 100644 src/test/resources/hex/I-ECALL-01.elf.hex create mode 100644 src/test/resources/hex/I-ENDIANESS-01.elf.hex create mode 100644 src/test/resources/hex/I-FENCE.I-01.elf.hex create mode 100644 src/test/resources/hex/I-IO.elf.hex create mode 100644 src/test/resources/hex/I-JAL-01.elf.hex create mode 100644 src/test/resources/hex/I-JALR-01.elf.hex create mode 100644 src/test/resources/hex/I-LB-01.elf.hex create mode 100644 src/test/resources/hex/I-LBU-01.elf.hex create mode 100644 src/test/resources/hex/I-LH-01.elf.hex create mode 100644 src/test/resources/hex/I-LHU-01.elf.hex create mode 100644 src/test/resources/hex/I-LUI-01.elf.hex create mode 100644 src/test/resources/hex/I-LW-01.elf.hex create mode 100644 src/test/resources/hex/I-MISALIGN_JMP-01.elf.hex create mode 100644 src/test/resources/hex/I-MISALIGN_LDST-01.elf.hex create mode 100644 src/test/resources/hex/I-NOP-01.elf.hex create mode 100644 src/test/resources/hex/I-OR-01.elf.hex create mode 100644 src/test/resources/hex/I-ORI-01.elf.hex create mode 100644 src/test/resources/hex/I-RF_size-01.elf.hex create mode 100644 src/test/resources/hex/I-RF_width-01.elf.hex create mode 100644 src/test/resources/hex/I-RF_x0-01.elf.hex create mode 100644 src/test/resources/hex/I-SB-01.elf.hex create mode 100644 src/test/resources/hex/I-SH-01.elf.hex create mode 100644 src/test/resources/hex/I-SLL-01.elf.hex create mode 100644 src/test/resources/hex/I-SLLI-01.elf.hex create mode 100644 src/test/resources/hex/I-SLT-01.elf.hex create mode 100644 src/test/resources/hex/I-SLTI-01.elf.hex create mode 100644 src/test/resources/hex/I-SLTIU-01.elf.hex create mode 100644 src/test/resources/hex/I-SLTU-01.elf.hex create mode 100644 src/test/resources/hex/I-SRA-01.elf.hex create mode 100644 src/test/resources/hex/I-SRAI-01.elf.hex create mode 100644 src/test/resources/hex/I-SRL-01.elf.hex create mode 100644 src/test/resources/hex/I-SRLI-01.elf.hex create mode 100644 src/test/resources/hex/I-SUB-01.elf.hex create mode 100644 src/test/resources/hex/I-SW-01.elf.hex create mode 100644 src/test/resources/hex/I-XOR-01.elf.hex create mode 100644 src/test/resources/hex/I-XORI-01.elf.hex create mode 100644 src/test/resources/ref/I-ADD-01.reference_output create mode 100644 src/test/resources/ref/I-ADDI-01.reference_output create mode 100644 src/test/resources/ref/I-AND-01.reference_output create mode 100644 src/test/resources/ref/I-ANDI-01.reference_output create mode 100644 src/test/resources/ref/I-AUIPC-01.reference_output create mode 100644 src/test/resources/ref/I-BEQ-01.reference_output create mode 100644 src/test/resources/ref/I-BGE-01.reference_output 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src/test/resources/ref/I-ORI-01.reference_output create mode 100644 src/test/resources/ref/I-RF_size-01.reference_output create mode 100644 src/test/resources/ref/I-RF_width-01.reference_output create mode 100644 src/test/resources/ref/I-RF_x0-01.reference_output create mode 100644 src/test/resources/ref/I-SB-01.reference_output create mode 100644 src/test/resources/ref/I-SH-01.reference_output create mode 100644 src/test/resources/ref/I-SLL-01.reference_output create mode 100644 src/test/resources/ref/I-SLLI-01.reference_output create mode 100644 src/test/resources/ref/I-SLT-01.reference_output create mode 100644 src/test/resources/ref/I-SLTI-01.reference_output create mode 100644 src/test/resources/ref/I-SLTIU-01.reference_output create mode 100644 src/test/resources/ref/I-SLTU-01.reference_output create mode 100644 src/test/resources/ref/I-SRA-01.reference_output create mode 100644 src/test/resources/ref/I-SRAI-01.reference_output create mode 100644 src/test/resources/ref/I-SRL-01.reference_output create mode 100644 src/test/resources/ref/I-SRLI-01.reference_output create mode 100644 src/test/resources/ref/I-SUB-01.reference_output create mode 100644 src/test/resources/ref/I-SW-01.reference_output create mode 100644 src/test/resources/ref/I-XOR-01.reference_output create mode 100644 src/test/resources/ref/I-XORI-01.reference_output diff --git a/src/main/scala/vexriscv/Riscv.scala b/src/main/scala/vexriscv/Riscv.scala index a7bc86a..a97f114 100644 --- a/src/main/scala/vexriscv/Riscv.scala +++ b/src/main/scala/vexriscv/Riscv.scala @@ -98,6 +98,7 @@ object Riscv{ def ECALL = M"00000000000000000000000001110011" def EBREAK = M"00000000000100000000000001110011" + def FENCEI = M"00000000000000000001000000001111" def MRET = M"00110000001000000000000001110011" def SRET = M"00010000001000000000000001110011" def WFI = M"00010000010100000000000001110011" diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index 80836e4..c5f0265 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -40,7 +40,7 @@ object TestsWorkspace { catchAccessFault = true, compressedGen = false, busLatencyMin = 1, - injectorStage = false + injectorStage = true ), // new IBusCachedPlugin( // resetVector = 0x80000000l, @@ -65,30 +65,30 @@ object TestsWorkspace { // portTlbSize = 4 // ) // ), -// new DBusSimplePlugin( -// catchAddressMisaligned = true, -// catchAccessFault = true, -// earlyInjection = false -// ), - new DBusCachedPlugin( - config = new DataCacheConfig( - cacheSize = 4096, - bytePerLine = 32, - wayCount = 1, - addressWidth = 32, - cpuDataWidth = 32, - memDataWidth = 32, - catchAccessError = true, - catchIllegal = true, - catchUnaligned = true, - catchMemoryTranslationMiss = true, - atomicEntriesCount = 2 - ), -// memoryTranslatorPortConfig = null - memoryTranslatorPortConfig = MemoryTranslatorPortConfig( - portTlbSize = 6 - ) + new DBusSimplePlugin( + catchAddressMisaligned = true, + catchAccessFault = true, + earlyInjection = false ), +// new DBusCachedPlugin( +// config = new DataCacheConfig( +// cacheSize = 4096, +// bytePerLine = 32, +// wayCount = 1, +// addressWidth = 32, +// cpuDataWidth = 32, +// memDataWidth = 32, +// catchAccessError = true, +// catchIllegal = true, +// catchUnaligned = true, +// catchMemoryTranslationMiss = true, +// atomicEntriesCount = 2 +// ), +//// memoryTranslatorPortConfig = null +// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( +// portTlbSize = 6 +// ) +// ), // new StaticMemoryTranslatorPlugin( // ioRange = _(31 downto 28) === 0xF // ), @@ -129,11 +129,12 @@ object TestsWorkspace { divUnrollFactor = 1 ), // new DivPlugin, - new CsrPlugin(CsrPluginConfig.all2(0x80000020l).copy(deterministicInteruptionEntry = false)), - new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), + new CsrPlugin(CsrPluginConfig.all2(0x80000020l).copy(deterministicInteruptionEntry = false, ebreakGen = true)), +// new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( earlyBranch = true, - catchAddressMisaligned = true + catchAddressMisaligned = true, + fenceiGenAsAJump = true ), new YamlPlugin("cpu0.yaml") ) diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 63023ec..b833beb 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -60,7 +60,7 @@ object MuraxConfig{ pipelineApbBridge = true, gpioWidth = 32, xipConfig = ifGen(withXip) (SpiDdrMasterCtrl.MemoryMappingParameters( - SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(2, 1)).addAllMods(), + SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(2, 2, 1)).addFullDuplex(0,1,false), cmdFifoDepth = 32, rspFifoDepth = 32, xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32) diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index 695fd56..f0ec5cf 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -101,17 +101,22 @@ object VexRiscvSynthesisBench { } - val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) +// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) -// val rtls = List(smallestNoCsr) + val rtls = List(fullNoMmu) + +// val targets = XilinxStdTargets( +// vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" +// ) ++ AlteraStdTargets( +// quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", +// quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" +// ) ++ IcestormStdTargets().take(1) + val targets = XilinxStdTargets( vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" - ) ++ AlteraStdTargets( - quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", - quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" - ) ++ IcestormStdTargets().take(1) + ) // val targets = AlteraStdTargets( // quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", diff --git a/src/test/cpp/regression/.cproject b/src/test/cpp/regression/.cproject index ba579f7..57ac8aa 100644 --- a/src/test/cpp/regression/.cproject +++ b/src/test/cpp/regression/.cproject @@ -1,11 +1,8 @@ - - - - - + + @@ -16,6 +13,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -98,40 +124,177 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/src/test/cpp/regression/I-ADDI-01.out32 new file mode 100644 index 0000000..d8a4aa9 --- /dev/null +++ b/src/test/cpp/regression/I-ADDI-01.out32 @@ -0,0 +1,11 @@ +ffffffff000007ff0000000100000000 +0000000200000001fffff80000000000 +fffff801000000010000000000000800 +fffffffe000007fe00000000ffffffff +800000007ffffffffffff7ffffffffff +7ffff7ff7fffffff7ffffffe800007fe +7fffffff800007ff8000000180000000 +0000abce0000abcd7ffff80080000000 +0000abd20000abd10000abd00000abcf +0000000100000000000000000000abd3 +36925814369258143692581436925814 diff --git a/src/test/cpp/regression/I-AND-01.out32 b/src/test/cpp/regression/I-AND-01.out32 new file mode 100644 index 0000000..36062e1 --- /dev/null +++ b/src/test/cpp/regression/I-AND-01.out32 @@ -0,0 +1,11 @@ +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000100000001 +ffffffff0000000100000000ffffffff +000000007fffffff800000007fffffff +000000007fffffff7fffffff00000001 +80000000000000000000000080000000 +abcdffff0000007f8000000000000000 +0000000f0000001f0000003f0000007f +00000000000000000000000300000007 +36925814369258143692581400000000 diff --git a/src/test/cpp/regression/I-ANDI-01.out32 b/src/test/cpp/regression/I-ANDI-01.out32 new file mode 100644 index 0000000..678ea1b --- /dev/null +++ b/src/test/cpp/regression/I-ANDI-01.out32 @@ -0,0 +1,11 @@ +00000000000000000000000000000000 +00000001000000010000000000000000 +00000000000000000000000100000001 +ffffffff000007ff00000001ffffffff +000000017ffffffffffff80000000000 +7ffff800000000007fffffff000007ff +80000000000000000000000080000000 +0000007fabcdffff8000000000000000 +000000070000000f0000001f0000003f +00000000000000000000000000000003 +36925814369258143692581436925814 diff --git a/src/test/cpp/regression/I-AUIPC-01.out32 b/src/test/cpp/regression/I-AUIPC-01.out32 new file mode 100644 index 0000000..aed7e49 --- /dev/null +++ b/src/test/cpp/regression/I-AUIPC-01.out32 @@ -0,0 +1,4 @@ +00000000000000000000000000000000 +00000000000000000000000000000000 +00000000000000000000000000000000 +00000000000000000000000000000000 diff --git a/src/test/cpp/regression/I-BEQ-01.out32 b/src/test/cpp/regression/I-BEQ-01.out32 new file mode 100644 index 0000000..55bcb00 --- /dev/null +++ b/src/test/cpp/regression/I-BEQ-01.out32 @@ -0,0 +1,10 @@ +ffffffff000000010000000000000000 +000000010000001e800000007fffffff +7fffffffffffffff0000000100000000 +00000000ffffffff0000001d80000000 +800000007fffffffffffffff00000001 +00000001000000007fffffff0000001b +00000017800000007fffffffffffffff +ffffffff000000010000000080000000 +000003de0000000f800000007fffffff +0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-BGE-01.out32 b/src/test/cpp/regression/I-BGE-01.out32 new file mode 100644 index 0000000..4d90737 --- /dev/null +++ b/src/test/cpp/regression/I-BGE-01.out32 @@ -0,0 +1,10 @@ +ffffffff000000010000000000000000 +000000010000000a800000007fffffff +7fffffffffffffff0000000100000000 +00000000ffffffff0000000880000000 +800000007fffffffffffffff00000001 +00000001000000007fffffff0000000b +00000000800000007fffffffffffffff +ffffffff000000010000000080000000 +000001540000000f800000007fffffff +0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-BGEU-01.out32 b/src/test/cpp/regression/I-BGEU-01.out32 new file mode 100644 index 0000000..ec77619 --- /dev/null +++ b/src/test/cpp/regression/I-BGEU-01.out32 @@ -0,0 +1,10 @@ +ffffffff000000010000000000000000 +000000010000001e800000007fffffff +7fffffffffffffff0000000100000000 +00000000ffffffff0000001c80000000 +800000007fffffffffffffff00000001 +00000001000000007fffffff00000000 +00000014800000007fffffffffffffff +ffffffff000000010000000080000000 +000003c000000004800000007fffffff +0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-BLT-01.out32 b/src/test/cpp/regression/I-BLT-01.out32 new file mode 100644 index 0000000..81618ad --- /dev/null +++ b/src/test/cpp/regression/I-BLT-01.out32 @@ -0,0 +1,10 @@ +ffffffff000000010000000000000000 +0000000100000015800000007fffffff +7fffffffffffffff0000000100000000 +00000000ffffffff0000001780000000 +800000007fffffffffffffff00000001 +00000001000000007fffffff00000014 +0000001f800000007fffffffffffffff +ffffffff000000010000000080000000 +000002ab00000010800000007fffffff +0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-BLTU-01.out32 b/src/test/cpp/regression/I-BLTU-01.out32 new file mode 100644 index 0000000..d4c8e1f --- /dev/null +++ b/src/test/cpp/regression/I-BLTU-01.out32 @@ -0,0 +1,10 @@ +ffffffff000000010000000000000000 +0000000100000001800000007fffffff +7fffffffffffffff0000000100000000 +00000000ffffffff0000000380000000 +800000007fffffffffffffff00000001 +00000001000000007fffffff0000001f +0000000b800000007fffffffffffffff +ffffffff000000010000000080000000 +0000003f0000001b800000007fffffff +0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-BNE-01.out32 b/src/test/cpp/regression/I-BNE-01.out32 new file mode 100644 index 0000000..7816951 --- /dev/null +++ b/src/test/cpp/regression/I-BNE-01.out32 @@ -0,0 +1,10 @@ +ffffffff000000010000000000000000 +0000000100000001800000007fffffff +7fffffffffffffff0000000100000000 +00000000ffffffff0000000280000000 +800000007fffffffffffffff00000001 +00000001000000007fffffff00000004 +00000008800000007fffffffffffffff +ffffffff000000010000000080000000 +0000002100000010800000007fffffff +0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-CSRRC-01.out32 b/src/test/cpp/regression/I-CSRRC-01.out32 new file mode 100644 index 0000000..f72c9e7 --- /dev/null +++ b/src/test/cpp/regression/I-CSRRC-01.out32 @@ -0,0 +1,6 @@ +800f0000fffffffffffffffe00000000 +fffffffeffffffff000000007fffffff +00000000000f0000800f0000fffffffe +ffffffff00000000ffffffffedcba987 +0000000042726e6f00000000ffffffff +49c1a90369c7ad8bfffffffff7ff8818 diff --git a/src/test/cpp/regression/I-CSRRCI-01.out32 b/src/test/cpp/regression/I-CSRRCI-01.out32 new file mode 100644 index 0000000..9b6918d --- /dev/null +++ b/src/test/cpp/regression/I-CSRRCI-01.out32 @@ -0,0 +1,4 @@ +ffffffe0fffffffffffffffe00000000 +fffffffffffffffffffffff0ffffffef +ffffffe0ffffffe0fffffffefffffffe +3216549000000000ffffffffffffffe0 diff --git a/src/test/cpp/regression/I-CSRRS-01.out32 b/src/test/cpp/regression/I-CSRRS-01.out32 new file mode 100644 index 0000000..126f7b6 --- /dev/null +++ b/src/test/cpp/regression/I-CSRRS-01.out32 @@ -0,0 +1,6 @@ +7ff0ffff000000000000000100000000 +0000000100000000ffffffff80000000 +fffffffffff0ffff7ff0ffff00000001 +00000000123456780000000012345678 +0000000042726e6f0000000012345678 +b63e56fc9638527400000000f7ff8818 diff --git a/src/test/cpp/regression/I-CSRRSI-01.out32 b/src/test/cpp/regression/I-CSRRSI-01.out32 new file mode 100644 index 0000000..1957fea --- /dev/null +++ b/src/test/cpp/regression/I-CSRRSI-01.out32 @@ -0,0 +1,4 @@ +0000001f000000000000000100000000 +00000000000000000000000f00000010 +0000001f0000001f0000000100000001 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a/src/test/cpp/regression/I-EBREAK-01.out32 b/src/test/cpp/regression/I-EBREAK-01.out32 new file mode 100644 index 0000000..b6cfdac --- /dev/null +++ b/src/test/cpp/regression/I-EBREAK-01.out32 @@ -0,0 +1 @@ +00000000000000001111111100000003 diff --git a/src/test/cpp/regression/I-ECALL-01.out32 b/src/test/cpp/regression/I-ECALL-01.out32 new file mode 100644 index 0000000..ee60be8 --- /dev/null +++ b/src/test/cpp/regression/I-ECALL-01.out32 @@ -0,0 +1 @@ +0000000000000000111111110000000b diff --git a/src/test/cpp/regression/I-ENDIANESS-01.out32 b/src/test/cpp/regression/I-ENDIANESS-01.out32 new file mode 100644 index 0000000..4d78561 --- /dev/null +++ b/src/test/cpp/regression/I-ENDIANESS-01.out32 @@ -0,0 +1,2 @@ +00000089000001230000456701234567 +00000001000000230000004500000067 diff --git a/src/test/cpp/regression/I-FENCE.I-01.out32 b/src/test/cpp/regression/I-FENCE.I-01.out32 new file mode 100644 index 0000000..ce9b712 --- /dev/null +++ b/src/test/cpp/regression/I-FENCE.I-01.out32 @@ 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+000000000000000000000000f37bc400 +80000000a19080000eca864287654321 diff --git a/src/test/cpp/regression/I-SLLI-01.out32 b/src/test/cpp/regression/I-SLLI-01.out32 new file mode 100644 index 0000000..25818ac --- /dev/null +++ b/src/test/cpp/regression/I-SLLI-01.out32 @@ -0,0 +1,10 @@ +00000000000000000000000000000000 +00000002000000010000000000000000 +00010000000000018000000000008000 +80000000ffff8000fffffffeffffffff +fffffffe7fffffffffff0000ffffffff +ffff00007fffffff80000000ffff8000 +00000000000000000000000080000000 +579bde20abcdef100000000080000000 +79bde200bcdef1005e6f7880af37bc40 +000000000000000000000000f37bc400 diff --git a/src/test/cpp/regression/I-SLT-01.out32 b/src/test/cpp/regression/I-SLT-01.out32 new file mode 100644 index 0000000..ffc1108 --- /dev/null +++ b/src/test/cpp/regression/I-SLT-01.out32 @@ -0,0 +1,12 @@ +00000000000000010000000100000000 +00000000000000010000000000000000 +00000000000000000000000000000001 +000000000000000100000001ffffffff +000000007fffffff0000000000000001 +00000000000000000000000000000000 +00000001000000010000000180000000 +ffffffff000000000000000000000001 +00000000000000010000000100000001 +00000000000000000000000000000000 +00000001000000010000000000000001 +00000001000000000000000100000000 diff --git a/src/test/cpp/regression/I-SLTI-01.out32 b/src/test/cpp/regression/I-SLTI-01.out32 new file mode 100644 index 0000000..ab1cdda --- /dev/null +++ b/src/test/cpp/regression/I-SLTI-01.out32 @@ -0,0 +1,11 @@ +00000000000000010000000100000000 +00000000000000010000000000000000 +00000000000000000000000000000001 +000000000000000100000001ffffffff +000000007fffffff0000000000000001 +00000000000000000000000000000000 +00000001000000010000000180000000 +00000000ffffffff0000000100000001 +00000000000000010000000100000000 +00000001000000000000000000000000 +00000001000000000000000100000000 diff --git a/src/test/cpp/regression/I-SLTIU-01.out32 b/src/test/cpp/regression/I-SLTIU-01.out32 new file mode 100644 index 0000000..fae3854 --- /dev/null +++ b/src/test/cpp/regression/I-SLTIU-01.out32 @@ -0,0 +1,11 @@ +00000001000000010000000100000000 +00000000000000010000000100000000 +00000001000000000000000100000001 +000000000000000000000000ffffffff +000000007fffffff0000000000000000 +00000001000000000000000100000000 +00000001000000000000000080000000 +00000000000000010000000100000000 +00000001000000010000000100000000 +00000001000000000000000100000000 +00000001000000000000000100000000 diff --git a/src/test/cpp/regression/I-SLTU-01.out32 b/src/test/cpp/regression/I-SLTU-01.out32 new file mode 100644 index 0000000..aa67d8f --- /dev/null +++ b/src/test/cpp/regression/I-SLTU-01.out32 @@ -0,0 +1,12 @@ +00000001000000010000000100000000 +00000000000000010000000100000000 +00000001000000000000000100000001 +000000000000000000000000ffffffff +000000007fffffff0000000000000000 +00000001000000000000000100000000 +00000001000000000000000080000000 +00000001000000000000000000000000 +000000010000000100000001ffffffff +00000000000000000000000100000000 +00000001000000000000000000000000 +00000001000000000000000100000000 diff --git a/src/test/cpp/regression/I-SRA-01.out32 b/src/test/cpp/regression/I-SRA-01.out32 new file mode 100644 index 0000000..5338082 --- /dev/null +++ b/src/test/cpp/regression/I-SRA-01.out32 @@ -0,0 +1,11 @@ +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +ffffffffffffffffffffffffffffffff +3fffffff7fffffffffffffffffffffff +00007fff7fffffff000000000000ffff +ffffffffffff0000c000000080000000 +d5e6f788abcdef10ffff800080000000 +fd5e6f78fabcdef1f579bde2eaf37bc4 +000000000000000000000000feaf37bc +ffffffffffff0ecac3b2a19087654321 diff --git a/src/test/cpp/regression/I-SRAI-01.out32 b/src/test/cpp/regression/I-SRAI-01.out32 new file mode 100644 index 0000000..adbf5bf --- /dev/null +++ b/src/test/cpp/regression/I-SRAI-01.out32 @@ -0,0 +1,10 @@ +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +ffffffffffffffffffffffffffffffff +3fffffff7fffffffffffffffffffffff +00007fff7fffffff000000000000ffff +ffffffffffff0000c000000080000000 +d5e6f788abcdef10ffff800080000000 +fd5e6f78fabcdef1f579bde2eaf37bc4 +000000000000000000000000feaf37bc diff --git a/src/test/cpp/regression/I-SRL-01.out32 b/src/test/cpp/regression/I-SRL-01.out32 new file mode 100644 index 0000000..baa9cdf --- /dev/null +++ b/src/test/cpp/regression/I-SRL-01.out32 @@ -0,0 +1,11 @@ +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +000000010001ffff7fffffffffffffff +3fffffff7fffffff0000ffffffffffff +00007fff7fffffff000000000000ffff +00000001000100004000000080000000 +55e6f788abcdef100000800080000000 +055e6f780abcdef11579bde22af37bc4 +00000000000000000000000002af37bc +0000000100010eca43b2a19087654321 diff --git a/src/test/cpp/regression/I-SRLI-01.out32 b/src/test/cpp/regression/I-SRLI-01.out32 new file mode 100644 index 0000000..8cf21d8 --- /dev/null +++ b/src/test/cpp/regression/I-SRLI-01.out32 @@ -0,0 +1,10 @@ +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +000000010001ffff7fffffffffffffff +3fffffff7fffffff0000ffffffffffff +00007fff7fffffff000000000000ffff +00000001000100004000000080000000 +55e6f788abcdef100000800080000000 +055e6f780abcdef11579bde22af37bc4 +00000000000000000000000002af37bc diff --git a/src/test/cpp/regression/I-SUB-01.out32 b/src/test/cpp/regression/I-SUB-01.out32 new file mode 100644 index 0000000..9bd5c2f --- /dev/null +++ b/src/test/cpp/regression/I-SUB-01.out32 @@ -0,0 +1,11 @@ +00000001ffffffff0000000000000000 +00000001000000018000000080000001 +80000001800000020000000200000000 +00000000fffffffeffffffffffffffff +7fffffff7fffffff7fffffff80000000 +ffffffff00000000800000007ffffffe +800000017fffffff8000000080000000 +0000abcd000000010000000000000001 +0000abc90000abca0000abcb0000abcc +00000000000000000000abc70000abc8 +c96da7ecc96da7ec3692581400000000 diff --git a/src/test/cpp/regression/I-SW-01.out32 b/src/test/cpp/regression/I-SW-01.out32 new file mode 100644 index 0000000..7ff05bd --- /dev/null +++ b/src/test/cpp/regression/I-SW-01.out32 @@ -0,0 +1,4 @@ +f77788f855f5f666f33344f411f1f222 +0fff00f0dd0d0eee0bbbcc0c99090aaa +765432109abcdef01122334400000000 +25814963147258361472583689abcdef diff --git a/src/test/cpp/regression/I-XOR-01.out32 b/src/test/cpp/regression/I-XOR-01.out32 new file mode 100644 index 0000000..514db10 --- /dev/null +++ b/src/test/cpp/regression/I-XOR-01.out32 @@ -0,0 +1,11 @@ +ffffffff000000010000000000000000 +0000000100000001800000007fffffff +800000017ffffffefffffffe00000000 +00000000fffffffeffffffffffffffff +7fffffff7fffffff7fffffff80000000 +ffffffff00000000800000007ffffffe +7fffffff800000018000000080000000 +abcdffff0000007f00000000ffffffff +abcdffafabcdffa0abcdffbfabcdff80 +0000000000000000abcdffababcdffa8 +36925814369258143692581400000000 diff --git a/src/test/cpp/regression/I-XORI-01.out32 b/src/test/cpp/regression/I-XORI-01.out32 new file mode 100644 index 0000000..dd8c914 --- /dev/null +++ b/src/test/cpp/regression/I-XORI-01.out32 @@ -0,0 +1,11 @@ +ffffffff000007ff0000000100000000 +0000000000000001fffff80000000000 +fffff80100000001fffffffe000007fe +00000000fffff800fffffffeffffffff +7ffffffe7fffffff000007ffffffffff +800007ff7fffffff800000007ffff800 +7fffffff800007ff8000000180000000 +abcdff80abcdffff7ffff80080000000 +abcdffa8abcdffafabcdffa0abcdffbf +000000010000000000000000abcdffab +36925814369258143692581436925814 diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 012680c..28dec0b 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -379,7 +379,11 @@ public: case 0x37:rfWrite(rd32, i & 0xFFFFF000);pcWrite(pc + 4);break; // LUI case 0x17:rfWrite(rd32, (i & 0xFFFFF000) + pc);pcWrite(pc + 4);break; //AUIPC case 0x6F:rfWrite(rd32, pc + 4);pcWrite(pc + (iBits(21, 10) << 1) + (iBits(20, 1) << 11) + (iBits(12, 8) << 12) + (iSign() << 20));break; //JAL - case 0x67:rfWrite(rd32, pc + 4);pcWrite((i32_rs1 + i32_i_imm) & ~1);break; //JALR + case 0x67:{ + uint32_t target = (i32_rs1 + i32_i_imm) & ~1; + rfWrite(rd32, pc + 4); + pcWrite(target); + } break; //JALR case 0x63: switch ((i >> 12) & 0x7) { case 0x0:if (i32_rs1 == i32_rs2)pcWrite(pc + i32_sb_imm);else pcWrite(pc + 4);break; @@ -682,7 +686,9 @@ public: switch(periphWrites.empty() + uint32_t(periphWritesGolden.empty())*2){ case 3: periphWriteTimer = 0; break; - case 1: case 2: if(periphWriteTimer++ == 20){ cout << "periphWrite timout" << endl; fail();} break; + case 1: case 2: if(periphWriteTimer++ == 20){ + cout << "periphWrite timout" << endl; fail(); + } break; case 0: MemWrite t = periphWrites.front(); MemWrite t2 = periphWritesGolden.front(); @@ -692,6 +698,7 @@ public: } periphWrites.pop(); periphWritesGolden.pop(); + periphWriteTimer = 0; break; } @@ -2069,6 +2076,60 @@ public: } }; +class Compliance : public Workspace{ +public: + string name; + ofstream out32; + int out32Counter = 0; + Compliance(string name) : Workspace(name) { + //withRiscvRef(); + loadHex("../../resources/hex/" + name + ".elf.hex"); + out32.open (name + ".out32"); + this->name = name; + if(name == "I-FENCE.I-01") withInstructionReadCheck = false; + } + + + virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) { + Workspace::dBusAccess(addr,wr,size,mask,data,error); + if(wr && addr == 0xF00FFF2C){ + out32 << hex << setw(8) << std::setfill('0') << *data; + if(++out32Counter % 4 == 0) out32 << "\r\n"; + *error = 0; + } + } + + virtual void checks(){ + + } + + + + virtual void pass(){ + FILE *refFile = fopen((string("../../resources/ref/") + name + ".reference_output").c_str(), "r"); + fseek(refFile, 0, SEEK_END); + uint32_t refSize = ftell(refFile); + fseek(refFile, 0, SEEK_SET); + char* ref = new char[refSize]; + fread(ref, 1, refSize, refFile); + + + out32.flush(); + FILE *logFile = fopen((name + ".out32").c_str(), "r"); + fseek(logFile, 0, SEEK_END); + uint32_t logSize = ftell(logFile); + fseek(logFile, 0, SEEK_SET); + char* log = new char[logSize]; + fread(log, 1, logSize, logFile); + + if(refSize > logSize || memcmp(log,ref,refSize)) + fail(); + else + Workspace::pass(); + } +}; + + #ifdef DEBUG_PLUGIN #include @@ -2331,6 +2392,66 @@ string freeRtosTests[] = { }; + +string riscvComplianceMain[] = { + "I-LB-01", + "I-LBU-01", + "I-LH-01", + "I-LHU-01", + "I-LW-01", + "I-SB-01", + "I-SH-01", + "I-SW-01", + "I-NOP-01", + "I-LUI-01", + "I-ADD-01", + "I-ADDI-01", + "I-AND-01", + "I-ANDI-01", + "I-SUB-01", + "I-OR-01", + "I-ORI-01", + "I-XOR-01", + "I-XORI-01", + "I-SRA-01", + "I-SRAI-01", + "I-SRL-01", + "I-SRLI-01", + "I-SLL-01", + "I-SLLI-01", + "I-SLT-01", + "I-SLTI-01", + "I-SLTIU-01", + "I-SLTU-01", + "I-AUIPC-01", + "I-BEQ-01", + "I-BGE-01", + "I-BGEU-01", + "I-BLT-01", + "I-BLTU-01", + "I-BNE-01", + "I-JAL-01", + "I-JALR-01", + "I-CSRRC-01", + "I-CSRRCI-01", + "I-CSRRS-01", + "I-CSRRSI-01", + "I-CSRRW-01", + "I-CSRRWI-01", + "I-DELAY_SLOTS-01", + "I-EBREAK-01", + "I-ECALL-01", + "I-ENDIANESS-01", + "I-FENCE.I-01", + "I-IO", + "I-MISALIGN_JMP-01", + "I-MISALIGN_LDST-01", + "I-RF_size-01", + "I-RF_width-01", + "I-RF_x0-01", + +}; + struct timespec timer_start(){ struct timespec start_time; clock_gettime(CLOCK_REALTIME, &start_time); //CLOCK_PROCESS_CPUTIME_ID @@ -2420,7 +2541,9 @@ int main(int argc, char **argv, char **env) { #ifdef ISA_TEST // redo(REDO,TestA().run();) - + for(const string &name : riscvComplianceMain){ + redo(REDO, Compliance(name).run();) + } for(const string &name : riscvTestMain){ diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile index 3a5c8f3..03cca7d 100644 --- a/src/test/cpp/regression/makefile +++ b/src/test/cpp/regression/makefile @@ -1,4 +1,4 @@ -DEBUG=yes +DEBUG?=no IBUS?=CACHED DBUS?=CACHED diff --git a/src/test/resources/asm/I-ADD-01.elf.objdump b/src/test/resources/asm/I-ADD-01.elf.objdump new file mode 100644 index 0000000..0da0b8d --- /dev/null +++ b/src/test/resources/asm/I-ADD-01.elf.objdump @@ -0,0 +1,344 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-ADD-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef1f> +80000028: 80000437 lui s0,0x80000 +8000002c: 00418233 add tp,gp,tp +80000030: 005182b3 add t0,gp,t0 +80000034: 00618333 add t1,gp,t1 +80000038: 007183b3 add t2,gp,t2 +8000003c: 00818433 add s0,gp,s0 +80000040: 00312023 sw gp,0(sp) +80000044: 00412223 sw tp,4(sp) +80000048: 00512423 sw t0,8(sp) +8000004c: 00612623 sw t1,12(sp) +80000050: 00712823 sw t2,16(sp) +80000054: 00812a23 sw s0,20(sp) +80000058: 00001097 auipc ra,0x1 +8000005c: fac08093 addi ra,ra,-84 # 80001004 +80000060: 00001117 auipc sp,0x1 +80000064: fe810113 addi sp,sp,-24 # 80001048 +80000068: 0000a403 lw s0,0(ra) +8000006c: 00000493 li s1,0 +80000070: 00100513 li a0,1 +80000074: fff00593 li a1,-1 +80000078: 80000637 lui a2,0x80000 +8000007c: fff60613 addi a2,a2,-1 # 7fffffff <_end+0xffffef1f> +80000080: 800006b7 lui a3,0x80000 +80000084: 009404b3 add s1,s0,s1 +80000088: 00a40533 add a0,s0,a0 +8000008c: 00b405b3 add a1,s0,a1 +80000090: 00c40633 add a2,s0,a2 +80000094: 00d406b3 add a3,s0,a3 +80000098: 00812023 sw s0,0(sp) +8000009c: 00912223 sw s1,4(sp) +800000a0: 00a12423 sw a0,8(sp) +800000a4: 00b12623 sw a1,12(sp) +800000a8: 00c12823 sw a2,16(sp) +800000ac: 00d12a23 sw a3,20(sp) +800000b0: 00001097 auipc ra,0x1 +800000b4: f5808093 addi ra,ra,-168 # 80001008 +800000b8: 00001117 auipc sp,0x1 +800000bc: fa810113 addi sp,sp,-88 # 80001060 +800000c0: 0000a683 lw a3,0(ra) +800000c4: 00000713 li a4,0 +800000c8: 00100793 li a5,1 +800000cc: fff00813 li a6,-1 +800000d0: 800008b7 lui a7,0x80000 +800000d4: fff88893 addi a7,a7,-1 # 7fffffff <_end+0xffffef1f> +800000d8: 80000937 lui s2,0x80000 +800000dc: 00e68733 add a4,a3,a4 +800000e0: 00f687b3 add a5,a3,a5 +800000e4: 01068833 add a6,a3,a6 +800000e8: 011688b3 add a7,a3,a7 +800000ec: 01268933 add s2,a3,s2 +800000f0: 00d12023 sw a3,0(sp) +800000f4: 00e12223 sw a4,4(sp) +800000f8: 00f12423 sw a5,8(sp) +800000fc: 01012623 sw a6,12(sp) +80000100: 01112823 sw a7,16(sp) +80000104: 01212a23 sw s2,20(sp) +80000108: 00001097 auipc ra,0x1 +8000010c: f0408093 addi ra,ra,-252 # 8000100c +80000110: 00001117 auipc sp,0x1 +80000114: f6810113 addi sp,sp,-152 # 80001078 +80000118: 0000a903 lw s2,0(ra) +8000011c: 00000993 li s3,0 +80000120: 00100a13 li s4,1 +80000124: fff00a93 li s5,-1 +80000128: 80000b37 lui s6,0x80000 +8000012c: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef1f> +80000130: 80000bb7 lui s7,0x80000 +80000134: 013909b3 add s3,s2,s3 +80000138: 01490a33 add s4,s2,s4 +8000013c: 01590ab3 add s5,s2,s5 +80000140: 01690b33 add s6,s2,s6 +80000144: 01790bb3 add s7,s2,s7 +80000148: 01212023 sw s2,0(sp) +8000014c: 01312223 sw s3,4(sp) +80000150: 01412423 sw s4,8(sp) +80000154: 01512623 sw s5,12(sp) +80000158: 01612823 sw s6,16(sp) +8000015c: 01712a23 sw s7,20(sp) +80000160: 00001097 auipc ra,0x1 +80000164: eb008093 addi ra,ra,-336 # 80001010 +80000168: 00001117 auipc sp,0x1 +8000016c: f2810113 addi sp,sp,-216 # 80001090 +80000170: 0000ab83 lw s7,0(ra) +80000174: 00000c13 li s8,0 +80000178: 00100c93 li s9,1 +8000017c: fff00d13 li s10,-1 +80000180: 80000db7 lui s11,0x80000 +80000184: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef1f> +80000188: 80000e37 lui t3,0x80000 +8000018c: 018b8c33 add s8,s7,s8 +80000190: 019b8cb3 add s9,s7,s9 +80000194: 01ab8d33 add s10,s7,s10 +80000198: 01bb8db3 add s11,s7,s11 +8000019c: 01cb8e33 add t3,s7,t3 +800001a0: 01712023 sw s7,0(sp) +800001a4: 01812223 sw s8,4(sp) +800001a8: 01912423 sw s9,8(sp) +800001ac: 01a12623 sw s10,12(sp) +800001b0: 01b12823 sw s11,16(sp) +800001b4: 01c12a23 sw t3,20(sp) +800001b8: 00001c97 auipc s9,0x1 +800001bc: e5cc8c93 addi s9,s9,-420 # 80001014 +800001c0: 00001d17 auipc s10,0x1 +800001c4: ee8d0d13 addi s10,s10,-280 # 800010a8 +800001c8: 000cae03 lw t3,0(s9) +800001cc: 00100d93 li s11,1 +800001d0: 01be0eb3 add t4,t3,s11 +800001d4: 01be8f33 add t5,t4,s11 +800001d8: 01bf0fb3 add t6,t5,s11 +800001dc: 01bf80b3 add ra,t6,s11 +800001e0: 01b08133 add sp,ra,s11 +800001e4: 01b101b3 add gp,sp,s11 +800001e8: 01bd2023 sw s11,0(s10) +800001ec: 01cd2223 sw t3,4(s10) +800001f0: 01dd2423 sw t4,8(s10) +800001f4: 01ed2623 sw t5,12(s10) +800001f8: 01fd2823 sw t6,16(s10) +800001fc: 001d2a23 sw ra,20(s10) +80000200: 002d2c23 sw sp,24(s10) +80000204: 003d2e23 sw gp,28(s10) +80000208: 00001097 auipc ra,0x1 +8000020c: e1008093 addi ra,ra,-496 # 80001018 +80000210: 00001117 auipc sp,0x1 +80000214: eb810113 addi sp,sp,-328 # 800010c8 +80000218: 0000ae03 lw t3,0(ra) +8000021c: f7ff9db7 lui s11,0xf7ff9 +80000220: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +80000224: 01be0033 add zero,t3,s11 +80000228: 00012023 sw zero,0(sp) +8000022c: 00001097 auipc ra,0x1 +80000230: df008093 addi ra,ra,-528 # 8000101c +80000234: 00001117 auipc sp,0x1 +80000238: e9810113 addi sp,sp,-360 # 800010cc +8000023c: 0000ae03 lw t3,0(ra) +80000240: f7ff9db7 lui s11,0xf7ff9 +80000244: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +80000248: 01be0033 add zero,t3,s11 +8000024c: 000002b3 add t0,zero,zero +80000250: 00012023 sw zero,0(sp) +80000254: 00512223 sw t0,4(sp) +80000258: 00001097 auipc ra,0x1 +8000025c: dc808093 addi ra,ra,-568 # 80001020 +80000260: 00001117 auipc sp,0x1 +80000264: e7410113 addi sp,sp,-396 # 800010d4 +80000268: 0000a183 lw gp,0(ra) +8000026c: 00018233 add tp,gp,zero +80000270: 000202b3 add t0,tp,zero +80000274: 00500333 add t1,zero,t0 +80000278: 00030733 add a4,t1,zero +8000027c: 000707b3 add a5,a4,zero +80000280: 00078833 add a6,a5,zero +80000284: 01000cb3 add s9,zero,a6 +80000288: 01900d33 add s10,zero,s9 +8000028c: 000d0db3 add s11,s10,zero +80000290: 00412023 sw tp,0(sp) +80000294: 01a12223 sw s10,4(sp) +80000298: 01b12423 sw s11,8(sp) +8000029c: 00001517 auipc a0,0x1 +800002a0: d9450513 addi a0,a0,-620 # 80001030 +800002a4: 00001597 auipc a1,0x1 +800002a8: e3c58593 addi a1,a1,-452 # 800010e0 <_end> +800002ac: f0100637 lui a2,0xf0100 +800002b0: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +800002b4 : +800002b4: 02b50663 beq a0,a1,800002e0 +800002b8: 00c52683 lw a3,12(a0) +800002bc: 00d62023 sw a3,0(a2) +800002c0: 00852683 lw a3,8(a0) +800002c4: 00d62023 sw a3,0(a2) +800002c8: 00452683 lw a3,4(a0) +800002cc: 00d62023 sw a3,0(a2) +800002d0: 00052683 lw a3,0(a0) +800002d4: 00d62023 sw a3,0(a2) +800002d8: 01050513 addi a0,a0,16 +800002dc: fd9ff06f j 800002b4 + +800002e0 : +800002e0: f0100537 lui a0,0xf0100 +800002e4: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +800002e8: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: abcd j 80001606 <_end+0x526> + ... + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 5814 lw a3,48(s0) +80001022: 3692 fld fa3,288(sp) + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff + +800010cc : +800010cc: ffff 0xffff +800010ce: ffff 0xffff +800010d0: ffff 0xffff +800010d2: ffff 0xffff + +800010d4 : +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-ADDI-01.elf.objdump b/src/test/resources/asm/I-ADDI-01.elf.objdump new file mode 100644 index 0000000..3a7b768 --- /dev/null +++ b/src/test/resources/asm/I-ADDI-01.elf.objdump @@ -0,0 +1,310 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-ADDI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00118213 addi tp,gp,1 +80000018: 7ff18293 addi t0,gp,2047 +8000001c: fff18313 addi t1,gp,-1 +80000020: 00018393 mv t2,gp +80000024: 80018413 addi s0,gp,-2048 +80000028: 00312023 sw gp,0(sp) +8000002c: 00412223 sw tp,4(sp) +80000030: 00512423 sw t0,8(sp) +80000034: 00612623 sw t1,12(sp) +80000038: 00712823 sw t2,16(sp) +8000003c: 00812a23 sw s0,20(sp) +80000040: 00001097 auipc ra,0x1 +80000044: fc408093 addi ra,ra,-60 # 80001004 +80000048: 00001117 auipc sp,0x1 +8000004c: 00010113 mv sp,sp +80000050: 0000a403 lw s0,0(ra) +80000054: 00140493 addi s1,s0,1 +80000058: 7ff40513 addi a0,s0,2047 +8000005c: fff40593 addi a1,s0,-1 +80000060: 00040613 mv a2,s0 +80000064: 80040693 addi a3,s0,-2048 +80000068: 00812023 sw s0,0(sp) # 80001048 +8000006c: 00912223 sw s1,4(sp) +80000070: 00a12423 sw a0,8(sp) +80000074: 00b12623 sw a1,12(sp) +80000078: 00c12823 sw a2,16(sp) +8000007c: 00d12a23 sw a3,20(sp) +80000080: 00001097 auipc ra,0x1 +80000084: f8808093 addi ra,ra,-120 # 80001008 +80000088: 00001117 auipc sp,0x1 +8000008c: fd810113 addi sp,sp,-40 # 80001060 +80000090: 0000a683 lw a3,0(ra) +80000094: 00168713 addi a4,a3,1 +80000098: 7ff68793 addi a5,a3,2047 +8000009c: fff68813 addi a6,a3,-1 +800000a0: 00068893 mv a7,a3 +800000a4: 80068913 addi s2,a3,-2048 +800000a8: 00d12023 sw a3,0(sp) +800000ac: 00e12223 sw a4,4(sp) +800000b0: 00f12423 sw a5,8(sp) +800000b4: 01012623 sw a6,12(sp) +800000b8: 01112823 sw a7,16(sp) +800000bc: 01212a23 sw s2,20(sp) +800000c0: 00001097 auipc ra,0x1 +800000c4: f4c08093 addi ra,ra,-180 # 8000100c +800000c8: 00001117 auipc sp,0x1 +800000cc: fb010113 addi sp,sp,-80 # 80001078 +800000d0: 0000a903 lw s2,0(ra) +800000d4: 00190993 addi s3,s2,1 +800000d8: 7ff90a13 addi s4,s2,2047 +800000dc: fff90a93 addi s5,s2,-1 +800000e0: 00090b13 mv s6,s2 +800000e4: 80090b93 addi s7,s2,-2048 +800000e8: 01212023 sw s2,0(sp) +800000ec: 01312223 sw s3,4(sp) +800000f0: 01412423 sw s4,8(sp) +800000f4: 01512623 sw s5,12(sp) +800000f8: 01612823 sw s6,16(sp) +800000fc: 01712a23 sw s7,20(sp) +80000100: 00001097 auipc ra,0x1 +80000104: f1008093 addi ra,ra,-240 # 80001010 +80000108: 00001117 auipc sp,0x1 +8000010c: f8810113 addi sp,sp,-120 # 80001090 +80000110: 0000ab83 lw s7,0(ra) +80000114: 001b8c13 addi s8,s7,1 +80000118: 7ffb8c93 addi s9,s7,2047 +8000011c: fffb8d13 addi s10,s7,-1 +80000120: 000b8d93 mv s11,s7 +80000124: 800b8e13 addi t3,s7,-2048 +80000128: 01712023 sw s7,0(sp) +8000012c: 01812223 sw s8,4(sp) +80000130: 01912423 sw s9,8(sp) +80000134: 01a12623 sw s10,12(sp) +80000138: 01b12823 sw s11,16(sp) +8000013c: 01c12a23 sw t3,20(sp) +80000140: 00001d17 auipc s10,0x1 +80000144: ed4d0d13 addi s10,s10,-300 # 80001014 +80000148: 00001d97 auipc s11,0x1 +8000014c: f60d8d93 addi s11,s11,-160 # 800010a8 +80000150: 000d2e03 lw t3,0(s10) +80000154: 001e0e93 addi t4,t3,1 +80000158: 001e8f13 addi t5,t4,1 +8000015c: 001f0f93 addi t6,t5,1 +80000160: 001f8093 addi ra,t6,1 +80000164: 00108113 addi sp,ra,1 +80000168: 00110193 addi gp,sp,1 +8000016c: 01cda023 sw t3,0(s11) +80000170: 01dda223 sw t4,4(s11) +80000174: 01eda423 sw t5,8(s11) +80000178: 01fda623 sw t6,12(s11) +8000017c: 001da823 sw ra,16(s11) +80000180: 002daa23 sw sp,20(s11) +80000184: 003dac23 sw gp,24(s11) +80000188: 00001097 auipc ra,0x1 +8000018c: e9008093 addi ra,ra,-368 # 80001018 +80000190: 00001117 auipc sp,0x1 +80000194: f3410113 addi sp,sp,-204 # 800010c4 +80000198: 0000a283 lw t0,0(ra) +8000019c: 00128013 addi zero,t0,1 +800001a0: 00012023 sw zero,0(sp) +800001a4: 00001097 auipc ra,0x1 +800001a8: e7808093 addi ra,ra,-392 # 8000101c +800001ac: 00001117 auipc sp,0x1 +800001b0: f1c10113 addi sp,sp,-228 # 800010c8 +800001b4: 0000a283 lw t0,0(ra) +800001b8: 00128013 addi zero,t0,1 +800001bc: 00100293 li t0,1 +800001c0: 00012023 sw zero,0(sp) +800001c4: 00512223 sw t0,4(sp) +800001c8: 00001097 auipc ra,0x1 +800001cc: e5808093 addi ra,ra,-424 # 80001020 +800001d0: 00001117 auipc sp,0x1 +800001d4: f0010113 addi sp,sp,-256 # 800010d0 +800001d8: 0000a183 lw gp,0(ra) +800001dc: 00018213 mv tp,gp +800001e0: 00020293 mv t0,tp +800001e4: 00028313 mv t1,t0 +800001e8: 00030713 mv a4,t1 +800001ec: 00070793 mv a5,a4 +800001f0: 00078813 mv a6,a5 +800001f4: 00080c93 mv s9,a6 +800001f8: 000c8d13 mv s10,s9 +800001fc: 000d0d93 mv s11,s10 +80000200: 00312023 sw gp,0(sp) +80000204: 00412223 sw tp,4(sp) +80000208: 01a12423 sw s10,8(sp) +8000020c: 01b12623 sw s11,12(sp) +80000210: 00001517 auipc a0,0x1 +80000214: e2050513 addi a0,a0,-480 # 80001030 +80000218: 00001597 auipc a1,0x1 +8000021c: ec858593 addi a1,a1,-312 # 800010e0 <_end> +80000220: f0100637 lui a2,0xf0100 +80000224: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +80000228 : +80000228: 02b50663 beq a0,a1,80000254 +8000022c: 00c52683 lw a3,12(a0) +80000230: 00d62023 sw a3,0(a2) +80000234: 00852683 lw a3,8(a0) +80000238: 00d62023 sw a3,0(a2) +8000023c: 00452683 lw a3,4(a0) +80000240: 00d62023 sw a3,0(a2) +80000244: 00052683 lw a3,0(a0) +80000248: 00d62023 sw a3,0(a2) +8000024c: 01050513 addi a0,a0,16 +80000250: fd9ff06f j 80000228 + +80000254 : +80000254: f0100537 lui a0,0xf0100 +80000258: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +8000025c: 00052023 sw zero,0(a0) +80000260: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: abcd j 80001606 <_end+0x526> + ... + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 5814 lw a3,48(s0) +80001022: 3692 fld fa3,288(sp) + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff + +800010c4 : +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff +800010cc: ffff 0xffff +800010ce: ffff 0xffff + +800010d0 : +800010d0: ffff 0xffff +800010d2: ffff 0xffff +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-AND-01.elf.objdump b/src/test/resources/asm/I-AND-01.elf.objdump new file mode 100644 index 0000000..1291340 --- /dev/null +++ b/src/test/resources/asm/I-AND-01.elf.objdump @@ -0,0 +1,349 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-AND-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef1f> +80000028: 80000437 lui s0,0x80000 +8000002c: 0041f233 and tp,gp,tp +80000030: 0051f2b3 and t0,gp,t0 +80000034: 0061f333 and t1,gp,t1 +80000038: 0071f3b3 and t2,gp,t2 +8000003c: 0081f433 and s0,gp,s0 +80000040: 00312023 sw gp,0(sp) +80000044: 00412223 sw tp,4(sp) +80000048: 00512423 sw t0,8(sp) +8000004c: 00612623 sw t1,12(sp) +80000050: 00712823 sw t2,16(sp) +80000054: 00812a23 sw s0,20(sp) +80000058: 00001097 auipc ra,0x1 +8000005c: fac08093 addi ra,ra,-84 # 80001004 +80000060: 00001117 auipc sp,0x1 +80000064: fe810113 addi sp,sp,-24 # 80001048 +80000068: 0000a403 lw s0,0(ra) +8000006c: 00000493 li s1,0 +80000070: 00100513 li a0,1 +80000074: fff00593 li a1,-1 +80000078: 80000637 lui a2,0x80000 +8000007c: fff60613 addi a2,a2,-1 # 7fffffff <_end+0xffffef1f> +80000080: 800006b7 lui a3,0x80000 +80000084: 009474b3 and s1,s0,s1 +80000088: 00a47533 and a0,s0,a0 +8000008c: 00b475b3 and a1,s0,a1 +80000090: 00c47633 and a2,s0,a2 +80000094: 00d476b3 and a3,s0,a3 +80000098: 00812023 sw s0,0(sp) +8000009c: 00912223 sw s1,4(sp) +800000a0: 00a12423 sw a0,8(sp) +800000a4: 00b12623 sw a1,12(sp) +800000a8: 00c12823 sw a2,16(sp) +800000ac: 00d12a23 sw a3,20(sp) +800000b0: 00001097 auipc ra,0x1 +800000b4: f5808093 addi ra,ra,-168 # 80001008 +800000b8: 00001117 auipc sp,0x1 +800000bc: fa810113 addi sp,sp,-88 # 80001060 +800000c0: 0000a683 lw a3,0(ra) +800000c4: 00000713 li a4,0 +800000c8: 00100793 li a5,1 +800000cc: fff00813 li a6,-1 +800000d0: 800008b7 lui a7,0x80000 +800000d4: fff88893 addi a7,a7,-1 # 7fffffff <_end+0xffffef1f> +800000d8: 80000937 lui s2,0x80000 +800000dc: 00e6f733 and a4,a3,a4 +800000e0: 00f6f7b3 and a5,a3,a5 +800000e4: 0106f833 and a6,a3,a6 +800000e8: 0116f8b3 and a7,a3,a7 +800000ec: 0126f933 and s2,a3,s2 +800000f0: 00d12023 sw a3,0(sp) +800000f4: 00e12223 sw a4,4(sp) +800000f8: 00f12423 sw a5,8(sp) +800000fc: 01012623 sw a6,12(sp) +80000100: 01112823 sw a7,16(sp) +80000104: 01212a23 sw s2,20(sp) +80000108: 00001097 auipc ra,0x1 +8000010c: f0408093 addi ra,ra,-252 # 8000100c +80000110: 00001117 auipc sp,0x1 +80000114: f6810113 addi sp,sp,-152 # 80001078 +80000118: 0000a903 lw s2,0(ra) +8000011c: 00000993 li s3,0 +80000120: 00100a13 li s4,1 +80000124: fff00a93 li s5,-1 +80000128: 80000b37 lui s6,0x80000 +8000012c: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef1f> +80000130: 80000bb7 lui s7,0x80000 +80000134: 013979b3 and s3,s2,s3 +80000138: 01497a33 and s4,s2,s4 +8000013c: 01597ab3 and s5,s2,s5 +80000140: 01697b33 and s6,s2,s6 +80000144: 01797bb3 and s7,s2,s7 +80000148: 01212023 sw s2,0(sp) +8000014c: 01312223 sw s3,4(sp) +80000150: 01412423 sw s4,8(sp) +80000154: 01512623 sw s5,12(sp) +80000158: 01612823 sw s6,16(sp) +8000015c: 01712a23 sw s7,20(sp) +80000160: 00001097 auipc ra,0x1 +80000164: eb008093 addi ra,ra,-336 # 80001010 +80000168: 00001117 auipc sp,0x1 +8000016c: f2810113 addi sp,sp,-216 # 80001090 +80000170: 0000ab83 lw s7,0(ra) +80000174: 00000c13 li s8,0 +80000178: 00100c93 li s9,1 +8000017c: fff00d13 li s10,-1 +80000180: 80000db7 lui s11,0x80000 +80000184: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef1f> +80000188: 80000e37 lui t3,0x80000 +8000018c: 018bfc33 and s8,s7,s8 +80000190: 019bfcb3 and s9,s7,s9 +80000194: 01abfd33 and s10,s7,s10 +80000198: 01bbfdb3 and s11,s7,s11 +8000019c: 01cbfe33 and t3,s7,t3 +800001a0: 01712023 sw s7,0(sp) +800001a4: 01812223 sw s8,4(sp) +800001a8: 01912423 sw s9,8(sp) +800001ac: 01a12623 sw s10,12(sp) +800001b0: 01b12823 sw s11,16(sp) +800001b4: 01c12a23 sw t3,20(sp) +800001b8: 00001c97 auipc s9,0x1 +800001bc: e5cc8c93 addi s9,s9,-420 # 80001014 +800001c0: 00001d17 auipc s10,0x1 +800001c4: ee8d0d13 addi s10,s10,-280 # 800010a8 +800001c8: 000cae03 lw t3,0(s9) +800001cc: 07f00213 li tp,127 +800001d0: 03f00293 li t0,63 +800001d4: 01f00313 li t1,31 +800001d8: 00f00393 li t2,15 +800001dc: 00700413 li s0,7 +800001e0: 00300493 li s1,3 +800001e4: 004e7eb3 and t4,t3,tp +800001e8: 005eff33 and t5,t4,t0 +800001ec: 006f7fb3 and t6,t5,t1 +800001f0: 007ff0b3 and ra,t6,t2 +800001f4: 0080f133 and sp,ra,s0 +800001f8: 009171b3 and gp,sp,s1 +800001fc: 004d2023 sw tp,0(s10) +80000200: 01cd2223 sw t3,4(s10) +80000204: 01dd2423 sw t4,8(s10) +80000208: 01ed2623 sw t5,12(s10) +8000020c: 01fd2823 sw t6,16(s10) +80000210: 001d2a23 sw ra,20(s10) +80000214: 002d2c23 sw sp,24(s10) +80000218: 003d2e23 sw gp,28(s10) +8000021c: 00001097 auipc ra,0x1 +80000220: dfc08093 addi ra,ra,-516 # 80001018 +80000224: 00001117 auipc sp,0x1 +80000228: ea410113 addi sp,sp,-348 # 800010c8 +8000022c: 0000ae03 lw t3,0(ra) +80000230: f7ff9db7 lui s11,0xf7ff9 +80000234: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +80000238: 01be7033 and zero,t3,s11 +8000023c: 00012023 sw zero,0(sp) +80000240: 00001097 auipc ra,0x1 +80000244: ddc08093 addi ra,ra,-548 # 8000101c +80000248: 00001117 auipc sp,0x1 +8000024c: e8410113 addi sp,sp,-380 # 800010cc +80000250: 0000ae03 lw t3,0(ra) +80000254: f7ff9db7 lui s11,0xf7ff9 +80000258: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +8000025c: 01be7033 and zero,t3,s11 +80000260: 000072b3 and t0,zero,zero +80000264: 00012023 sw zero,0(sp) +80000268: 00512223 sw t0,4(sp) +8000026c: 00001097 auipc ra,0x1 +80000270: db408093 addi ra,ra,-588 # 80001020 +80000274: 00001117 auipc sp,0x1 +80000278: e6010113 addi sp,sp,-416 # 800010d4 +8000027c: 0000a183 lw gp,0(ra) +80000280: fff00393 li t2,-1 +80000284: 0071f233 and tp,gp,t2 +80000288: 007272b3 and t0,tp,t2 +8000028c: 0053f333 and t1,t2,t0 +80000290: 00737733 and a4,t1,t2 +80000294: 007777b3 and a5,a4,t2 +80000298: 0077f833 and a6,a5,t2 +8000029c: 0103fcb3 and s9,t2,a6 +800002a0: 0193fd33 and s10,t2,s9 +800002a4: 007d7db3 and s11,s10,t2 +800002a8: 00412023 sw tp,0(sp) +800002ac: 01a12223 sw s10,4(sp) +800002b0: 01b12423 sw s11,8(sp) +800002b4: 00001517 auipc a0,0x1 +800002b8: d7c50513 addi a0,a0,-644 # 80001030 +800002bc: 00001597 auipc a1,0x1 +800002c0: e2458593 addi a1,a1,-476 # 800010e0 <_end> +800002c4: f0100637 lui a2,0xf0100 +800002c8: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +800002cc : +800002cc: 02b50663 beq a0,a1,800002f8 +800002d0: 00c52683 lw a3,12(a0) +800002d4: 00d62023 sw a3,0(a2) +800002d8: 00852683 lw a3,8(a0) +800002dc: 00d62023 sw a3,0(a2) +800002e0: 00452683 lw a3,4(a0) +800002e4: 00d62023 sw a3,0(a2) +800002e8: 00052683 lw a3,0(a0) +800002ec: 00d62023 sw a3,0(a2) +800002f0: 01050513 addi a0,a0,16 +800002f4: fd9ff06f j 800002cc + +800002f8 : +800002f8: f0100537 lui a0,0xf0100 +800002fc: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +80000300: 00052023 sw zero,0(a0) + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ffff 0xffff +80001016: abcd j 80001608 <_end+0x528> + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 5814 lw a3,48(s0) +80001022: 3692 fld fa3,288(sp) + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff + +800010cc : +800010cc: ffff 0xffff +800010ce: ffff 0xffff +800010d0: ffff 0xffff +800010d2: ffff 0xffff + +800010d4 : +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-ANDI-01.elf.objdump b/src/test/resources/asm/I-ANDI-01.elf.objdump new file mode 100644 index 0000000..e3b8126 --- /dev/null +++ b/src/test/resources/asm/I-ANDI-01.elf.objdump @@ -0,0 +1,310 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-ANDI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 0011f213 andi tp,gp,1 +80000018: 7ff1f293 andi t0,gp,2047 +8000001c: fff1f313 andi t1,gp,-1 +80000020: 0001f393 andi t2,gp,0 +80000024: 8001f413 andi s0,gp,-2048 +80000028: 00312023 sw gp,0(sp) +8000002c: 00412223 sw tp,4(sp) +80000030: 00512423 sw t0,8(sp) +80000034: 00612623 sw t1,12(sp) +80000038: 00712823 sw t2,16(sp) +8000003c: 00812a23 sw s0,20(sp) +80000040: 00001097 auipc ra,0x1 +80000044: fc408093 addi ra,ra,-60 # 80001004 +80000048: 00001117 auipc sp,0x1 +8000004c: 00010113 mv sp,sp +80000050: 0000a403 lw s0,0(ra) +80000054: 00147493 andi s1,s0,1 +80000058: 7ff47513 andi a0,s0,2047 +8000005c: fff47593 andi a1,s0,-1 +80000060: 00047613 andi a2,s0,0 +80000064: 80047693 andi a3,s0,-2048 +80000068: 00812023 sw s0,0(sp) # 80001048 +8000006c: 00912223 sw s1,4(sp) +80000070: 00a12423 sw a0,8(sp) +80000074: 00b12623 sw a1,12(sp) +80000078: 00c12823 sw a2,16(sp) +8000007c: 00d12a23 sw a3,20(sp) +80000080: 00001097 auipc ra,0x1 +80000084: f8808093 addi ra,ra,-120 # 80001008 +80000088: 00001117 auipc sp,0x1 +8000008c: fd810113 addi sp,sp,-40 # 80001060 +80000090: 0000a683 lw a3,0(ra) +80000094: 0016f713 andi a4,a3,1 +80000098: 7ff6f793 andi a5,a3,2047 +8000009c: fff6f813 andi a6,a3,-1 +800000a0: 0006f893 andi a7,a3,0 +800000a4: 8006f913 andi s2,a3,-2048 +800000a8: 00d12023 sw a3,0(sp) +800000ac: 00e12223 sw a4,4(sp) +800000b0: 00f12423 sw a5,8(sp) +800000b4: 01012623 sw a6,12(sp) +800000b8: 01112823 sw a7,16(sp) +800000bc: 01212a23 sw s2,20(sp) +800000c0: 00001097 auipc ra,0x1 +800000c4: f4c08093 addi ra,ra,-180 # 8000100c +800000c8: 00001117 auipc sp,0x1 +800000cc: fb010113 addi sp,sp,-80 # 80001078 +800000d0: 0000a903 lw s2,0(ra) +800000d4: 00197993 andi s3,s2,1 +800000d8: 7ff97a13 andi s4,s2,2047 +800000dc: fff97a93 andi s5,s2,-1 +800000e0: 00097b13 andi s6,s2,0 +800000e4: 80097b93 andi s7,s2,-2048 +800000e8: 01212023 sw s2,0(sp) +800000ec: 01312223 sw s3,4(sp) +800000f0: 01412423 sw s4,8(sp) +800000f4: 01512623 sw s5,12(sp) +800000f8: 01612823 sw s6,16(sp) +800000fc: 01712a23 sw s7,20(sp) +80000100: 00001097 auipc ra,0x1 +80000104: f1008093 addi ra,ra,-240 # 80001010 +80000108: 00001117 auipc sp,0x1 +8000010c: f8810113 addi sp,sp,-120 # 80001090 +80000110: 0000ab83 lw s7,0(ra) +80000114: 001bfc13 andi s8,s7,1 +80000118: 7ffbfc93 andi s9,s7,2047 +8000011c: fffbfd13 andi s10,s7,-1 +80000120: 000bfd93 andi s11,s7,0 +80000124: 800bfe13 andi t3,s7,-2048 +80000128: 01712023 sw s7,0(sp) +8000012c: 01812223 sw s8,4(sp) +80000130: 01912423 sw s9,8(sp) +80000134: 01a12623 sw s10,12(sp) +80000138: 01b12823 sw s11,16(sp) +8000013c: 01c12a23 sw t3,20(sp) +80000140: 00001d17 auipc s10,0x1 +80000144: ed4d0d13 addi s10,s10,-300 # 80001014 +80000148: 00001d97 auipc s11,0x1 +8000014c: f60d8d93 addi s11,s11,-160 # 800010a8 +80000150: 000d2e03 lw t3,0(s10) +80000154: 07fe7e93 andi t4,t3,127 +80000158: 03feff13 andi t5,t4,63 +8000015c: 01ff7f93 andi t6,t5,31 +80000160: 00fff093 andi ra,t6,15 +80000164: 0070f113 andi sp,ra,7 +80000168: 00317193 andi gp,sp,3 +8000016c: 01cda023 sw t3,0(s11) +80000170: 01dda223 sw t4,4(s11) +80000174: 01eda423 sw t5,8(s11) +80000178: 01fda623 sw t6,12(s11) +8000017c: 001da823 sw ra,16(s11) +80000180: 002daa23 sw sp,20(s11) +80000184: 003dac23 sw gp,24(s11) +80000188: 00001097 auipc ra,0x1 +8000018c: e9008093 addi ra,ra,-368 # 80001018 +80000190: 00001117 auipc sp,0x1 +80000194: f3410113 addi sp,sp,-204 # 800010c4 +80000198: 0000a283 lw t0,0(ra) +8000019c: 0012f013 andi zero,t0,1 +800001a0: 00012023 sw zero,0(sp) +800001a4: 00001097 auipc ra,0x1 +800001a8: e7808093 addi ra,ra,-392 # 8000101c +800001ac: 00001117 auipc sp,0x1 +800001b0: f1c10113 addi sp,sp,-228 # 800010c8 +800001b4: 0000a283 lw t0,0(ra) +800001b8: 0012f013 andi zero,t0,1 +800001bc: 00107293 andi t0,zero,1 +800001c0: 00012023 sw zero,0(sp) +800001c4: 00512223 sw t0,4(sp) +800001c8: 00001097 auipc ra,0x1 +800001cc: e5808093 addi ra,ra,-424 # 80001020 +800001d0: 00001117 auipc sp,0x1 +800001d4: f0010113 addi sp,sp,-256 # 800010d0 +800001d8: 0000a183 lw gp,0(ra) +800001dc: fff1f213 andi tp,gp,-1 +800001e0: fff27293 andi t0,tp,-1 +800001e4: fff2f313 andi t1,t0,-1 +800001e8: fff37713 andi a4,t1,-1 +800001ec: fff77793 andi a5,a4,-1 +800001f0: fff7f813 andi a6,a5,-1 +800001f4: fff87c93 andi s9,a6,-1 +800001f8: fffcfd13 andi s10,s9,-1 +800001fc: fffd7d93 andi s11,s10,-1 +80000200: 00312023 sw gp,0(sp) +80000204: 00412223 sw tp,4(sp) +80000208: 01a12423 sw s10,8(sp) +8000020c: 01b12623 sw s11,12(sp) +80000210: 00001517 auipc a0,0x1 +80000214: e2050513 addi a0,a0,-480 # 80001030 +80000218: 00001597 auipc a1,0x1 +8000021c: ec858593 addi a1,a1,-312 # 800010e0 <_end> +80000220: f0100637 lui a2,0xf0100 +80000224: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +80000228 : +80000228: 02b50663 beq a0,a1,80000254 +8000022c: 00c52683 lw a3,12(a0) +80000230: 00d62023 sw a3,0(a2) +80000234: 00852683 lw a3,8(a0) +80000238: 00d62023 sw a3,0(a2) +8000023c: 00452683 lw a3,4(a0) +80000240: 00d62023 sw a3,0(a2) +80000244: 00052683 lw a3,0(a0) +80000248: 00d62023 sw a3,0(a2) +8000024c: 01050513 addi a0,a0,16 +80000250: fd9ff06f j 80000228 + +80000254 : +80000254: f0100537 lui a0,0xf0100 +80000258: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +8000025c: 00052023 sw zero,0(a0) +80000260: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ffff 0xffff +80001016: abcd j 80001608 <_end+0x528> + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 5814 lw a3,48(s0) +80001022: 3692 fld fa3,288(sp) + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff + +800010c4 : +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff +800010cc: ffff 0xffff +800010ce: ffff 0xffff + +800010d0 : +800010d0: ffff 0xffff +800010d2: ffff 0xffff +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-AUIPC-01.elf.objdump b/src/test/resources/asm/I-AUIPC-01.elf.objdump new file mode 100644 index 0000000..a10de4b --- /dev/null +++ b/src/test/resources/asm/I-AUIPC-01.elf.objdump @@ -0,0 +1,205 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-AUIPC-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001717 auipc a4,0x1 +80000004: 00070713 mv a4,a4 +80000008: 00001797 auipc a5,0x1 +8000000c: 01878793 addi a5,a5,24 # 80001020 +80000010: 00072083 lw ra,0(a4) # 80001000 +80000014: 00001137 lui sp,0x1 +80000018: 00410113 addi sp,sp,4 # 1004 <_start-0x7fffeffc> +8000001c: fffff1b7 lui gp,0xfffff +80000020: 00818193 addi gp,gp,8 # fffff008 <_end+0x7fffdfa8> +80000024: 7ffff237 lui tp,0x7ffff +80000028: 00c20213 addi tp,tp,12 # 7ffff00c <_start-0xff4> +8000002c: 800002b7 lui t0,0x80000 +80000030: 01028293 addi t0,t0,16 # 80000010 <_end+0xffffefb0> +80000034: 00208133 add sp,ra,sp +80000038: 003081b3 add gp,ra,gp +8000003c: 00408233 add tp,ra,tp +80000040: 005082b3 add t0,ra,t0 + +80000044 : +80000044: 00000317 auipc t1,0x0 +80000048: 00001397 auipc t2,0x1 +8000004c: fffff817 auipc a6,0xfffff +80000050: 7ffffe97 auipc t4,0x7ffff +80000054: 80000f97 auipc t6,0x80000 +80000058: 00134333 xor t1,t1,ra +8000005c: 0023c3b3 xor t2,t2,sp +80000060: 00384833 xor a6,a6,gp +80000064: 004eceb3 xor t4,t4,tp +80000068: 005fcfb3 xor t6,t6,t0 +8000006c: 0067a023 sw t1,0(a5) +80000070: 0077a223 sw t2,4(a5) +80000074: 0107a423 sw a6,8(a5) +80000078: 01d7a623 sw t4,12(a5) +8000007c: 01f7a823 sw t6,16(a5) +80000080: 00001897 auipc a7,0x1 +80000084: f8488893 addi a7,a7,-124 # 80001004 +80000088: 00001817 auipc a6,0x1 +8000008c: fac80813 addi a6,a6,-84 # 80001034 +80000090: 111110b7 lui ra,0x11111 +80000094: 11108093 addi ra,ra,273 # 11111111 <_start-0x6eeeeeef> +80000098: 22222137 lui sp,0x22222 +8000009c: 22210113 addi sp,sp,546 # 22222222 <_start-0x5dddddde> +800000a0: 333337b7 lui a5,0x33333 +800000a4: 33378793 addi a5,a5,819 # 33333333 <_start-0x4ccccccd> +800000a8: 44444e37 lui t3,0x44444 +800000ac: 444e0e13 addi t3,t3,1092 # 44444444 <_start-0x3bbbbbbc> +800000b0: 55555f37 lui t5,0x55555 +800000b4: 555f0f13 addi t5,t5,1365 # 55555555 <_start-0x2aaaaaab> +800000b8: 0008a183 lw gp,0(a7) +800000bc: 80000237 lui tp,0x80000 +800000c0: 7ffff2b7 lui t0,0x7ffff +800000c4: 00428293 addi t0,t0,4 # 7ffff004 <_start-0xffc> +800000c8: 00800313 li t1,8 +800000cc: 000013b7 lui t2,0x1 +800000d0: 00c38393 addi t2,t2,12 # 100c <_start-0x7fffeff4> +800000d4: fffff437 lui s0,0xfffff +800000d8: 01040413 addi s0,s0,16 # fffff010 <_end+0x7fffdfb0> +800000dc: 00418233 add tp,gp,tp +800000e0: 005182b3 add t0,gp,t0 +800000e4: 00618333 add t1,gp,t1 +800000e8: 007183b3 add t2,gp,t2 +800000ec: 00818433 add s0,gp,s0 + +800000f0 : +800000f0: 80000097 auipc ra,0x80000 +800000f4: 7ffff117 auipc sp,0x7ffff +800000f8: 00000797 auipc a5,0x0 +800000fc: 00001e17 auipc t3,0x1 +80000100: ffffff17 auipc t5,0xfffff +80000104: 0040c0b3 xor ra,ra,tp +80000108: 00514133 xor sp,sp,t0 +8000010c: 0067c7b3 xor a5,a5,t1 +80000110: 007e4e33 xor t3,t3,t2 +80000114: 008f4f33 xor t5,t5,s0 +80000118: 00182023 sw ra,0(a6) +8000011c: 00282223 sw sp,4(a6) +80000120: 00f82423 sw a5,8(a6) +80000124: 01c82623 sw t3,12(a6) +80000128: 01e82823 sw t5,16(a6) +8000012c: 00001917 auipc s2,0x1 +80000130: edc90913 addi s2,s2,-292 # 80001008 +80000134: 00001897 auipc a7,0x1 +80000138: f1488893 addi a7,a7,-236 # 80001048 + +8000013c : +8000013c: 00092083 lw ra,0(s2) +80000140: 00492103 lw sp,4(s2) +80000144: 00892183 lw gp,8(s2) +80000148: 00000217 auipc tp,0x0 +8000014c: ff420213 addi tp,tp,-12 # 8000013c +80000150: 00000797 auipc a5,0x0 +80000154: 01878793 addi a5,a5,24 # 80000168 +80000158: 00000f17 auipc t5,0x0 +8000015c: 040f0f13 addi t5,t5,64 # 80000198 +80000160: 00000297 auipc t0,0x0 +80000164: fdc28293 addi t0,t0,-36 # 8000013c + +80000168 : +80000168: 00000817 auipc a6,0x0 +8000016c: 00080813 mv a6,a6 +80000170: 00000f97 auipc t6,0x0 +80000174: 028f8f93 addi t6,t6,40 # 80000198 +80000178: 00124233 xor tp,tp,ra +8000017c: 0027c7b3 xor a5,a5,sp +80000180: 003f4f33 xor t5,t5,gp +80000184: 401282b3 sub t0,t0,ra +80000188: 00284833 xor a6,a6,sp +8000018c: 003fcfb3 xor t6,t6,gp +80000190: 0048a023 sw tp,0(a7) +80000194: 00f8a223 sw a5,4(a7) + +80000198 : +80000198: 01e8a423 sw t5,8(a7) +8000019c: 0058a623 sw t0,12(a7) +800001a0: 0108a823 sw a6,16(a7) +800001a4: 01f8aa23 sw t6,20(a7) +800001a8: 00001517 auipc a0,0x1 +800001ac: e7850513 addi a0,a0,-392 # 80001020 +800001b0: 00001597 auipc a1,0x1 +800001b4: eb058593 addi a1,a1,-336 # 80001060 <_end> +800001b8: f0100637 lui a2,0xf0100 +800001bc: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feecc> + +800001c0 : +800001c0: 02b50663 beq a0,a1,800001ec +800001c4: 00c52683 lw a3,12(a0) +800001c8: 00d62023 sw a3,0(a2) +800001cc: 00852683 lw a3,8(a0) +800001d0: 00d62023 sw a3,0(a2) +800001d4: 00452683 lw a3,4(a0) +800001d8: 00d62023 sw a3,0(a2) +800001dc: 00052683 lw a3,0(a0) +800001e0: 00d62023 sw a3,0(a2) +800001e4: 01050513 addi a0,a0,16 +800001e8: fd9ff06f j 800001c0 + +800001ec : +800001ec: f0100537 lui a0,0xf0100 +800001f0: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feec0> +800001f4: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0044 addi s1,sp,4 +80001002: 8000 0x8000 + +80001004 : +80001004: 00f0 addi a2,sp,76 +80001006: 8000 0x8000 + +80001008 : +80001008: 013c addi a5,sp,136 +8000100a: 8000 0x8000 +8000100c: 0168 addi a0,sp,140 +8000100e: 8000 0x8000 +80001010: 0198 addi a4,sp,192 +80001012: 8000 0x8000 + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff + +80001034 : +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff diff --git a/src/test/resources/asm/I-BEQ-01.elf.objdump b/src/test/resources/asm/I-BEQ-01.elf.objdump new file mode 100644 index 0000000..337a437 --- /dev/null +++ b/src/test/resources/asm/I-BEQ-01.elf.objdump @@ -0,0 +1,356 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-BEQ-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef3f> +80000028: 80000437 lui s0,0x80000 +8000002c: 00000f93 li t6,0 +80000030: 00418463 beq gp,tp,80000038 <_start+0x38> +80000034: 001fef93 ori t6,t6,1 +80000038: 00518463 beq gp,t0,80000040 <_start+0x40> +8000003c: 002fef93 ori t6,t6,2 +80000040: 00618463 beq gp,t1,80000048 <_start+0x48> +80000044: 004fef93 ori t6,t6,4 +80000048: 00718463 beq gp,t2,80000050 <_start+0x50> +8000004c: 008fef93 ori t6,t6,8 +80000050: 00818463 beq gp,s0,80000058 <_start+0x58> +80000054: 010fef93 ori t6,t6,16 +80000058: 00312023 sw gp,0(sp) +8000005c: 00412223 sw tp,4(sp) +80000060: 00512423 sw t0,8(sp) +80000064: 00612623 sw t1,12(sp) +80000068: 00712823 sw t2,16(sp) +8000006c: 00812a23 sw s0,20(sp) +80000070: 01f12c23 sw t6,24(sp) +80000074: 00001097 auipc ra,0x1 +80000078: f9008093 addi ra,ra,-112 # 80001004 +8000007c: 00001117 auipc sp,0x1 +80000080: fc010113 addi sp,sp,-64 # 8000103c +80000084: 0000a303 lw t1,0(ra) +80000088: 00000393 li t2,0 +8000008c: 00100413 li s0,1 +80000090: fff00493 li s1,-1 +80000094: 80000537 lui a0,0x80000 +80000098: fff50513 addi a0,a0,-1 # 7fffffff <_end+0xffffef3f> +8000009c: 800005b7 lui a1,0x80000 +800000a0: 00000f93 li t6,0 +800000a4: 00730463 beq t1,t2,800000ac <_start+0xac> +800000a8: 001fef93 ori t6,t6,1 +800000ac: 00830463 beq t1,s0,800000b4 <_start+0xb4> +800000b0: 002fef93 ori t6,t6,2 +800000b4: 00930463 beq t1,s1,800000bc <_start+0xbc> +800000b8: 004fef93 ori t6,t6,4 +800000bc: 00a30463 beq t1,a0,800000c4 <_start+0xc4> +800000c0: 008fef93 ori t6,t6,8 +800000c4: 00b30463 beq t1,a1,800000cc <_start+0xcc> +800000c8: 010fef93 ori t6,t6,16 +800000cc: 00612023 sw t1,0(sp) +800000d0: 00712223 sw t2,4(sp) +800000d4: 00812423 sw s0,8(sp) +800000d8: 00912623 sw s1,12(sp) +800000dc: 00a12823 sw a0,16(sp) +800000e0: 00b12a23 sw a1,20(sp) +800000e4: 01f12c23 sw t6,24(sp) +800000e8: 00001097 auipc ra,0x1 +800000ec: f2008093 addi ra,ra,-224 # 80001008 +800000f0: 00001117 auipc sp,0x1 +800000f4: f6810113 addi sp,sp,-152 # 80001058 +800000f8: 0000a603 lw a2,0(ra) +800000fc: 00000693 li a3,0 +80000100: 00100713 li a4,1 +80000104: fff00793 li a5,-1 +80000108: 80000837 lui a6,0x80000 +8000010c: fff80813 addi a6,a6,-1 # 7fffffff <_end+0xffffef3f> +80000110: 800008b7 lui a7,0x80000 +80000114: 00000f93 li t6,0 +80000118: 00d60463 beq a2,a3,80000120 <_start+0x120> +8000011c: 001fef93 ori t6,t6,1 +80000120: 00e60463 beq a2,a4,80000128 <_start+0x128> +80000124: 002fef93 ori t6,t6,2 +80000128: 00f60463 beq a2,a5,80000130 <_start+0x130> +8000012c: 004fef93 ori t6,t6,4 +80000130: 01060463 beq a2,a6,80000138 <_start+0x138> +80000134: 008fef93 ori t6,t6,8 +80000138: 01160463 beq a2,a7,80000140 <_start+0x140> +8000013c: 010fef93 ori t6,t6,16 +80000140: 00c12023 sw a2,0(sp) +80000144: 00d12223 sw a3,4(sp) +80000148: 00e12423 sw a4,8(sp) +8000014c: 00f12623 sw a5,12(sp) +80000150: 01012823 sw a6,16(sp) +80000154: 01112a23 sw a7,20(sp) +80000158: 01f12c23 sw t6,24(sp) +8000015c: 00001097 auipc ra,0x1 +80000160: eb008093 addi ra,ra,-336 # 8000100c +80000164: 00001117 auipc sp,0x1 +80000168: f1010113 addi sp,sp,-240 # 80001074 +8000016c: 0000a903 lw s2,0(ra) +80000170: 00000993 li s3,0 +80000174: 00100a13 li s4,1 +80000178: fff00a93 li s5,-1 +8000017c: 80000b37 lui s6,0x80000 +80000180: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef3f> +80000184: 80000bb7 lui s7,0x80000 +80000188: 00000f93 li t6,0 +8000018c: 01390463 beq s2,s3,80000194 <_start+0x194> +80000190: 001fef93 ori t6,t6,1 +80000194: 01490463 beq s2,s4,8000019c <_start+0x19c> +80000198: 002fef93 ori t6,t6,2 +8000019c: 01590463 beq s2,s5,800001a4 <_start+0x1a4> +800001a0: 004fef93 ori t6,t6,4 +800001a4: 01690463 beq s2,s6,800001ac <_start+0x1ac> +800001a8: 008fef93 ori t6,t6,8 +800001ac: 01790463 beq s2,s7,800001b4 <_start+0x1b4> +800001b0: 010fef93 ori t6,t6,16 +800001b4: 01212023 sw s2,0(sp) +800001b8: 01312223 sw s3,4(sp) +800001bc: 01412423 sw s4,8(sp) +800001c0: 01512623 sw s5,12(sp) +800001c4: 01612823 sw s6,16(sp) +800001c8: 01712a23 sw s7,20(sp) +800001cc: 01f12c23 sw t6,24(sp) +800001d0: 00001097 auipc ra,0x1 +800001d4: e4008093 addi ra,ra,-448 # 80001010 +800001d8: 00001117 auipc sp,0x1 +800001dc: eb810113 addi sp,sp,-328 # 80001090 +800001e0: 0000ac03 lw s8,0(ra) +800001e4: 00000c93 li s9,0 +800001e8: 00100d13 li s10,1 +800001ec: fff00d93 li s11,-1 +800001f0: 80000e37 lui t3,0x80000 +800001f4: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef3f> +800001f8: 80000eb7 lui t4,0x80000 +800001fc: 00000f93 li t6,0 +80000200: 019c0463 beq s8,s9,80000208 <_start+0x208> +80000204: 001fef93 ori t6,t6,1 +80000208: 01ac0463 beq s8,s10,80000210 <_start+0x210> +8000020c: 002fef93 ori t6,t6,2 +80000210: 01bc0463 beq s8,s11,80000218 <_start+0x218> +80000214: 004fef93 ori t6,t6,4 +80000218: 01cc0463 beq s8,t3,80000220 <_start+0x220> +8000021c: 008fef93 ori t6,t6,8 +80000220: 01dc0463 beq s8,t4,80000228 <_start+0x228> +80000224: 010fef93 ori t6,t6,16 +80000228: 01812023 sw s8,0(sp) +8000022c: 01912223 sw s9,4(sp) +80000230: 01a12423 sw s10,8(sp) +80000234: 01b12623 sw s11,12(sp) +80000238: 01c12823 sw t3,16(sp) +8000023c: 01d12a23 sw t4,20(sp) +80000240: 01f12c23 sw t6,24(sp) +80000244: 00001d97 auipc s11,0x1 +80000248: e68d8d93 addi s11,s11,-408 # 800010ac +8000024c: 00000093 li ra,0 +80000250: 00100113 li sp,1 +80000254: fff00193 li gp,-1 +80000258: 80000237 lui tp,0x80000 +8000025c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef3f> +80000260: 800002b7 lui t0,0x80000 +80000264: 00000f93 li t6,0 +80000268: 00008463 beqz ra,80000270 <_start+0x270> +8000026c: 001fef93 ori t6,t6,1 +80000270: 00010463 beqz sp,80000278 <_start+0x278> +80000274: 002fef93 ori t6,t6,2 +80000278: 00018463 beqz gp,80000280 <_start+0x280> +8000027c: 004fef93 ori t6,t6,4 +80000280: 00020463 beqz tp,80000288 <_start+0x288> +80000284: 008fef93 ori t6,t6,8 +80000288: 00028463 beqz t0,80000290 <_start+0x290> +8000028c: 010fef93 ori t6,t6,16 +80000290: 00100463 beq zero,ra,80000298 <_start+0x298> +80000294: 020fef93 ori t6,t6,32 +80000298: 00200463 beq zero,sp,800002a0 <_start+0x2a0> +8000029c: 040fef93 ori t6,t6,64 +800002a0: 00300463 beq zero,gp,800002a8 <_start+0x2a8> +800002a4: 080fef93 ori t6,t6,128 +800002a8: 00400463 beq zero,tp,800002b0 <_start+0x2b0> +800002ac: 100fef93 ori t6,t6,256 +800002b0: 00500463 beq zero,t0,800002b8 <_start+0x2b8> +800002b4: 200fef93 ori t6,t6,512 +800002b8: 01fda023 sw t6,0(s11) +800002bc: 00001a97 auipc s5,0x1 +800002c0: d58a8a93 addi s5,s5,-680 # 80001014 +800002c4: 00001b17 auipc s6,0x1 +800002c8: decb0b13 addi s6,s6,-532 # 800010b0 +800002cc: 000aaf83 lw t6,0(s5) +800002d0: fff00113 li sp,-1 +800002d4: fff00193 li gp,-1 +800002d8: 0fedd237 lui tp,0xfedd +800002dc: ba920213 addi tp,tp,-1111 # fedcba9 <_start-0x70123457> +800002e0: 020f8463 beqz t6,80000308 <_start+0x308> +800002e4: 00000113 li sp,0 +800002e8: 00000193 li gp,0 +800002ec: 00000213 li tp,0 +800002f0: 876541b7 lui gp,0x87654 +800002f4: 32118193 addi gp,gp,801 # 87654321 <_end+0x7653261> +800002f8: 020f8463 beqz t6,80000320 <_start+0x320> +800002fc: 00000113 li sp,0 +80000300: 00000193 li gp,0 +80000304: 00000213 li tp,0 +80000308: 9abce137 lui sp,0x9abce +8000030c: ef010113 addi sp,sp,-272 # 9abcdef0 <_end+0x1abcce30> +80000310: fe0f80e3 beqz t6,800002f0 <_start+0x2f0> +80000314: 00000113 li sp,0 +80000318: 00000193 li gp,0 +8000031c: 00000213 li tp,0 +80000320: 000b2023 sw zero,0(s6) +80000324: 002b2223 sw sp,4(s6) +80000328: 003b2423 sw gp,8(s6) +8000032c: 004b2623 sw tp,12(s6) +80000330: 00001517 auipc a0,0x1 +80000334: cf050513 addi a0,a0,-784 # 80001020 +80000338: 00001597 auipc a1,0x1 +8000033c: d8858593 addi a1,a1,-632 # 800010c0 <_end> +80000340: f0100637 lui a2,0xf0100 +80000344: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee6c> + +80000348 : +80000348: 02b50663 beq a0,a1,80000374 +8000034c: 00c52683 lw a3,12(a0) +80000350: 00d62023 sw a3,0(a2) +80000354: 00852683 lw a3,8(a0) +80000358: 00d62023 sw a3,0(a2) +8000035c: 00452683 lw a3,4(a0) +80000360: 00d62023 sw a3,0(a2) +80000364: 00052683 lw a3,0(a0) +80000368: 00d62023 sw a3,0(a2) +8000036c: 01050513 addi a0,a0,16 +80000370: fd9ff06f j 80000348 + +80000374 : +80000374: f0100537 lui a0,0xf0100 +80000378: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee60> +8000037c: 00052023 sw zero,0(a0) +80000380: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff + +80001058 : +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff + +80001074 : +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff + +800010ac : +800010ac: ffff 0xffff +800010ae: ffff 0xffff + +800010b0 : +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff diff --git a/src/test/resources/asm/I-BGE-01.elf.objdump b/src/test/resources/asm/I-BGE-01.elf.objdump new file mode 100644 index 0000000..21cace1 --- /dev/null +++ b/src/test/resources/asm/I-BGE-01.elf.objdump @@ -0,0 +1,357 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-BGE-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef3f> +80000028: 80000437 lui s0,0x80000 +8000002c: 00000f93 li t6,0 +80000030: 0041d463 ble tp,gp,80000038 <_start+0x38> +80000034: 001fef93 ori t6,t6,1 +80000038: 0051d463 ble t0,gp,80000040 <_start+0x40> +8000003c: 002fef93 ori t6,t6,2 +80000040: 0061d463 ble t1,gp,80000048 <_start+0x48> +80000044: 004fef93 ori t6,t6,4 +80000048: 0071d463 ble t2,gp,80000050 <_start+0x50> +8000004c: 008fef93 ori t6,t6,8 +80000050: 0081d463 ble s0,gp,80000058 <_start+0x58> +80000054: 010fef93 ori t6,t6,16 +80000058: 00312023 sw gp,0(sp) +8000005c: 00412223 sw tp,4(sp) +80000060: 00512423 sw t0,8(sp) +80000064: 00612623 sw t1,12(sp) +80000068: 00712823 sw t2,16(sp) +8000006c: 00812a23 sw s0,20(sp) +80000070: 01f12c23 sw t6,24(sp) +80000074: 00001097 auipc ra,0x1 +80000078: f9008093 addi ra,ra,-112 # 80001004 +8000007c: 00001117 auipc sp,0x1 +80000080: fc010113 addi sp,sp,-64 # 8000103c +80000084: 0000a303 lw t1,0(ra) +80000088: 00000393 li t2,0 +8000008c: 00100413 li s0,1 +80000090: fff00493 li s1,-1 +80000094: 80000537 lui a0,0x80000 +80000098: fff50513 addi a0,a0,-1 # 7fffffff <_end+0xffffef3f> +8000009c: 800005b7 lui a1,0x80000 +800000a0: 00000f93 li t6,0 +800000a4: 00735463 ble t2,t1,800000ac <_start+0xac> +800000a8: 001fef93 ori t6,t6,1 +800000ac: 00835463 ble s0,t1,800000b4 <_start+0xb4> +800000b0: 002fef93 ori t6,t6,2 +800000b4: 00935463 ble s1,t1,800000bc <_start+0xbc> +800000b8: 004fef93 ori t6,t6,4 +800000bc: 00a35463 ble a0,t1,800000c4 <_start+0xc4> +800000c0: 008fef93 ori t6,t6,8 +800000c4: 00b35463 ble a1,t1,800000cc <_start+0xcc> +800000c8: 010fef93 ori t6,t6,16 +800000cc: 00612023 sw t1,0(sp) +800000d0: 00712223 sw t2,4(sp) +800000d4: 00812423 sw s0,8(sp) +800000d8: 00912623 sw s1,12(sp) +800000dc: 00a12823 sw a0,16(sp) +800000e0: 00b12a23 sw a1,20(sp) +800000e4: 01f12c23 sw t6,24(sp) +800000e8: 00001097 auipc ra,0x1 +800000ec: f2008093 addi ra,ra,-224 # 80001008 +800000f0: 00001117 auipc sp,0x1 +800000f4: f6810113 addi sp,sp,-152 # 80001058 +800000f8: 0000a603 lw a2,0(ra) +800000fc: 00000693 li a3,0 +80000100: 00100713 li a4,1 +80000104: fff00793 li a5,-1 +80000108: 80000837 lui a6,0x80000 +8000010c: fff80813 addi a6,a6,-1 # 7fffffff <_end+0xffffef3f> +80000110: 800008b7 lui a7,0x80000 +80000114: 00000f93 li t6,0 +80000118: 00d65463 ble a3,a2,80000120 <_start+0x120> +8000011c: 001fef93 ori t6,t6,1 +80000120: 00e65463 ble a4,a2,80000128 <_start+0x128> +80000124: 002fef93 ori t6,t6,2 +80000128: 00f65463 ble a5,a2,80000130 <_start+0x130> +8000012c: 004fef93 ori t6,t6,4 +80000130: 01065463 ble a6,a2,80000138 <_start+0x138> +80000134: 008fef93 ori t6,t6,8 +80000138: 01165463 ble a7,a2,80000140 <_start+0x140> +8000013c: 010fef93 ori t6,t6,16 +80000140: 00c12023 sw a2,0(sp) +80000144: 00d12223 sw a3,4(sp) +80000148: 00e12423 sw a4,8(sp) +8000014c: 00f12623 sw a5,12(sp) +80000150: 01012823 sw a6,16(sp) +80000154: 01112a23 sw a7,20(sp) +80000158: 01f12c23 sw t6,24(sp) +8000015c: 00001097 auipc ra,0x1 +80000160: eb008093 addi ra,ra,-336 # 8000100c +80000164: 00001117 auipc sp,0x1 +80000168: f1010113 addi sp,sp,-240 # 80001074 +8000016c: 0000a903 lw s2,0(ra) +80000170: 00000993 li s3,0 +80000174: 00100a13 li s4,1 +80000178: fff00a93 li s5,-1 +8000017c: 80000b37 lui s6,0x80000 +80000180: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef3f> +80000184: 80000bb7 lui s7,0x80000 +80000188: 00000f93 li t6,0 +8000018c: 01395463 ble s3,s2,80000194 <_start+0x194> +80000190: 001fef93 ori t6,t6,1 +80000194: 01495463 ble s4,s2,8000019c <_start+0x19c> +80000198: 002fef93 ori t6,t6,2 +8000019c: 01595463 ble s5,s2,800001a4 <_start+0x1a4> +800001a0: 004fef93 ori t6,t6,4 +800001a4: 01695463 ble s6,s2,800001ac <_start+0x1ac> +800001a8: 008fef93 ori t6,t6,8 +800001ac: 01795463 ble s7,s2,800001b4 <_start+0x1b4> +800001b0: 010fef93 ori t6,t6,16 +800001b4: 01212023 sw s2,0(sp) +800001b8: 01312223 sw s3,4(sp) +800001bc: 01412423 sw s4,8(sp) +800001c0: 01512623 sw s5,12(sp) +800001c4: 01612823 sw s6,16(sp) +800001c8: 01712a23 sw s7,20(sp) +800001cc: 01f12c23 sw t6,24(sp) +800001d0: 00001097 auipc ra,0x1 +800001d4: e4008093 addi ra,ra,-448 # 80001010 +800001d8: 00001117 auipc sp,0x1 +800001dc: eb810113 addi sp,sp,-328 # 80001090 +800001e0: 0000ac03 lw s8,0(ra) +800001e4: 00000c93 li s9,0 +800001e8: 00100d13 li s10,1 +800001ec: fff00d93 li s11,-1 +800001f0: 80000e37 lui t3,0x80000 +800001f4: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef3f> +800001f8: 80000eb7 lui t4,0x80000 +800001fc: 00000f93 li t6,0 +80000200: 019c5463 ble s9,s8,80000208 <_start+0x208> +80000204: 001fef93 ori t6,t6,1 +80000208: 01ac5463 ble s10,s8,80000210 <_start+0x210> +8000020c: 002fef93 ori t6,t6,2 +80000210: 01bc5463 ble s11,s8,80000218 <_start+0x218> +80000214: 004fef93 ori t6,t6,4 +80000218: 01cc5463 ble t3,s8,80000220 <_start+0x220> +8000021c: 008fef93 ori t6,t6,8 +80000220: 01dc5463 ble t4,s8,80000228 <_start+0x228> +80000224: 010fef93 ori t6,t6,16 +80000228: 01812023 sw s8,0(sp) +8000022c: 01912223 sw s9,4(sp) +80000230: 01a12423 sw s10,8(sp) +80000234: 01b12623 sw s11,12(sp) +80000238: 01c12823 sw t3,16(sp) +8000023c: 01d12a23 sw t4,20(sp) +80000240: 01f12c23 sw t6,24(sp) +80000244: 00001d97 auipc s11,0x1 +80000248: e68d8d93 addi s11,s11,-408 # 800010ac +8000024c: 00000093 li ra,0 +80000250: 00100113 li sp,1 +80000254: fff00193 li gp,-1 +80000258: 80000237 lui tp,0x80000 +8000025c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef3f> +80000260: 800002b7 lui t0,0x80000 +80000264: 00000f93 li t6,0 +80000268: 0000d463 bgez ra,80000270 <_start+0x270> +8000026c: 001fef93 ori t6,t6,1 +80000270: 00015463 bgez sp,80000278 <_start+0x278> +80000274: 002fef93 ori t6,t6,2 +80000278: 0001d463 bgez gp,80000280 <_start+0x280> +8000027c: 004fef93 ori t6,t6,4 +80000280: 00025463 bgez tp,80000288 <_start+0x288> +80000284: 008fef93 ori t6,t6,8 +80000288: 0002d463 bgez t0,80000290 <_start+0x290> +8000028c: 010fef93 ori t6,t6,16 +80000290: 00105463 blez ra,80000298 <_start+0x298> +80000294: 020fef93 ori t6,t6,32 +80000298: 00205463 blez sp,800002a0 <_start+0x2a0> +8000029c: 040fef93 ori t6,t6,64 +800002a0: 00305463 blez gp,800002a8 <_start+0x2a8> +800002a4: 080fef93 ori t6,t6,128 +800002a8: 00405463 blez tp,800002b0 <_start+0x2b0> +800002ac: 100fef93 ori t6,t6,256 +800002b0: 00505463 blez t0,800002b8 <_start+0x2b8> +800002b4: 200fef93 ori t6,t6,512 +800002b8: 01fda023 sw t6,0(s11) +800002bc: 00001a97 auipc s5,0x1 +800002c0: d58a8a93 addi s5,s5,-680 # 80001014 +800002c4: 00001b17 auipc s6,0x1 +800002c8: decb0b13 addi s6,s6,-532 # 800010b0 +800002cc: 000aaf83 lw t6,0(s5) +800002d0: fff00113 li sp,-1 +800002d4: fff00193 li gp,-1 +800002d8: 0fedd237 lui tp,0xfedd +800002dc: ba920213 addi tp,tp,-1111 # fedcba9 <_start-0x70123457> +800002e0: 020fd463 bgez t6,80000308 <_start+0x308> +800002e4: 00000113 li sp,0 +800002e8: 00000193 li gp,0 +800002ec: 00000213 li tp,0 +800002f0: 876541b7 lui gp,0x87654 +800002f4: 32118193 addi gp,gp,801 # 87654321 <_end+0x7653261> +800002f8: 020fd463 bgez t6,80000320 <_start+0x320> +800002fc: 00000113 li sp,0 +80000300: 00000193 li gp,0 +80000304: 00000213 li tp,0 +80000308: 9abce137 lui sp,0x9abce +8000030c: ef010113 addi sp,sp,-272 # 9abcdef0 <_end+0x1abcce30> +80000310: fe0fd0e3 bgez t6,800002f0 <_start+0x2f0> +80000314: 00000113 li sp,0 +80000318: 00000193 li gp,0 +8000031c: 00000213 li tp,0 +80000320: 000b2023 sw zero,0(s6) +80000324: 002b2223 sw sp,4(s6) +80000328: 003b2423 sw gp,8(s6) +8000032c: 004b2623 sw tp,12(s6) +80000330: 00001517 auipc a0,0x1 +80000334: cf050513 addi a0,a0,-784 # 80001020 +80000338: 00001597 auipc a1,0x1 +8000033c: d8858593 addi a1,a1,-632 # 800010c0 <_end> +80000340: f0100637 lui a2,0xf0100 +80000344: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee6c> + +80000348 : +80000348: 02b50663 beq a0,a1,80000374 +8000034c: 00c52683 lw a3,12(a0) +80000350: 00d62023 sw a3,0(a2) +80000354: 00852683 lw a3,8(a0) +80000358: 00d62023 sw a3,0(a2) +8000035c: 00452683 lw a3,4(a0) +80000360: 00d62023 sw a3,0(a2) +80000364: 00052683 lw a3,0(a0) +80000368: 00d62023 sw a3,0(a2) +8000036c: 01050513 addi a0,a0,16 +80000370: fd9ff06f j 80000348 + +80000374 : +80000374: f0100537 lui a0,0xf0100 +80000378: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee60> +8000037c: 00052023 sw zero,0(a0) +80000380: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: 0001 nop + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff + +80001058 : +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff + +80001074 : +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff + +800010ac : +800010ac: ffff 0xffff +800010ae: ffff 0xffff + +800010b0 : +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff diff --git a/src/test/resources/asm/I-BGEU-01.elf.objdump b/src/test/resources/asm/I-BGEU-01.elf.objdump new file mode 100644 index 0000000..4727fe1 --- /dev/null +++ b/src/test/resources/asm/I-BGEU-01.elf.objdump @@ -0,0 +1,357 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-BGEU-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef3f> +80000028: 80000437 lui s0,0x80000 +8000002c: 00000f93 li t6,0 +80000030: 0041f463 bleu tp,gp,80000038 <_start+0x38> +80000034: 001fef93 ori t6,t6,1 +80000038: 0051f463 bleu t0,gp,80000040 <_start+0x40> +8000003c: 002fef93 ori t6,t6,2 +80000040: 0061f463 bleu t1,gp,80000048 <_start+0x48> +80000044: 004fef93 ori t6,t6,4 +80000048: 0071f463 bleu t2,gp,80000050 <_start+0x50> +8000004c: 008fef93 ori t6,t6,8 +80000050: 0081f463 bleu s0,gp,80000058 <_start+0x58> +80000054: 010fef93 ori t6,t6,16 +80000058: 00312023 sw gp,0(sp) +8000005c: 00412223 sw tp,4(sp) +80000060: 00512423 sw t0,8(sp) +80000064: 00612623 sw t1,12(sp) +80000068: 00712823 sw t2,16(sp) +8000006c: 00812a23 sw s0,20(sp) +80000070: 01f12c23 sw t6,24(sp) +80000074: 00001097 auipc ra,0x1 +80000078: f9008093 addi ra,ra,-112 # 80001004 +8000007c: 00001117 auipc sp,0x1 +80000080: fc010113 addi sp,sp,-64 # 8000103c +80000084: 0000a303 lw t1,0(ra) +80000088: 00000393 li t2,0 +8000008c: 00100413 li s0,1 +80000090: fff00493 li s1,-1 +80000094: 80000537 lui a0,0x80000 +80000098: fff50513 addi a0,a0,-1 # 7fffffff <_end+0xffffef3f> +8000009c: 800005b7 lui a1,0x80000 +800000a0: 00000f93 li t6,0 +800000a4: 00737463 bleu t2,t1,800000ac <_start+0xac> +800000a8: 001fef93 ori t6,t6,1 +800000ac: 00837463 bleu s0,t1,800000b4 <_start+0xb4> +800000b0: 002fef93 ori t6,t6,2 +800000b4: 00937463 bleu s1,t1,800000bc <_start+0xbc> +800000b8: 004fef93 ori t6,t6,4 +800000bc: 00a37463 bleu a0,t1,800000c4 <_start+0xc4> +800000c0: 008fef93 ori t6,t6,8 +800000c4: 00b37463 bleu a1,t1,800000cc <_start+0xcc> +800000c8: 010fef93 ori t6,t6,16 +800000cc: 00612023 sw t1,0(sp) +800000d0: 00712223 sw t2,4(sp) +800000d4: 00812423 sw s0,8(sp) +800000d8: 00912623 sw s1,12(sp) +800000dc: 00a12823 sw a0,16(sp) +800000e0: 00b12a23 sw a1,20(sp) +800000e4: 01f12c23 sw t6,24(sp) +800000e8: 00001097 auipc ra,0x1 +800000ec: f2008093 addi ra,ra,-224 # 80001008 +800000f0: 00001117 auipc sp,0x1 +800000f4: f6810113 addi sp,sp,-152 # 80001058 +800000f8: 0000a603 lw a2,0(ra) +800000fc: 00000693 li a3,0 +80000100: 00100713 li a4,1 +80000104: fff00793 li a5,-1 +80000108: 80000837 lui a6,0x80000 +8000010c: fff80813 addi a6,a6,-1 # 7fffffff <_end+0xffffef3f> +80000110: 800008b7 lui a7,0x80000 +80000114: 00000f93 li t6,0 +80000118: 00d67463 bleu a3,a2,80000120 <_start+0x120> +8000011c: 001fef93 ori t6,t6,1 +80000120: 00e67463 bleu a4,a2,80000128 <_start+0x128> +80000124: 002fef93 ori t6,t6,2 +80000128: 00f67463 bleu a5,a2,80000130 <_start+0x130> +8000012c: 004fef93 ori t6,t6,4 +80000130: 01067463 bleu a6,a2,80000138 <_start+0x138> +80000134: 008fef93 ori t6,t6,8 +80000138: 01167463 bleu a7,a2,80000140 <_start+0x140> +8000013c: 010fef93 ori t6,t6,16 +80000140: 00c12023 sw a2,0(sp) +80000144: 00d12223 sw a3,4(sp) +80000148: 00e12423 sw a4,8(sp) +8000014c: 00f12623 sw a5,12(sp) +80000150: 01012823 sw a6,16(sp) +80000154: 01112a23 sw a7,20(sp) +80000158: 01f12c23 sw t6,24(sp) +8000015c: 00001097 auipc ra,0x1 +80000160: eb008093 addi ra,ra,-336 # 8000100c +80000164: 00001117 auipc sp,0x1 +80000168: f1010113 addi sp,sp,-240 # 80001074 +8000016c: 0000a903 lw s2,0(ra) +80000170: 00000993 li s3,0 +80000174: 00100a13 li s4,1 +80000178: fff00a93 li s5,-1 +8000017c: 80000b37 lui s6,0x80000 +80000180: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef3f> +80000184: 80000bb7 lui s7,0x80000 +80000188: 00000f93 li t6,0 +8000018c: 01397463 bleu s3,s2,80000194 <_start+0x194> +80000190: 001fef93 ori t6,t6,1 +80000194: 01497463 bleu s4,s2,8000019c <_start+0x19c> +80000198: 002fef93 ori t6,t6,2 +8000019c: 01597463 bleu s5,s2,800001a4 <_start+0x1a4> +800001a0: 004fef93 ori t6,t6,4 +800001a4: 01697463 bleu s6,s2,800001ac <_start+0x1ac> +800001a8: 008fef93 ori t6,t6,8 +800001ac: 01797463 bleu s7,s2,800001b4 <_start+0x1b4> +800001b0: 010fef93 ori t6,t6,16 +800001b4: 01212023 sw s2,0(sp) +800001b8: 01312223 sw s3,4(sp) +800001bc: 01412423 sw s4,8(sp) +800001c0: 01512623 sw s5,12(sp) +800001c4: 01612823 sw s6,16(sp) +800001c8: 01712a23 sw s7,20(sp) +800001cc: 01f12c23 sw t6,24(sp) +800001d0: 00001097 auipc ra,0x1 +800001d4: e4008093 addi ra,ra,-448 # 80001010 +800001d8: 00001117 auipc sp,0x1 +800001dc: eb810113 addi sp,sp,-328 # 80001090 +800001e0: 0000ac03 lw s8,0(ra) +800001e4: 00000c93 li s9,0 +800001e8: 00100d13 li s10,1 +800001ec: fff00d93 li s11,-1 +800001f0: 80000e37 lui t3,0x80000 +800001f4: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef3f> +800001f8: 80000eb7 lui t4,0x80000 +800001fc: 00000f93 li t6,0 +80000200: 019c7463 bleu s9,s8,80000208 <_start+0x208> +80000204: 001fef93 ori t6,t6,1 +80000208: 01ac7463 bleu s10,s8,80000210 <_start+0x210> +8000020c: 002fef93 ori t6,t6,2 +80000210: 01bc7463 bleu s11,s8,80000218 <_start+0x218> +80000214: 004fef93 ori t6,t6,4 +80000218: 01cc7463 bleu t3,s8,80000220 <_start+0x220> +8000021c: 008fef93 ori t6,t6,8 +80000220: 01dc7463 bleu t4,s8,80000228 <_start+0x228> +80000224: 010fef93 ori t6,t6,16 +80000228: 01812023 sw s8,0(sp) +8000022c: 01912223 sw s9,4(sp) +80000230: 01a12423 sw s10,8(sp) +80000234: 01b12623 sw s11,12(sp) +80000238: 01c12823 sw t3,16(sp) +8000023c: 01d12a23 sw t4,20(sp) +80000240: 01f12c23 sw t6,24(sp) +80000244: 00001d97 auipc s11,0x1 +80000248: e68d8d93 addi s11,s11,-408 # 800010ac +8000024c: 00000093 li ra,0 +80000250: 00100113 li sp,1 +80000254: fff00193 li gp,-1 +80000258: 80000237 lui tp,0x80000 +8000025c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef3f> +80000260: 800002b7 lui t0,0x80000 +80000264: 00000f93 li t6,0 +80000268: 0000f463 bleu zero,ra,80000270 <_start+0x270> +8000026c: 001fef93 ori t6,t6,1 +80000270: 00017463 bleu zero,sp,80000278 <_start+0x278> +80000274: 002fef93 ori t6,t6,2 +80000278: 0001f463 bleu zero,gp,80000280 <_start+0x280> +8000027c: 004fef93 ori t6,t6,4 +80000280: 00027463 bleu zero,tp,80000288 <_start+0x288> +80000284: 008fef93 ori t6,t6,8 +80000288: 0002f463 bleu zero,t0,80000290 <_start+0x290> +8000028c: 010fef93 ori t6,t6,16 +80000290: 00107463 bleu ra,zero,80000298 <_start+0x298> +80000294: 020fef93 ori t6,t6,32 +80000298: 00207463 bleu sp,zero,800002a0 <_start+0x2a0> +8000029c: 040fef93 ori t6,t6,64 +800002a0: 00307463 bleu gp,zero,800002a8 <_start+0x2a8> +800002a4: 080fef93 ori t6,t6,128 +800002a8: 00407463 bleu tp,zero,800002b0 <_start+0x2b0> +800002ac: 100fef93 ori t6,t6,256 +800002b0: 00507463 bleu t0,zero,800002b8 <_start+0x2b8> +800002b4: 200fef93 ori t6,t6,512 +800002b8: 01fda023 sw t6,0(s11) +800002bc: 00001a97 auipc s5,0x1 +800002c0: d58a8a93 addi s5,s5,-680 # 80001014 +800002c4: 00001b17 auipc s6,0x1 +800002c8: decb0b13 addi s6,s6,-532 # 800010b0 +800002cc: 000aaf83 lw t6,0(s5) +800002d0: fff00113 li sp,-1 +800002d4: fff00193 li gp,-1 +800002d8: 0fedd237 lui tp,0xfedd +800002dc: ba920213 addi tp,tp,-1111 # fedcba9 <_start-0x70123457> +800002e0: 020ff463 bleu zero,t6,80000308 <_start+0x308> +800002e4: 00000113 li sp,0 +800002e8: 00000193 li gp,0 +800002ec: 00000213 li tp,0 +800002f0: 876541b7 lui gp,0x87654 +800002f4: 32118193 addi gp,gp,801 # 87654321 <_end+0x7653261> +800002f8: 020ff463 bleu zero,t6,80000320 <_start+0x320> +800002fc: 00000113 li sp,0 +80000300: 00000193 li gp,0 +80000304: 00000213 li tp,0 +80000308: 9abce137 lui sp,0x9abce +8000030c: ef010113 addi sp,sp,-272 # 9abcdef0 <_end+0x1abcce30> +80000310: fe0ff0e3 bleu zero,t6,800002f0 <_start+0x2f0> +80000314: 00000113 li sp,0 +80000318: 00000193 li gp,0 +8000031c: 00000213 li tp,0 +80000320: 000b2023 sw zero,0(s6) +80000324: 002b2223 sw sp,4(s6) +80000328: 003b2423 sw gp,8(s6) +8000032c: 004b2623 sw tp,12(s6) +80000330: 00001517 auipc a0,0x1 +80000334: cf050513 addi a0,a0,-784 # 80001020 +80000338: 00001597 auipc a1,0x1 +8000033c: d8858593 addi a1,a1,-632 # 800010c0 <_end> +80000340: f0100637 lui a2,0xf0100 +80000344: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee6c> + +80000348 : +80000348: 02b50663 beq a0,a1,80000374 +8000034c: 00c52683 lw a3,12(a0) +80000350: 00d62023 sw a3,0(a2) +80000354: 00852683 lw a3,8(a0) +80000358: 00d62023 sw a3,0(a2) +8000035c: 00452683 lw a3,4(a0) +80000360: 00d62023 sw a3,0(a2) +80000364: 00052683 lw a3,0(a0) +80000368: 00d62023 sw a3,0(a2) +8000036c: 01050513 addi a0,a0,16 +80000370: fd9ff06f j 80000348 + +80000374 : +80000374: f0100537 lui a0,0xf0100 +80000378: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee60> +8000037c: 00052023 sw zero,0(a0) +80000380: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: 0001 nop + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff + +80001058 : +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff + +80001074 : +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff + +800010ac : +800010ac: ffff 0xffff +800010ae: ffff 0xffff + +800010b0 : +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff diff --git a/src/test/resources/asm/I-BLT-01.elf.objdump b/src/test/resources/asm/I-BLT-01.elf.objdump new file mode 100644 index 0000000..837a074 --- /dev/null +++ b/src/test/resources/asm/I-BLT-01.elf.objdump @@ -0,0 +1,358 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-BLT-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef3f> +80000028: 80000437 lui s0,0x80000 +8000002c: 00000f93 li t6,0 +80000030: 0041c463 blt gp,tp,80000038 <_start+0x38> +80000034: 001fef93 ori t6,t6,1 +80000038: 0051c463 blt gp,t0,80000040 <_start+0x40> +8000003c: 002fef93 ori t6,t6,2 +80000040: 0061c463 blt gp,t1,80000048 <_start+0x48> +80000044: 004fef93 ori t6,t6,4 +80000048: 0071c463 blt gp,t2,80000050 <_start+0x50> +8000004c: 008fef93 ori t6,t6,8 +80000050: 0081c463 blt gp,s0,80000058 <_start+0x58> +80000054: 010fef93 ori t6,t6,16 +80000058: 00312023 sw gp,0(sp) +8000005c: 00412223 sw tp,4(sp) +80000060: 00512423 sw t0,8(sp) +80000064: 00612623 sw t1,12(sp) +80000068: 00712823 sw t2,16(sp) +8000006c: 00812a23 sw s0,20(sp) +80000070: 01f12c23 sw t6,24(sp) +80000074: 00001097 auipc ra,0x1 +80000078: f9008093 addi ra,ra,-112 # 80001004 +8000007c: 00001117 auipc sp,0x1 +80000080: fc010113 addi sp,sp,-64 # 8000103c +80000084: 0000a303 lw t1,0(ra) +80000088: 00000393 li t2,0 +8000008c: 00100413 li s0,1 +80000090: fff00493 li s1,-1 +80000094: 80000537 lui a0,0x80000 +80000098: fff50513 addi a0,a0,-1 # 7fffffff <_end+0xffffef3f> +8000009c: 800005b7 lui a1,0x80000 +800000a0: 00000f93 li t6,0 +800000a4: 00734463 blt t1,t2,800000ac <_start+0xac> +800000a8: 001fef93 ori t6,t6,1 +800000ac: 00834463 blt t1,s0,800000b4 <_start+0xb4> +800000b0: 002fef93 ori t6,t6,2 +800000b4: 00934463 blt t1,s1,800000bc <_start+0xbc> +800000b8: 004fef93 ori t6,t6,4 +800000bc: 00a34463 blt t1,a0,800000c4 <_start+0xc4> +800000c0: 008fef93 ori t6,t6,8 +800000c4: 00b34463 blt t1,a1,800000cc <_start+0xcc> +800000c8: 010fef93 ori t6,t6,16 +800000cc: 00612023 sw t1,0(sp) +800000d0: 00712223 sw t2,4(sp) +800000d4: 00812423 sw s0,8(sp) +800000d8: 00912623 sw s1,12(sp) +800000dc: 00a12823 sw a0,16(sp) +800000e0: 00b12a23 sw a1,20(sp) +800000e4: 01f12c23 sw t6,24(sp) +800000e8: 00001097 auipc ra,0x1 +800000ec: f2008093 addi ra,ra,-224 # 80001008 +800000f0: 00001117 auipc sp,0x1 +800000f4: f6810113 addi sp,sp,-152 # 80001058 +800000f8: 0000a603 lw a2,0(ra) +800000fc: 00000693 li a3,0 +80000100: 00100713 li a4,1 +80000104: fff00793 li a5,-1 +80000108: 80000837 lui a6,0x80000 +8000010c: fff80813 addi a6,a6,-1 # 7fffffff <_end+0xffffef3f> +80000110: 800008b7 lui a7,0x80000 +80000114: 00000f93 li t6,0 +80000118: 00d64463 blt a2,a3,80000120 <_start+0x120> +8000011c: 001fef93 ori t6,t6,1 +80000120: 00e64463 blt a2,a4,80000128 <_start+0x128> +80000124: 002fef93 ori t6,t6,2 +80000128: 00f64463 blt a2,a5,80000130 <_start+0x130> +8000012c: 004fef93 ori t6,t6,4 +80000130: 01064463 blt a2,a6,80000138 <_start+0x138> +80000134: 008fef93 ori t6,t6,8 +80000138: 01164463 blt a2,a7,80000140 <_start+0x140> +8000013c: 010fef93 ori t6,t6,16 +80000140: 00c12023 sw a2,0(sp) +80000144: 00d12223 sw a3,4(sp) +80000148: 00e12423 sw a4,8(sp) +8000014c: 00f12623 sw a5,12(sp) +80000150: 01012823 sw a6,16(sp) +80000154: 01112a23 sw a7,20(sp) +80000158: 01f12c23 sw t6,24(sp) +8000015c: 00001097 auipc ra,0x1 +80000160: eb008093 addi ra,ra,-336 # 8000100c +80000164: 00001117 auipc sp,0x1 +80000168: f1010113 addi sp,sp,-240 # 80001074 +8000016c: 0000a903 lw s2,0(ra) +80000170: 00000993 li s3,0 +80000174: 00100a13 li s4,1 +80000178: fff00a93 li s5,-1 +8000017c: 80000b37 lui s6,0x80000 +80000180: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef3f> +80000184: 80000bb7 lui s7,0x80000 +80000188: 00000f93 li t6,0 +8000018c: 01394463 blt s2,s3,80000194 <_start+0x194> +80000190: 001fef93 ori t6,t6,1 +80000194: 01494463 blt s2,s4,8000019c <_start+0x19c> +80000198: 002fef93 ori t6,t6,2 +8000019c: 01594463 blt s2,s5,800001a4 <_start+0x1a4> +800001a0: 004fef93 ori t6,t6,4 +800001a4: 01694463 blt s2,s6,800001ac <_start+0x1ac> +800001a8: 008fef93 ori t6,t6,8 +800001ac: 01794463 blt s2,s7,800001b4 <_start+0x1b4> +800001b0: 010fef93 ori t6,t6,16 +800001b4: 01212023 sw s2,0(sp) +800001b8: 01312223 sw s3,4(sp) +800001bc: 01412423 sw s4,8(sp) +800001c0: 01512623 sw s5,12(sp) +800001c4: 01612823 sw s6,16(sp) +800001c8: 01712a23 sw s7,20(sp) +800001cc: 01f12c23 sw t6,24(sp) +800001d0: 00001097 auipc ra,0x1 +800001d4: e4008093 addi ra,ra,-448 # 80001010 +800001d8: 00001117 auipc sp,0x1 +800001dc: eb810113 addi sp,sp,-328 # 80001090 +800001e0: 0000ac03 lw s8,0(ra) +800001e4: 00000c93 li s9,0 +800001e8: 00100d13 li s10,1 +800001ec: fff00d93 li s11,-1 +800001f0: 80000e37 lui t3,0x80000 +800001f4: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef3f> +800001f8: 80000eb7 lui t4,0x80000 +800001fc: 00000f93 li t6,0 +80000200: 019c4463 blt s8,s9,80000208 <_start+0x208> +80000204: 001fef93 ori t6,t6,1 +80000208: 01ac4463 blt s8,s10,80000210 <_start+0x210> +8000020c: 002fef93 ori t6,t6,2 +80000210: 01bc4463 blt s8,s11,80000218 <_start+0x218> +80000214: 004fef93 ori t6,t6,4 +80000218: 01cc4463 blt s8,t3,80000220 <_start+0x220> +8000021c: 008fef93 ori t6,t6,8 +80000220: 01dc4463 blt s8,t4,80000228 <_start+0x228> +80000224: 010fef93 ori t6,t6,16 +80000228: 01812023 sw s8,0(sp) +8000022c: 01912223 sw s9,4(sp) +80000230: 01a12423 sw s10,8(sp) +80000234: 01b12623 sw s11,12(sp) +80000238: 01c12823 sw t3,16(sp) +8000023c: 01d12a23 sw t4,20(sp) +80000240: 01f12c23 sw t6,24(sp) +80000244: 00001d97 auipc s11,0x1 +80000248: e68d8d93 addi s11,s11,-408 # 800010ac +8000024c: 00000093 li ra,0 +80000250: 00100113 li sp,1 +80000254: fff00193 li gp,-1 +80000258: 80000237 lui tp,0x80000 +8000025c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef3f> +80000260: 800002b7 lui t0,0x80000 +80000264: 00000f93 li t6,0 +80000268: 0000c463 bltz ra,80000270 <_start+0x270> +8000026c: 001fef93 ori t6,t6,1 +80000270: 00014463 bltz sp,80000278 <_start+0x278> +80000274: 002fef93 ori t6,t6,2 +80000278: 0001c463 bltz gp,80000280 <_start+0x280> +8000027c: 004fef93 ori t6,t6,4 +80000280: 00024463 bltz tp,80000288 <_start+0x288> +80000284: 008fef93 ori t6,t6,8 +80000288: 0002c463 bltz t0,80000290 <_start+0x290> +8000028c: 010fef93 ori t6,t6,16 +80000290: 00104463 bgtz ra,80000298 <_start+0x298> +80000294: 020fef93 ori t6,t6,32 +80000298: 00204463 bgtz sp,800002a0 <_start+0x2a0> +8000029c: 040fef93 ori t6,t6,64 +800002a0: 00304463 bgtz gp,800002a8 <_start+0x2a8> +800002a4: 080fef93 ori t6,t6,128 +800002a8: 00404463 bgtz tp,800002b0 <_start+0x2b0> +800002ac: 100fef93 ori t6,t6,256 +800002b0: 00504463 bgtz t0,800002b8 <_start+0x2b8> +800002b4: 200fef93 ori t6,t6,512 +800002b8: 01fda023 sw t6,0(s11) +800002bc: 00001a97 auipc s5,0x1 +800002c0: d58a8a93 addi s5,s5,-680 # 80001014 +800002c4: 00001b17 auipc s6,0x1 +800002c8: decb0b13 addi s6,s6,-532 # 800010b0 +800002cc: 000aaf83 lw t6,0(s5) +800002d0: fff00113 li sp,-1 +800002d4: fff00193 li gp,-1 +800002d8: 0fedd237 lui tp,0xfedd +800002dc: ba920213 addi tp,tp,-1111 # fedcba9 <_start-0x70123457> +800002e0: 020fc463 bltz t6,80000308 <_start+0x308> +800002e4: 00000113 li sp,0 +800002e8: 00000193 li gp,0 +800002ec: 00000213 li tp,0 +800002f0: 876541b7 lui gp,0x87654 +800002f4: 32118193 addi gp,gp,801 # 87654321 <_end+0x7653261> +800002f8: 020fc463 bltz t6,80000320 <_start+0x320> +800002fc: 00000113 li sp,0 +80000300: 00000193 li gp,0 +80000304: 00000213 li tp,0 +80000308: 9abce137 lui sp,0x9abce +8000030c: ef010113 addi sp,sp,-272 # 9abcdef0 <_end+0x1abcce30> +80000310: fe0fc0e3 bltz t6,800002f0 <_start+0x2f0> +80000314: 00000113 li sp,0 +80000318: 00000193 li gp,0 +8000031c: 00000213 li tp,0 +80000320: 000b2023 sw zero,0(s6) +80000324: 002b2223 sw sp,4(s6) +80000328: 003b2423 sw gp,8(s6) +8000032c: 004b2623 sw tp,12(s6) +80000330: 00001517 auipc a0,0x1 +80000334: cf050513 addi a0,a0,-784 # 80001020 +80000338: 00001597 auipc a1,0x1 +8000033c: d8858593 addi a1,a1,-632 # 800010c0 <_end> +80000340: f0100637 lui a2,0xf0100 +80000344: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee6c> + +80000348 : +80000348: 02b50663 beq a0,a1,80000374 +8000034c: 00c52683 lw a3,12(a0) +80000350: 00d62023 sw a3,0(a2) +80000354: 00852683 lw a3,8(a0) +80000358: 00d62023 sw a3,0(a2) +8000035c: 00452683 lw a3,4(a0) +80000360: 00d62023 sw a3,0(a2) +80000364: 00052683 lw a3,0(a0) +80000368: 00d62023 sw a3,0(a2) +8000036c: 01050513 addi a0,a0,16 +80000370: fd9ff06f j 80000348 + +80000374 : +80000374: f0100537 lui a0,0xf0100 +80000378: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee60> +8000037c: 00052023 sw zero,0(a0) +80000380: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff + +80001058 : +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff + +80001074 : +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff + +800010ac : +800010ac: ffff 0xffff +800010ae: ffff 0xffff + +800010b0 : +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff diff --git a/src/test/resources/asm/I-BLTU-01.elf.objdump b/src/test/resources/asm/I-BLTU-01.elf.objdump new file mode 100644 index 0000000..cd90729 --- /dev/null +++ b/src/test/resources/asm/I-BLTU-01.elf.objdump @@ -0,0 +1,357 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-BLTU-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef3f> +80000028: 80000437 lui s0,0x80000 +8000002c: 00000f93 li t6,0 +80000030: 0041e463 bltu gp,tp,80000038 <_start+0x38> +80000034: 001fef93 ori t6,t6,1 +80000038: 0051e463 bltu gp,t0,80000040 <_start+0x40> +8000003c: 002fef93 ori t6,t6,2 +80000040: 0061e463 bltu gp,t1,80000048 <_start+0x48> +80000044: 004fef93 ori t6,t6,4 +80000048: 0071e463 bltu gp,t2,80000050 <_start+0x50> +8000004c: 008fef93 ori t6,t6,8 +80000050: 0081e463 bltu gp,s0,80000058 <_start+0x58> +80000054: 010fef93 ori t6,t6,16 +80000058: 00312023 sw gp,0(sp) +8000005c: 00412223 sw tp,4(sp) +80000060: 00512423 sw t0,8(sp) +80000064: 00612623 sw t1,12(sp) +80000068: 00712823 sw t2,16(sp) +8000006c: 00812a23 sw s0,20(sp) +80000070: 01f12c23 sw t6,24(sp) +80000074: 00001097 auipc ra,0x1 +80000078: f9008093 addi ra,ra,-112 # 80001004 +8000007c: 00001117 auipc sp,0x1 +80000080: fc010113 addi sp,sp,-64 # 8000103c +80000084: 0000a303 lw t1,0(ra) +80000088: 00000393 li t2,0 +8000008c: 00100413 li s0,1 +80000090: fff00493 li s1,-1 +80000094: 80000537 lui a0,0x80000 +80000098: fff50513 addi a0,a0,-1 # 7fffffff <_end+0xffffef3f> +8000009c: 800005b7 lui a1,0x80000 +800000a0: 00000f93 li t6,0 +800000a4: 00736463 bltu t1,t2,800000ac <_start+0xac> +800000a8: 001fef93 ori t6,t6,1 +800000ac: 00836463 bltu t1,s0,800000b4 <_start+0xb4> +800000b0: 002fef93 ori t6,t6,2 +800000b4: 00936463 bltu t1,s1,800000bc <_start+0xbc> +800000b8: 004fef93 ori t6,t6,4 +800000bc: 00a36463 bltu t1,a0,800000c4 <_start+0xc4> +800000c0: 008fef93 ori t6,t6,8 +800000c4: 00b36463 bltu t1,a1,800000cc <_start+0xcc> +800000c8: 010fef93 ori t6,t6,16 +800000cc: 00612023 sw t1,0(sp) +800000d0: 00712223 sw t2,4(sp) +800000d4: 00812423 sw s0,8(sp) +800000d8: 00912623 sw s1,12(sp) +800000dc: 00a12823 sw a0,16(sp) +800000e0: 00b12a23 sw a1,20(sp) +800000e4: 01f12c23 sw t6,24(sp) +800000e8: 00001097 auipc ra,0x1 +800000ec: f2008093 addi ra,ra,-224 # 80001008 +800000f0: 00001117 auipc sp,0x1 +800000f4: f6810113 addi sp,sp,-152 # 80001058 +800000f8: 0000a603 lw a2,0(ra) +800000fc: 00000693 li a3,0 +80000100: 00100713 li a4,1 +80000104: fff00793 li a5,-1 +80000108: 80000837 lui a6,0x80000 +8000010c: fff80813 addi a6,a6,-1 # 7fffffff <_end+0xffffef3f> +80000110: 800008b7 lui a7,0x80000 +80000114: 00000f93 li t6,0 +80000118: 00d66463 bltu a2,a3,80000120 <_start+0x120> +8000011c: 001fef93 ori t6,t6,1 +80000120: 00e66463 bltu a2,a4,80000128 <_start+0x128> +80000124: 002fef93 ori t6,t6,2 +80000128: 00f66463 bltu a2,a5,80000130 <_start+0x130> +8000012c: 004fef93 ori t6,t6,4 +80000130: 01066463 bltu a2,a6,80000138 <_start+0x138> +80000134: 008fef93 ori t6,t6,8 +80000138: 01166463 bltu a2,a7,80000140 <_start+0x140> +8000013c: 010fef93 ori t6,t6,16 +80000140: 00c12023 sw a2,0(sp) +80000144: 00d12223 sw a3,4(sp) +80000148: 00e12423 sw a4,8(sp) +8000014c: 00f12623 sw a5,12(sp) +80000150: 01012823 sw a6,16(sp) +80000154: 01112a23 sw a7,20(sp) +80000158: 01f12c23 sw t6,24(sp) +8000015c: 00001097 auipc ra,0x1 +80000160: eb008093 addi ra,ra,-336 # 8000100c +80000164: 00001117 auipc sp,0x1 +80000168: f1010113 addi sp,sp,-240 # 80001074 +8000016c: 0000a903 lw s2,0(ra) +80000170: 00000993 li s3,0 +80000174: 00100a13 li s4,1 +80000178: fff00a93 li s5,-1 +8000017c: 80000b37 lui s6,0x80000 +80000180: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef3f> +80000184: 80000bb7 lui s7,0x80000 +80000188: 00000f93 li t6,0 +8000018c: 01396463 bltu s2,s3,80000194 <_start+0x194> +80000190: 001fef93 ori t6,t6,1 +80000194: 01496463 bltu s2,s4,8000019c <_start+0x19c> +80000198: 002fef93 ori t6,t6,2 +8000019c: 01596463 bltu s2,s5,800001a4 <_start+0x1a4> +800001a0: 004fef93 ori t6,t6,4 +800001a4: 01696463 bltu s2,s6,800001ac <_start+0x1ac> +800001a8: 008fef93 ori t6,t6,8 +800001ac: 01796463 bltu s2,s7,800001b4 <_start+0x1b4> +800001b0: 010fef93 ori t6,t6,16 +800001b4: 01212023 sw s2,0(sp) +800001b8: 01312223 sw s3,4(sp) +800001bc: 01412423 sw s4,8(sp) +800001c0: 01512623 sw s5,12(sp) +800001c4: 01612823 sw s6,16(sp) +800001c8: 01712a23 sw s7,20(sp) +800001cc: 01f12c23 sw t6,24(sp) +800001d0: 00001097 auipc ra,0x1 +800001d4: e4008093 addi ra,ra,-448 # 80001010 +800001d8: 00001117 auipc sp,0x1 +800001dc: eb810113 addi sp,sp,-328 # 80001090 +800001e0: 0000ac03 lw s8,0(ra) +800001e4: 00000c93 li s9,0 +800001e8: 00100d13 li s10,1 +800001ec: fff00d93 li s11,-1 +800001f0: 80000e37 lui t3,0x80000 +800001f4: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef3f> +800001f8: 80000eb7 lui t4,0x80000 +800001fc: 00000f93 li t6,0 +80000200: 019c6463 bltu s8,s9,80000208 <_start+0x208> +80000204: 001fef93 ori t6,t6,1 +80000208: 01ac6463 bltu s8,s10,80000210 <_start+0x210> +8000020c: 002fef93 ori t6,t6,2 +80000210: 01bc6463 bltu s8,s11,80000218 <_start+0x218> +80000214: 004fef93 ori t6,t6,4 +80000218: 01cc6463 bltu s8,t3,80000220 <_start+0x220> +8000021c: 008fef93 ori t6,t6,8 +80000220: 01dc6463 bltu s8,t4,80000228 <_start+0x228> +80000224: 010fef93 ori t6,t6,16 +80000228: 01812023 sw s8,0(sp) +8000022c: 01912223 sw s9,4(sp) +80000230: 01a12423 sw s10,8(sp) +80000234: 01b12623 sw s11,12(sp) +80000238: 01c12823 sw t3,16(sp) +8000023c: 01d12a23 sw t4,20(sp) +80000240: 01f12c23 sw t6,24(sp) +80000244: 00001d97 auipc s11,0x1 +80000248: e68d8d93 addi s11,s11,-408 # 800010ac +8000024c: 00000093 li ra,0 +80000250: 00100113 li sp,1 +80000254: fff00193 li gp,-1 +80000258: 80000237 lui tp,0x80000 +8000025c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef3f> +80000260: 800002b7 lui t0,0x80000 +80000264: 00000f93 li t6,0 +80000268: 0000e463 bltu ra,zero,80000270 <_start+0x270> +8000026c: 001fef93 ori t6,t6,1 +80000270: 00016463 bltu sp,zero,80000278 <_start+0x278> +80000274: 002fef93 ori t6,t6,2 +80000278: 0001e463 bltu gp,zero,80000280 <_start+0x280> +8000027c: 004fef93 ori t6,t6,4 +80000280: 00026463 bltu tp,zero,80000288 <_start+0x288> +80000284: 008fef93 ori t6,t6,8 +80000288: 0002e463 bltu t0,zero,80000290 <_start+0x290> +8000028c: 010fef93 ori t6,t6,16 +80000290: 00106463 bltu zero,ra,80000298 <_start+0x298> +80000294: 020fef93 ori t6,t6,32 +80000298: 00206463 bltu zero,sp,800002a0 <_start+0x2a0> +8000029c: 040fef93 ori t6,t6,64 +800002a0: 00306463 bltu zero,gp,800002a8 <_start+0x2a8> +800002a4: 080fef93 ori t6,t6,128 +800002a8: 00406463 bltu zero,tp,800002b0 <_start+0x2b0> +800002ac: 100fef93 ori t6,t6,256 +800002b0: 00506463 bltu zero,t0,800002b8 <_start+0x2b8> +800002b4: 200fef93 ori t6,t6,512 +800002b8: 01fda023 sw t6,0(s11) +800002bc: 00001a97 auipc s5,0x1 +800002c0: d58a8a93 addi s5,s5,-680 # 80001014 +800002c4: 00001b17 auipc s6,0x1 +800002c8: decb0b13 addi s6,s6,-532 # 800010b0 +800002cc: 000aaf83 lw t6,0(s5) +800002d0: fff00113 li sp,-1 +800002d4: fff00193 li gp,-1 +800002d8: 0fedd237 lui tp,0xfedd +800002dc: ba920213 addi tp,tp,-1111 # fedcba9 <_start-0x70123457> +800002e0: 03f06463 bltu zero,t6,80000308 <_start+0x308> +800002e4: 00000113 li sp,0 +800002e8: 00000193 li gp,0 +800002ec: 00000213 li tp,0 +800002f0: 876541b7 lui gp,0x87654 +800002f4: 32118193 addi gp,gp,801 # 87654321 <_end+0x7653261> +800002f8: 03f06463 bltu zero,t6,80000320 <_start+0x320> +800002fc: 00000113 li sp,0 +80000300: 00000193 li gp,0 +80000304: 00000213 li tp,0 +80000308: 9abce137 lui sp,0x9abce +8000030c: ef010113 addi sp,sp,-272 # 9abcdef0 <_end+0x1abcce30> +80000310: fff060e3 bltu zero,t6,800002f0 <_start+0x2f0> +80000314: 00000113 li sp,0 +80000318: 00000193 li gp,0 +8000031c: 00000213 li tp,0 +80000320: 000b2023 sw zero,0(s6) +80000324: 002b2223 sw sp,4(s6) +80000328: 003b2423 sw gp,8(s6) +8000032c: 004b2623 sw tp,12(s6) +80000330: 00001517 auipc a0,0x1 +80000334: cf050513 addi a0,a0,-784 # 80001020 +80000338: 00001597 auipc a1,0x1 +8000033c: d8858593 addi a1,a1,-632 # 800010c0 <_end> +80000340: f0100637 lui a2,0xf0100 +80000344: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee6c> + +80000348 : +80000348: 02b50663 beq a0,a1,80000374 +8000034c: 00c52683 lw a3,12(a0) +80000350: 00d62023 sw a3,0(a2) +80000354: 00852683 lw a3,8(a0) +80000358: 00d62023 sw a3,0(a2) +8000035c: 00452683 lw a3,4(a0) +80000360: 00d62023 sw a3,0(a2) +80000364: 00052683 lw a3,0(a0) +80000368: 00d62023 sw a3,0(a2) +8000036c: 01050513 addi a0,a0,16 +80000370: fd9ff06f j 80000348 + +80000374 : +80000374: f0100537 lui a0,0xf0100 +80000378: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee60> +8000037c: 00052023 sw zero,0(a0) +80000380: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: 0001 nop + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff + +80001058 : +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff + +80001074 : +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff + +800010ac : +800010ac: ffff 0xffff +800010ae: ffff 0xffff + +800010b0 : +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff diff --git a/src/test/resources/asm/I-BNE-01.elf.objdump b/src/test/resources/asm/I-BNE-01.elf.objdump new file mode 100644 index 0000000..d976a5d --- /dev/null +++ b/src/test/resources/asm/I-BNE-01.elf.objdump @@ -0,0 +1,358 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-BNE-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef3f> +80000028: 80000437 lui s0,0x80000 +8000002c: 00000f93 li t6,0 +80000030: 00419463 bne gp,tp,80000038 <_start+0x38> +80000034: 001fef93 ori t6,t6,1 +80000038: 00519463 bne gp,t0,80000040 <_start+0x40> +8000003c: 002fef93 ori t6,t6,2 +80000040: 00619463 bne gp,t1,80000048 <_start+0x48> +80000044: 004fef93 ori t6,t6,4 +80000048: 00719463 bne gp,t2,80000050 <_start+0x50> +8000004c: 008fef93 ori t6,t6,8 +80000050: 00819463 bne gp,s0,80000058 <_start+0x58> +80000054: 010fef93 ori t6,t6,16 +80000058: 00312023 sw gp,0(sp) +8000005c: 00412223 sw tp,4(sp) +80000060: 00512423 sw t0,8(sp) +80000064: 00612623 sw t1,12(sp) +80000068: 00712823 sw t2,16(sp) +8000006c: 00812a23 sw s0,20(sp) +80000070: 01f12c23 sw t6,24(sp) +80000074: 00001097 auipc ra,0x1 +80000078: f9008093 addi ra,ra,-112 # 80001004 +8000007c: 00001117 auipc sp,0x1 +80000080: fc010113 addi sp,sp,-64 # 8000103c +80000084: 0000a303 lw t1,0(ra) +80000088: 00000393 li t2,0 +8000008c: 00100413 li s0,1 +80000090: fff00493 li s1,-1 +80000094: 80000537 lui a0,0x80000 +80000098: fff50513 addi a0,a0,-1 # 7fffffff <_end+0xffffef3f> +8000009c: 800005b7 lui a1,0x80000 +800000a0: 00000f93 li t6,0 +800000a4: 00731463 bne t1,t2,800000ac <_start+0xac> +800000a8: 001fef93 ori t6,t6,1 +800000ac: 00831463 bne t1,s0,800000b4 <_start+0xb4> +800000b0: 002fef93 ori t6,t6,2 +800000b4: 00931463 bne t1,s1,800000bc <_start+0xbc> +800000b8: 004fef93 ori t6,t6,4 +800000bc: 00a31463 bne t1,a0,800000c4 <_start+0xc4> +800000c0: 008fef93 ori t6,t6,8 +800000c4: 00b31463 bne t1,a1,800000cc <_start+0xcc> +800000c8: 010fef93 ori t6,t6,16 +800000cc: 00612023 sw t1,0(sp) +800000d0: 00712223 sw t2,4(sp) +800000d4: 00812423 sw s0,8(sp) +800000d8: 00912623 sw s1,12(sp) +800000dc: 00a12823 sw a0,16(sp) +800000e0: 00b12a23 sw a1,20(sp) +800000e4: 01f12c23 sw t6,24(sp) +800000e8: 00001097 auipc ra,0x1 +800000ec: f2008093 addi ra,ra,-224 # 80001008 +800000f0: 00001117 auipc sp,0x1 +800000f4: f6810113 addi sp,sp,-152 # 80001058 +800000f8: 0000a603 lw a2,0(ra) +800000fc: 00000693 li a3,0 +80000100: 00100713 li a4,1 +80000104: fff00793 li a5,-1 +80000108: 80000837 lui a6,0x80000 +8000010c: fff80813 addi a6,a6,-1 # 7fffffff <_end+0xffffef3f> +80000110: 800008b7 lui a7,0x80000 +80000114: 00000f93 li t6,0 +80000118: 00d61463 bne a2,a3,80000120 <_start+0x120> +8000011c: 001fef93 ori t6,t6,1 +80000120: 00e61463 bne a2,a4,80000128 <_start+0x128> +80000124: 002fef93 ori t6,t6,2 +80000128: 00f61463 bne a2,a5,80000130 <_start+0x130> +8000012c: 004fef93 ori t6,t6,4 +80000130: 01061463 bne a2,a6,80000138 <_start+0x138> +80000134: 008fef93 ori t6,t6,8 +80000138: 01161463 bne a2,a7,80000140 <_start+0x140> +8000013c: 010fef93 ori t6,t6,16 +80000140: 00c12023 sw a2,0(sp) +80000144: 00d12223 sw a3,4(sp) +80000148: 00e12423 sw a4,8(sp) +8000014c: 00f12623 sw a5,12(sp) +80000150: 01012823 sw a6,16(sp) +80000154: 01112a23 sw a7,20(sp) +80000158: 01f12c23 sw t6,24(sp) +8000015c: 00001097 auipc ra,0x1 +80000160: eb008093 addi ra,ra,-336 # 8000100c +80000164: 00001117 auipc sp,0x1 +80000168: f1010113 addi sp,sp,-240 # 80001074 +8000016c: 0000a903 lw s2,0(ra) +80000170: 00000993 li s3,0 +80000174: 00100a13 li s4,1 +80000178: fff00a93 li s5,-1 +8000017c: 80000b37 lui s6,0x80000 +80000180: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef3f> +80000184: 80000bb7 lui s7,0x80000 +80000188: 00000f93 li t6,0 +8000018c: 01391463 bne s2,s3,80000194 <_start+0x194> +80000190: 001fef93 ori t6,t6,1 +80000194: 01491463 bne s2,s4,8000019c <_start+0x19c> +80000198: 002fef93 ori t6,t6,2 +8000019c: 01591463 bne s2,s5,800001a4 <_start+0x1a4> +800001a0: 004fef93 ori t6,t6,4 +800001a4: 01691463 bne s2,s6,800001ac <_start+0x1ac> +800001a8: 008fef93 ori t6,t6,8 +800001ac: 01791463 bne s2,s7,800001b4 <_start+0x1b4> +800001b0: 010fef93 ori t6,t6,16 +800001b4: 01212023 sw s2,0(sp) +800001b8: 01312223 sw s3,4(sp) +800001bc: 01412423 sw s4,8(sp) +800001c0: 01512623 sw s5,12(sp) +800001c4: 01612823 sw s6,16(sp) +800001c8: 01712a23 sw s7,20(sp) +800001cc: 01f12c23 sw t6,24(sp) +800001d0: 00001097 auipc ra,0x1 +800001d4: e4008093 addi ra,ra,-448 # 80001010 +800001d8: 00001117 auipc sp,0x1 +800001dc: eb810113 addi sp,sp,-328 # 80001090 +800001e0: 0000ac03 lw s8,0(ra) +800001e4: 00000c93 li s9,0 +800001e8: 00100d13 li s10,1 +800001ec: fff00d93 li s11,-1 +800001f0: 80000e37 lui t3,0x80000 +800001f4: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef3f> +800001f8: 80000eb7 lui t4,0x80000 +800001fc: 00000f93 li t6,0 +80000200: 019c1463 bne s8,s9,80000208 <_start+0x208> +80000204: 001fef93 ori t6,t6,1 +80000208: 01ac1463 bne s8,s10,80000210 <_start+0x210> +8000020c: 002fef93 ori t6,t6,2 +80000210: 01bc1463 bne s8,s11,80000218 <_start+0x218> +80000214: 004fef93 ori t6,t6,4 +80000218: 01cc1463 bne s8,t3,80000220 <_start+0x220> +8000021c: 008fef93 ori t6,t6,8 +80000220: 01dc1463 bne s8,t4,80000228 <_start+0x228> +80000224: 010fef93 ori t6,t6,16 +80000228: 01812023 sw s8,0(sp) +8000022c: 01912223 sw s9,4(sp) +80000230: 01a12423 sw s10,8(sp) +80000234: 01b12623 sw s11,12(sp) +80000238: 01c12823 sw t3,16(sp) +8000023c: 01d12a23 sw t4,20(sp) +80000240: 01f12c23 sw t6,24(sp) +80000244: 00001d97 auipc s11,0x1 +80000248: e68d8d93 addi s11,s11,-408 # 800010ac +8000024c: 00000093 li ra,0 +80000250: 00100113 li sp,1 +80000254: fff00193 li gp,-1 +80000258: 80000237 lui tp,0x80000 +8000025c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef3f> +80000260: 800002b7 lui t0,0x80000 +80000264: 00000f93 li t6,0 +80000268: 00009463 bnez ra,80000270 <_start+0x270> +8000026c: 001fef93 ori t6,t6,1 +80000270: 00011463 bnez sp,80000278 <_start+0x278> +80000274: 002fef93 ori t6,t6,2 +80000278: 00019463 bnez gp,80000280 <_start+0x280> +8000027c: 004fef93 ori t6,t6,4 +80000280: 00021463 bnez tp,80000288 <_start+0x288> +80000284: 008fef93 ori t6,t6,8 +80000288: 00029463 bnez t0,80000290 <_start+0x290> +8000028c: 010fef93 ori t6,t6,16 +80000290: 00101463 bne zero,ra,80000298 <_start+0x298> +80000294: 020fef93 ori t6,t6,32 +80000298: 00201463 bne zero,sp,800002a0 <_start+0x2a0> +8000029c: 040fef93 ori t6,t6,64 +800002a0: 00301463 bne zero,gp,800002a8 <_start+0x2a8> +800002a4: 080fef93 ori t6,t6,128 +800002a8: 00401463 bne zero,tp,800002b0 <_start+0x2b0> +800002ac: 100fef93 ori t6,t6,256 +800002b0: 00501463 bne zero,t0,800002b8 <_start+0x2b8> +800002b4: 200fef93 ori t6,t6,512 +800002b8: 01fda023 sw t6,0(s11) +800002bc: 00001a97 auipc s5,0x1 +800002c0: d58a8a93 addi s5,s5,-680 # 80001014 +800002c4: 00001b17 auipc s6,0x1 +800002c8: decb0b13 addi s6,s6,-532 # 800010b0 +800002cc: 000aaf83 lw t6,0(s5) +800002d0: fff00113 li sp,-1 +800002d4: fff00193 li gp,-1 +800002d8: 0fedd237 lui tp,0xfedd +800002dc: ba920213 addi tp,tp,-1111 # fedcba9 <_start-0x70123457> +800002e0: 020f9463 bnez t6,80000308 <_start+0x308> +800002e4: 00000113 li sp,0 +800002e8: 00000193 li gp,0 +800002ec: 00000213 li tp,0 +800002f0: 876541b7 lui gp,0x87654 +800002f4: 32118193 addi gp,gp,801 # 87654321 <_end+0x7653261> +800002f8: 020f9463 bnez t6,80000320 <_start+0x320> +800002fc: 00000113 li sp,0 +80000300: 00000193 li gp,0 +80000304: 00000213 li tp,0 +80000308: 9abce137 lui sp,0x9abce +8000030c: ef010113 addi sp,sp,-272 # 9abcdef0 <_end+0x1abcce30> +80000310: fe0f90e3 bnez t6,800002f0 <_start+0x2f0> +80000314: 00000113 li sp,0 +80000318: 00000193 li gp,0 +8000031c: 00000213 li tp,0 +80000320: 000b2023 sw zero,0(s6) +80000324: 002b2223 sw sp,4(s6) +80000328: 003b2423 sw gp,8(s6) +8000032c: 004b2623 sw tp,12(s6) +80000330: 00001517 auipc a0,0x1 +80000334: cf050513 addi a0,a0,-784 # 80001020 +80000338: 00001597 auipc a1,0x1 +8000033c: d8858593 addi a1,a1,-632 # 800010c0 <_end> +80000340: f0100637 lui a2,0xf0100 +80000344: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee6c> + +80000348 : +80000348: 02b50663 beq a0,a1,80000374 +8000034c: 00c52683 lw a3,12(a0) +80000350: 00d62023 sw a3,0(a2) +80000354: 00852683 lw a3,8(a0) +80000358: 00d62023 sw a3,0(a2) +8000035c: 00452683 lw a3,4(a0) +80000360: 00d62023 sw a3,0(a2) +80000364: 00052683 lw a3,0(a0) +80000368: 00d62023 sw a3,0(a2) +8000036c: 01050513 addi a0,a0,16 +80000370: fd9ff06f j 80000348 + +80000374 : +80000374: f0100537 lui a0,0xf0100 +80000378: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee60> +8000037c: 00052023 sw zero,0(a0) +80000380: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff + +80001058 : +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff + +80001074 : +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff + +800010ac : +800010ac: ffff 0xffff +800010ae: ffff 0xffff + +800010b0 : +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff diff --git a/src/test/resources/asm/I-CSRRC-01.elf.objdump b/src/test/resources/asm/I-CSRRC-01.elf.objdump new file mode 100644 index 0000000..125a2d2 --- /dev/null +++ b/src/test/resources/asm/I-CSRRC-01.elf.objdump @@ -0,0 +1,188 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-CSRRC-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001797 auipc a5,0x1 +80000004: 00078793 mv a5,a5 +80000008: 00100093 li ra,1 +8000000c: 00000113 li sp,0 +80000010: 7ff101b7 lui gp,0x7ff10 +80000014: fff18193 addi gp,gp,-1 # 7ff0ffff <_start-0xf0001> +80000018: 80000237 lui tp,0x80000 +8000001c: fff00293 li t0,-1 +80000020: 34029073 csrw mscratch,t0 +80000024: 3400b0f3 csrrc ra,mscratch,ra +80000028: 340290f3 csrrw ra,mscratch,t0 +8000002c: 34013173 csrrc sp,mscratch,sp +80000030: 34029173 csrrw sp,mscratch,t0 +80000034: 3401b1f3 csrrc gp,mscratch,gp +80000038: 340291f3 csrrw gp,mscratch,t0 +8000003c: 34023273 csrrc tp,mscratch,tp +80000040: 34029273 csrrw tp,mscratch,t0 +80000044: 3402b2f3 csrrc t0,mscratch,t0 +80000048: 340012f3 csrrw t0,mscratch,zero +8000004c: 0007a023 sw zero,0(a5) # 80001000 +80000050: 0017a223 sw ra,4(a5) +80000054: 0027a423 sw sp,8(a5) +80000058: 0037a623 sw gp,12(a5) +8000005c: 0047a823 sw tp,16(a5) +80000060: 0057aa23 sw t0,20(a5) +80000064: 00001297 auipc t0,0x1 +80000068: fb428293 addi t0,t0,-76 # 80001018 +8000006c: 00100593 li a1,1 +80000070: 00000613 li a2,0 +80000074: 7ff106b7 lui a3,0x7ff10 +80000078: fff68693 addi a3,a3,-1 # 7ff0ffff <_start-0xf0001> +8000007c: 80000737 lui a4,0x80000 +80000080: fff00793 li a5,-1 +80000084: 34079073 csrw mscratch,a5 +80000088: 3405b5f3 csrrc a1,mscratch,a1 +8000008c: 34063673 csrrc a2,mscratch,a2 +80000090: 3406b6f3 csrrc a3,mscratch,a3 +80000094: 34073773 csrrc a4,mscratch,a4 +80000098: 3407b7f3 csrrc a5,mscratch,a5 +8000009c: 34003873 csrrc a6,mscratch,zero +800000a0: 00b2a023 sw a1,0(t0) +800000a4: 00c2a223 sw a2,4(t0) +800000a8: 00d2a423 sw a3,8(t0) +800000ac: 00e2a623 sw a4,12(t0) +800000b0: 00f2a823 sw a5,16(t0) +800000b4: 0102aa23 sw a6,20(t0) +800000b8: 00001d17 auipc s10,0x1 +800000bc: f78d0d13 addi s10,s10,-136 # 80001030 +800000c0: 12345ab7 lui s5,0x12345 +800000c4: 678a8a93 addi s5,s5,1656 # 12345678 <_start-0x6dcba988> +800000c8: fff00a13 li s4,-1 +800000cc: 340a1073 csrw mscratch,s4 +800000d0: 340abb73 csrrc s6,mscratch,s5 +800000d4: 340b3af3 csrrc s5,mscratch,s6 +800000d8: 340a1bf3 csrrw s7,mscratch,s4 +800000dc: 340bbc73 csrrc s8,mscratch,s7 +800000e0: 34003cf3 csrrc s9,mscratch,zero +800000e4: 015d2023 sw s5,0(s10) +800000e8: 016d2223 sw s6,4(s10) +800000ec: 017d2423 sw s7,8(s10) +800000f0: 018d2623 sw s8,12(s10) +800000f4: 019d2823 sw s9,16(s10) +800000f8: 00001097 auipc ra,0x1 +800000fc: f4c08093 addi ra,ra,-180 # 80001044 +80000100: 42727f37 lui t5,0x42727 +80000104: e6ff0f13 addi t5,t5,-401 # 42726e6f <_start-0x3d8d9191> +80000108: 340f1073 csrw mscratch,t5 +8000010c: 340f3073 csrc mscratch,t5 +80000110: 0000a023 sw zero,0(ra) +80000114: 01e0a223 sw t5,4(ra) +80000118: 00001117 auipc sp,0x1 +8000011c: f3410113 addi sp,sp,-204 # 8000104c +80000120: f7ff9fb7 lui t6,0xf7ff9 +80000124: 818f8f93 addi t6,t6,-2024 # f7ff8818 <_end+0x77ff77b8> +80000128: 340f9073 csrw mscratch,t6 +8000012c: 34003073 csrc mscratch,zero +80000130: 34003073 csrc mscratch,zero +80000134: 34003ff3 csrrc t6,mscratch,zero +80000138: 00012023 sw zero,0(sp) +8000013c: 01f12223 sw t6,4(sp) +80000140: 00001117 auipc sp,0x1 +80000144: f1410113 addi sp,sp,-236 # 80001054 +80000148: fff00213 li tp,-1 +8000014c: 963852b7 lui t0,0x96385 +80000150: 27428293 addi t0,t0,628 # 96385274 <_end+0x16384214> +80000154: 321653b7 lui t2,0x32165 +80000158: 49838393 addi t2,t2,1176 # 32165498 <_start-0x4de9ab68> +8000015c: 34021073 csrw mscratch,tp +80000160: 3402b2f3 csrrc t0,mscratch,t0 +80000164: 3403b3f3 csrrc t2,mscratch,t2 +80000168: 34043473 csrrc s0,mscratch,s0 +8000016c: 00512023 sw t0,0(sp) +80000170: 00712223 sw t2,4(sp) +80000174: 00812423 sw s0,8(sp) +80000178: 00001517 auipc a0,0x1 +8000017c: e8850513 addi a0,a0,-376 # 80001000 +80000180: 00001597 auipc a1,0x1 +80000184: ee058593 addi a1,a1,-288 # 80001060 <_end> +80000188: f0100637 lui a2,0xf0100 +8000018c: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feecc> + +80000190 : +80000190: 02b50663 beq a0,a1,800001bc +80000194: 00c52683 lw a3,12(a0) +80000198: 00d62023 sw a3,0(a2) +8000019c: 00852683 lw a3,8(a0) +800001a0: 00d62023 sw a3,0(a2) +800001a4: 00452683 lw a3,4(a0) +800001a8: 00d62023 sw a3,0(a2) +800001ac: 00052683 lw a3,0(a0) +800001b0: 00d62023 sw a3,0(a2) +800001b4: 01050513 addi a0,a0,16 +800001b8: fd9ff06f j 80000190 + +800001bc : +800001bc: f0100537 lui a0,0xf0100 +800001c0: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feec0> +800001c4: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff + +80001044 : +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff + +8000104c : +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff + +80001054 : +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff diff --git a/src/test/resources/asm/I-CSRRCI-01.elf.objdump b/src/test/resources/asm/I-CSRRCI-01.elf.objdump new file mode 100644 index 0000000..3699174 --- /dev/null +++ b/src/test/resources/asm/I-CSRRCI-01.elf.objdump @@ -0,0 +1,119 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-CSRRCI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001797 auipc a5,0x1 +80000004: 00078793 mv a5,a5 +80000008: fff00413 li s0,-1 +8000000c: 34041073 csrw mscratch,s0 +80000010: 3400f0f3 csrrci ra,mscratch,1 +80000014: 340410f3 csrrw ra,mscratch,s0 +80000018: 34007173 csrrci sp,mscratch,0 +8000001c: 34041173 csrrw sp,mscratch,s0 +80000020: 340ff1f3 csrrci gp,mscratch,31 +80000024: 340411f3 csrrw gp,mscratch,s0 +80000028: 34087273 csrrci tp,mscratch,16 +8000002c: 34041273 csrrw tp,mscratch,s0 +80000030: 3407f2f3 csrrci t0,mscratch,15 +80000034: 340412f3 csrrw t0,mscratch,s0 +80000038: 0007a023 sw zero,0(a5) # 80001000 +8000003c: 0017a223 sw ra,4(a5) +80000040: 0027a423 sw sp,8(a5) +80000044: 0037a623 sw gp,12(a5) +80000048: 0047a823 sw tp,16(a5) +8000004c: 0057aa23 sw t0,20(a5) +80000050: 0087ac23 sw s0,24(a5) +80000054: 00001297 auipc t0,0x1 +80000058: fc828293 addi t0,t0,-56 # 8000101c +8000005c: fff00413 li s0,-1 +80000060: 34041073 csrw mscratch,s0 +80000064: 3400f5f3 csrrci a1,mscratch,1 +80000068: 34007673 csrrci a2,mscratch,0 +8000006c: 340ff6f3 csrrci a3,mscratch,31 +80000070: 34087773 csrrci a4,mscratch,16 +80000074: 3407f7f3 csrrci a5,mscratch,15 +80000078: 34007873 csrrci a6,mscratch,0 +8000007c: 00b2a023 sw a1,0(t0) +80000080: 00c2a223 sw a2,4(t0) +80000084: 00d2a423 sw a3,8(t0) +80000088: 00e2a623 sw a4,12(t0) +8000008c: 00f2a823 sw a5,16(t0) +80000090: 0102aa23 sw a6,20(t0) +80000094: 0082ac23 sw s0,24(t0) +80000098: 00001097 auipc ra,0x1 +8000009c: fa008093 addi ra,ra,-96 # 80001038 +800000a0: 32165a37 lui s4,0x32165 +800000a4: 498a0a13 addi s4,s4,1176 # 32165498 <_start-0x4de9ab68> +800000a8: 340a1073 csrw mscratch,s4 +800000ac: 3407f073 csrci mscratch,15 +800000b0: 340a1a73 csrrw s4,mscratch,s4 +800000b4: 0000a023 sw zero,0(ra) +800000b8: 0140a223 sw s4,4(ra) +800000bc: 00001517 auipc a0,0x1 +800000c0: f4450513 addi a0,a0,-188 # 80001000 +800000c4: 00001597 auipc a1,0x1 +800000c8: f7c58593 addi a1,a1,-132 # 80001040 <_end> +800000cc: f0100637 lui a2,0xf0100 +800000d0: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feeec> + +800000d4 : +800000d4: 02b50663 beq a0,a1,80000100 +800000d8: 00c52683 lw a3,12(a0) +800000dc: 00d62023 sw a3,0(a2) +800000e0: 00852683 lw a3,8(a0) +800000e4: 00d62023 sw a3,0(a2) +800000e8: 00452683 lw a3,4(a0) +800000ec: 00d62023 sw a3,0(a2) +800000f0: 00052683 lw a3,0(a0) +800000f4: 00d62023 sw a3,0(a2) +800000f8: 01050513 addi a0,a0,16 +800000fc: fd9ff06f j 800000d4 + +80000100 : +80000100: f0100537 lui a0,0xf0100 +80000104: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feee0> +80000108: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff + +8000101c : +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff diff --git a/src/test/resources/asm/I-CSRRS-01.elf.objdump b/src/test/resources/asm/I-CSRRS-01.elf.objdump new file mode 100644 index 0000000..7b672b2 --- /dev/null +++ b/src/test/resources/asm/I-CSRRS-01.elf.objdump @@ -0,0 +1,187 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-CSRRS-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001797 auipc a5,0x1 +80000004: 00078793 mv a5,a5 +80000008: 00100093 li ra,1 +8000000c: 00000113 li sp,0 +80000010: 7ff101b7 lui gp,0x7ff10 +80000014: fff18193 addi gp,gp,-1 # 7ff0ffff <_start-0xf0001> +80000018: 80000237 lui tp,0x80000 +8000001c: fff00293 li t0,-1 +80000020: 34001073 csrw mscratch,zero +80000024: 3400a0f3 csrrs ra,mscratch,ra +80000028: 340010f3 csrrw ra,mscratch,zero +8000002c: 34012173 csrrs sp,mscratch,sp +80000030: 34001173 csrrw sp,mscratch,zero +80000034: 3401a1f3 csrrs gp,mscratch,gp +80000038: 340011f3 csrrw gp,mscratch,zero +8000003c: 34022273 csrrs tp,mscratch,tp +80000040: 34001273 csrrw tp,mscratch,zero +80000044: 3402a2f3 csrrs t0,mscratch,t0 +80000048: 340012f3 csrrw t0,mscratch,zero +8000004c: 0007a023 sw zero,0(a5) # 80001000 +80000050: 0017a223 sw ra,4(a5) +80000054: 0027a423 sw sp,8(a5) +80000058: 0037a623 sw gp,12(a5) +8000005c: 0047a823 sw tp,16(a5) +80000060: 0057aa23 sw t0,20(a5) +80000064: 00001297 auipc t0,0x1 +80000068: fb428293 addi t0,t0,-76 # 80001018 +8000006c: 00100593 li a1,1 +80000070: 00000613 li a2,0 +80000074: 7ff106b7 lui a3,0x7ff10 +80000078: fff68693 addi a3,a3,-1 # 7ff0ffff <_start-0xf0001> +8000007c: 80000737 lui a4,0x80000 +80000080: fff00793 li a5,-1 +80000084: 34001073 csrw mscratch,zero +80000088: 3405a5f3 csrrs a1,mscratch,a1 +8000008c: 34062673 csrrs a2,mscratch,a2 +80000090: 3406a6f3 csrrs a3,mscratch,a3 +80000094: 34072773 csrrs a4,mscratch,a4 +80000098: 3407a7f3 csrrs a5,mscratch,a5 +8000009c: 34002873 csrr a6,mscratch +800000a0: 00b2a023 sw a1,0(t0) +800000a4: 00c2a223 sw a2,4(t0) +800000a8: 00d2a423 sw a3,8(t0) +800000ac: 00e2a623 sw a4,12(t0) +800000b0: 00f2a823 sw a5,16(t0) +800000b4: 0102aa23 sw a6,20(t0) +800000b8: 00001d17 auipc s10,0x1 +800000bc: f78d0d13 addi s10,s10,-136 # 80001030 +800000c0: 12345ab7 lui s5,0x12345 +800000c4: 678a8a93 addi s5,s5,1656 # 12345678 <_start-0x6dcba988> +800000c8: 34001073 csrw mscratch,zero +800000cc: 340aab73 csrrs s6,mscratch,s5 +800000d0: 340b2bf3 csrrs s7,mscratch,s6 +800000d4: 34001bf3 csrrw s7,mscratch,zero +800000d8: 340bac73 csrrs s8,mscratch,s7 +800000dc: 34002cf3 csrr s9,mscratch +800000e0: 015d2023 sw s5,0(s10) +800000e4: 016d2223 sw s6,4(s10) +800000e8: 017d2423 sw s7,8(s10) +800000ec: 018d2623 sw s8,12(s10) +800000f0: 019d2823 sw s9,16(s10) +800000f4: 00001097 auipc ra,0x1 +800000f8: f5008093 addi ra,ra,-176 # 80001044 +800000fc: 42727f37 lui t5,0x42727 +80000100: e6ff0f13 addi t5,t5,-401 # 42726e6f <_start-0x3d8d9191> +80000104: 340f1073 csrw mscratch,t5 +80000108: 340f2073 csrs mscratch,t5 +8000010c: 0000a023 sw zero,0(ra) +80000110: 01e0a223 sw t5,4(ra) +80000114: 00001117 auipc sp,0x1 +80000118: f3810113 addi sp,sp,-200 # 8000104c +8000011c: f7ff9fb7 lui t6,0xf7ff9 +80000120: 818f8f93 addi t6,t6,-2024 # f7ff8818 <_end+0x77ff77b8> +80000124: 340f9073 csrw mscratch,t6 +80000128: 34002073 csrr zero,mscratch +8000012c: 34002073 csrr zero,mscratch +80000130: 34002ff3 csrr t6,mscratch +80000134: 00012023 sw zero,0(sp) +80000138: 01f12223 sw t6,4(sp) +8000013c: 00001117 auipc sp,0x1 +80000140: f1810113 addi sp,sp,-232 # 80001054 +80000144: 321653b7 lui t2,0x32165 +80000148: 49838393 addi t2,t2,1176 # 32165498 <_start-0x4de9ab68> +8000014c: 963852b7 lui t0,0x96385 +80000150: 27428293 addi t0,t0,628 # 96385274 <_end+0x16384214> +80000154: 34001073 csrw mscratch,zero +80000158: 3402a2f3 csrrs t0,mscratch,t0 +8000015c: 3403a3f3 csrrs t2,mscratch,t2 +80000160: 34042473 csrrs s0,mscratch,s0 +80000164: 00512023 sw t0,0(sp) +80000168: 00712223 sw t2,4(sp) +8000016c: 00812423 sw s0,8(sp) +80000170: 00001517 auipc a0,0x1 +80000174: e9050513 addi a0,a0,-368 # 80001000 +80000178: 00001597 auipc a1,0x1 +8000017c: ee858593 addi a1,a1,-280 # 80001060 <_end> +80000180: f0100637 lui a2,0xf0100 +80000184: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feecc> + +80000188 : +80000188: 02b50663 beq a0,a1,800001b4 +8000018c: 00c52683 lw a3,12(a0) +80000190: 00d62023 sw a3,0(a2) +80000194: 00852683 lw a3,8(a0) +80000198: 00d62023 sw a3,0(a2) +8000019c: 00452683 lw a3,4(a0) +800001a0: 00d62023 sw a3,0(a2) +800001a4: 00052683 lw a3,0(a0) +800001a8: 00d62023 sw a3,0(a2) +800001ac: 01050513 addi a0,a0,16 +800001b0: fd9ff06f j 80000188 + +800001b4 : +800001b4: f0100537 lui a0,0xf0100 +800001b8: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feec0> +800001bc: 00052023 sw zero,0(a0) +800001c0: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff + +80001044 : +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff + +8000104c : +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff + +80001054 : +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff diff --git a/src/test/resources/asm/I-CSRRSI-01.elf.objdump b/src/test/resources/asm/I-CSRRSI-01.elf.objdump new file mode 100644 index 0000000..64cd496 --- /dev/null +++ b/src/test/resources/asm/I-CSRRSI-01.elf.objdump @@ -0,0 +1,116 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-CSRRSI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001797 auipc a5,0x1 +80000004: 00078793 mv a5,a5 +80000008: 34001073 csrw mscratch,zero +8000000c: 3400e0f3 csrrsi ra,mscratch,1 +80000010: 340010f3 csrrw ra,mscratch,zero +80000014: 34006173 csrrsi sp,mscratch,0 +80000018: 34001173 csrrw sp,mscratch,zero +8000001c: 340fe1f3 csrrsi gp,mscratch,31 +80000020: 340011f3 csrrw gp,mscratch,zero +80000024: 34086273 csrrsi tp,mscratch,16 +80000028: 34001273 csrrw tp,mscratch,zero +8000002c: 3407e2f3 csrrsi t0,mscratch,15 +80000030: 340012f3 csrrw t0,mscratch,zero +80000034: 0007a023 sw zero,0(a5) # 80001000 +80000038: 0017a223 sw ra,4(a5) +8000003c: 0027a423 sw sp,8(a5) +80000040: 0037a623 sw gp,12(a5) +80000044: 0047a823 sw tp,16(a5) +80000048: 0057aa23 sw t0,20(a5) +8000004c: 00001297 auipc t0,0x1 +80000050: fcc28293 addi t0,t0,-52 # 80001018 +80000054: 34001073 csrw mscratch,zero +80000058: 3400e5f3 csrrsi a1,mscratch,1 +8000005c: 34006673 csrrsi a2,mscratch,0 +80000060: 340fe6f3 csrrsi a3,mscratch,31 +80000064: 34086773 csrrsi a4,mscratch,16 +80000068: 3407e7f3 csrrsi a5,mscratch,15 +8000006c: 34006873 csrrsi a6,mscratch,0 +80000070: 0002a023 sw zero,0(t0) +80000074: 00b2a223 sw a1,4(t0) +80000078: 00c2a423 sw a2,8(t0) +8000007c: 00d2a623 sw a3,12(t0) +80000080: 00e2a823 sw a4,16(t0) +80000084: 00f2aa23 sw a5,20(t0) +80000088: 0102ac23 sw a6,24(t0) +8000008c: 00001097 auipc ra,0x1 +80000090: fa808093 addi ra,ra,-88 # 80001034 +80000094: 32165a37 lui s4,0x32165 +80000098: 498a0a13 addi s4,s4,1176 # 32165498 <_start-0x4de9ab68> +8000009c: 340a1073 csrw mscratch,s4 +800000a0: 3407e073 csrsi mscratch,15 +800000a4: 340a1af3 csrrw s5,mscratch,s4 +800000a8: 0000a023 sw zero,0(ra) +800000ac: 0150a223 sw s5,4(ra) +800000b0: 0140a423 sw s4,8(ra) +800000b4: 00001517 auipc a0,0x1 +800000b8: f4c50513 addi a0,a0,-180 # 80001000 +800000bc: 00001597 auipc a1,0x1 +800000c0: f8458593 addi a1,a1,-124 # 80001040 <_end> +800000c4: f0100637 lui a2,0xf0100 +800000c8: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feeec> + +800000cc : +800000cc: 02b50663 beq a0,a1,800000f8 +800000d0: 00c52683 lw a3,12(a0) +800000d4: 00d62023 sw a3,0(a2) +800000d8: 00852683 lw a3,8(a0) +800000dc: 00d62023 sw a3,0(a2) +800000e0: 00452683 lw a3,4(a0) +800000e4: 00d62023 sw a3,0(a2) +800000e8: 00052683 lw a3,0(a0) +800000ec: 00d62023 sw a3,0(a2) +800000f0: 01050513 addi a0,a0,16 +800000f4: fd9ff06f j 800000cc + +800000f8 : +800000f8: f0100537 lui a0,0xf0100 +800000fc: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feee0> +80000100: 00052023 sw zero,0(a0) + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff + +80001034 : +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff diff --git a/src/test/resources/asm/I-CSRRW-01.elf.objdump b/src/test/resources/asm/I-CSRRW-01.elf.objdump new file mode 100644 index 0000000..3791434 --- /dev/null +++ b/src/test/resources/asm/I-CSRRW-01.elf.objdump @@ -0,0 +1,145 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-CSRRW-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001797 auipc a5,0x1 +80000004: 00078793 mv a5,a5 +80000008: 00100093 li ra,1 +8000000c: 00000193 li gp,0 +80000010: fff00293 li t0,-1 +80000014: 80000db7 lui s11,0x80000 +80000018: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffefbf> +8000001c: 80000eb7 lui t4,0x80000 +80000020: 34001073 csrw mscratch,zero +80000024: 34009173 csrrw sp,mscratch,ra +80000028: 34019273 csrrw tp,mscratch,gp +8000002c: 34029373 csrrw t1,mscratch,t0 +80000030: 340d9e73 csrrw t3,mscratch,s11 +80000034: 340e9f73 csrrw t5,mscratch,t4 +80000038: 34001ff3 csrrw t6,mscratch,zero +8000003c: 0027a023 sw sp,0(a5) # 80001000 +80000040: 0047a223 sw tp,4(a5) +80000044: 0067a423 sw t1,8(a5) +80000048: 01c7a623 sw t3,12(a5) +8000004c: 01e7a823 sw t5,16(a5) +80000050: 01f7aa23 sw t6,20(a5) +80000054: 00001d17 auipc s10,0x1 +80000058: fc4d0d13 addi s10,s10,-60 # 80001018 +8000005c: 123450b7 lui ra,0x12345 +80000060: 67808093 addi ra,ra,1656 # 12345678 <_start-0x6dcba988> +80000064: 9abce137 lui sp,0x9abce +80000068: ef010113 addi sp,sp,-272 # 9abcdef0 <_end+0x1abcceb0> +8000006c: 34009073 csrw mscratch,ra +80000070: 340111f3 csrrw gp,mscratch,sp +80000074: 34019273 csrrw tp,mscratch,gp +80000078: 340212f3 csrrw t0,mscratch,tp +8000007c: 34001373 csrrw t1,mscratch,zero +80000080: 003d2023 sw gp,0(s10) +80000084: 004d2223 sw tp,4(s10) +80000088: 005d2423 sw t0,8(s10) +8000008c: 006d2623 sw t1,12(s10) +80000090: 00001097 auipc ra,0x1 +80000094: f9808093 addi ra,ra,-104 # 80001028 +80000098: 42727137 lui sp,0x42727 +8000009c: e6f10113 addi sp,sp,-401 # 42726e6f <_start-0x3d8d9191> +800000a0: 34011073 csrw mscratch,sp +800000a4: 34001073 csrw mscratch,zero +800000a8: 0000a023 sw zero,0(ra) +800000ac: 00001117 auipc sp,0x1 +800000b0: f8010113 addi sp,sp,-128 # 8000102c +800000b4: f7ff9db7 lui s11,0xf7ff9 +800000b8: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff77d8> +800000bc: 340d9073 csrw mscratch,s11 +800000c0: 34001073 csrw mscratch,zero +800000c4: 34001073 csrw mscratch,zero +800000c8: 340012f3 csrrw t0,mscratch,zero +800000cc: 00012023 sw zero,0(sp) +800000d0: 00512223 sw t0,4(sp) +800000d4: 00001117 auipc sp,0x1 +800000d8: f6010113 addi sp,sp,-160 # 80001034 +800000dc: 321653b7 lui t2,0x32165 +800000e0: 49838393 addi t2,t2,1176 # 32165498 <_start-0x4de9ab68> +800000e4: 14726337 lui t1,0x14726 +800000e8: 83630313 addi t1,t1,-1994 # 14725836 <_start-0x6b8da7ca> +800000ec: 963852b7 lui t0,0x96385 +800000f0: 27428293 addi t0,t0,628 # 96385274 <_end+0x16384234> +800000f4: 34031073 csrw mscratch,t1 +800000f8: 340292f3 csrrw t0,mscratch,t0 +800000fc: 340393f3 csrrw t2,mscratch,t2 +80000100: 34001473 csrrw s0,mscratch,zero +80000104: 00512023 sw t0,0(sp) +80000108: 00712223 sw t2,4(sp) +8000010c: 00812423 sw s0,8(sp) +80000110: 00001517 auipc a0,0x1 +80000114: ef050513 addi a0,a0,-272 # 80001000 +80000118: 00001597 auipc a1,0x1 +8000011c: f2858593 addi a1,a1,-216 # 80001040 <_end> +80000120: f0100637 lui a2,0xf0100 +80000124: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feeec> + +80000128 : +80000128: 02b50663 beq a0,a1,80000154 +8000012c: 00c52683 lw a3,12(a0) +80000130: 00d62023 sw a3,0(a2) +80000134: 00852683 lw a3,8(a0) +80000138: 00d62023 sw a3,0(a2) +8000013c: 00452683 lw a3,4(a0) +80000140: 00d62023 sw a3,0(a2) +80000144: 00052683 lw a3,0(a0) +80000148: 00d62023 sw a3,0(a2) +8000014c: 01050513 addi a0,a0,16 +80000150: fd9ff06f j 80000128 + +80000154 : +80000154: f0100537 lui a0,0xf0100 +80000158: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feee0> +8000015c: 00052023 sw zero,0(a0) +80000160: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff + +8000102c : +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff + +80001034 : +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff diff --git a/src/test/resources/asm/I-CSRRWI-01.elf.objdump b/src/test/resources/asm/I-CSRRWI-01.elf.objdump new file mode 100644 index 0000000..b1307ce --- /dev/null +++ b/src/test/resources/asm/I-CSRRWI-01.elf.objdump @@ -0,0 +1,74 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-CSRRWI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001797 auipc a5,0x1 +80000004: 00078793 mv a5,a5 +80000008: 34001073 csrw mscratch,zero +8000000c: 3400d173 csrrwi sp,mscratch,1 +80000010: 34005273 csrrwi tp,mscratch,0 +80000014: 340fd373 csrrwi t1,mscratch,31 +80000018: 3407de73 csrrwi t3,mscratch,15 +8000001c: 34085f73 csrrwi t5,mscratch,16 +80000020: 34005ff3 csrrwi t6,mscratch,0 +80000024: 0007a023 sw zero,0(a5) # 80001000 +80000028: 0027a223 sw sp,4(a5) +8000002c: 0047a423 sw tp,8(a5) +80000030: 0067a623 sw t1,12(a5) +80000034: 01c7a823 sw t3,16(a5) +80000038: 01e7aa23 sw t5,20(a5) +8000003c: 01f7ac23 sw t6,24(a5) +80000040: 00001097 auipc ra,0x1 +80000044: fdc08093 addi ra,ra,-36 # 8000101c +80000048: 3407d073 csrwi mscratch,15 +8000004c: 34005073 csrwi mscratch,0 +80000050: 0000a023 sw zero,0(ra) +80000054: 00001517 auipc a0,0x1 +80000058: fac50513 addi a0,a0,-84 # 80001000 +8000005c: 00001597 auipc a1,0x1 +80000060: fc458593 addi a1,a1,-60 # 80001020 <_end> +80000064: f0100637 lui a2,0xf0100 +80000068: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +8000006c : +8000006c: 02b50663 beq a0,a1,80000098 +80000070: 00c52683 lw a3,12(a0) +80000074: 00d62023 sw a3,0(a2) +80000078: 00852683 lw a3,8(a0) +8000007c: 00d62023 sw a3,0(a2) +80000080: 00452683 lw a3,4(a0) +80000084: 00d62023 sw a3,0(a2) +80000088: 00052683 lw a3,0(a0) +8000008c: 00d62023 sw a3,0(a2) +80000090: 01050513 addi a0,a0,16 +80000094: fd9ff06f j 8000006c + +80000098 : +80000098: f0100537 lui a0,0xf0100 +8000009c: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +800000a0: 00052023 sw zero,0(a0) + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff + +8000101c : +8000101c: ffff 0xffff +8000101e: ffff 0xffff diff --git a/src/test/resources/asm/I-DELAY_SLOTS-01.elf.objdump b/src/test/resources/asm/I-DELAY_SLOTS-01.elf.objdump new file mode 100644 index 0000000..00fc5fb --- /dev/null +++ b/src/test/resources/asm/I-DELAY_SLOTS-01.elf.objdump @@ -0,0 +1,136 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-DELAY_SLOTS-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 11111137 lui sp,0x11111 +8000000c: 11110113 addi sp,sp,273 # 11111111 <_start-0x6eeeeeef> +80000010: 0080006f j 80000018 <_start+0x18> +80000014: 00000113 li sp,0 +80000018: 0020a023 sw sp,0(ra) # 80001000 +8000001c: 00001097 auipc ra,0x1 +80000020: fe808093 addi ra,ra,-24 # 80001004 +80000024: 22222137 lui sp,0x22222 +80000028: 22210113 addi sp,sp,546 # 22222222 <_start-0x5dddddde> +8000002c: 00000217 auipc tp,0x0 +80000030: 01020213 addi tp,tp,16 # 8000003c <_start+0x3c> +80000034: 00020067 jr tp +80000038: 00000113 li sp,0 +8000003c: 0020a023 sw sp,0(ra) +80000040: 00001097 auipc ra,0x1 +80000044: fc808093 addi ra,ra,-56 # 80001008 +80000048: 00500293 li t0,5 +8000004c: 00600313 li t1,6 +80000050: 33333137 lui sp,0x33333 +80000054: 33310113 addi sp,sp,819 # 33333333 <_start-0x4ccccccd> +80000058: 00528463 beq t0,t0,80000060 <_start+0x60> +8000005c: 00000113 li sp,0 +80000060: 0020a023 sw sp,0(ra) +80000064: 00001097 auipc ra,0x1 +80000068: fa808093 addi ra,ra,-88 # 8000100c +8000006c: 00500293 li t0,5 +80000070: 00600313 li t1,6 +80000074: 44444137 lui sp,0x44444 +80000078: 44410113 addi sp,sp,1092 # 44444444 <_start-0x3bbbbbbc> +8000007c: 00629463 bne t0,t1,80000084 <_start+0x84> +80000080: 00000113 li sp,0 +80000084: 0020a023 sw sp,0(ra) +80000088: 00001097 auipc ra,0x1 +8000008c: f8808093 addi ra,ra,-120 # 80001010 +80000090: 00500293 li t0,5 +80000094: 00600313 li t1,6 +80000098: 55555137 lui sp,0x55555 +8000009c: 55510113 addi sp,sp,1365 # 55555555 <_start-0x2aaaaaab> +800000a0: 0062c463 blt t0,t1,800000a8 <_start+0xa8> +800000a4: 00000113 li sp,0 +800000a8: 0020a023 sw sp,0(ra) +800000ac: 00001097 auipc ra,0x1 +800000b0: f6808093 addi ra,ra,-152 # 80001014 +800000b4: 00500293 li t0,5 +800000b8: 00600313 li t1,6 +800000bc: 66666137 lui sp,0x66666 +800000c0: 66610113 addi sp,sp,1638 # 66666666 <_start-0x1999999a> +800000c4: 0062e463 bltu t0,t1,800000cc <_start+0xcc> +800000c8: 00000113 li sp,0 +800000cc: 0020a023 sw sp,0(ra) +800000d0: 00001097 auipc ra,0x1 +800000d4: f4808093 addi ra,ra,-184 # 80001018 +800000d8: 00500293 li t0,5 +800000dc: 00600313 li t1,6 +800000e0: 77777137 lui sp,0x77777 +800000e4: 77710113 addi sp,sp,1911 # 77777777 <_start-0x8888889> +800000e8: 00535463 ble t0,t1,800000f0 <_start+0xf0> +800000ec: 00000113 li sp,0 +800000f0: 0020a023 sw sp,0(ra) +800000f4: 00001097 auipc ra,0x1 +800000f8: f2808093 addi ra,ra,-216 # 8000101c +800000fc: 00500293 li t0,5 +80000100: 00600313 li t1,6 +80000104: 88889137 lui sp,0x88889 +80000108: 88810113 addi sp,sp,-1912 # 88888888 <_end+0x8887868> +8000010c: 00537463 bleu t0,t1,80000114 <_start+0x114> +80000110: 00000113 li sp,0 +80000114: 0020a023 sw sp,0(ra) +80000118: 00001517 auipc a0,0x1 +8000011c: ee850513 addi a0,a0,-280 # 80001000 +80000120: 00001597 auipc a1,0x1 +80000124: f0058593 addi a1,a1,-256 # 80001020 <_end> +80000128: f0100637 lui a2,0xf0100 +8000012c: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +80000130 : +80000130: 02b50663 beq a0,a1,8000015c +80000134: 00c52683 lw a3,12(a0) +80000138: 00d62023 sw a3,0(a2) +8000013c: 00852683 lw a3,8(a0) +80000140: 00d62023 sw a3,0(a2) +80000144: 00452683 lw a3,4(a0) +80000148: 00d62023 sw a3,0(a2) +8000014c: 00052683 lw a3,0(a0) +80000150: 00d62023 sw a3,0(a2) +80000154: 01050513 addi a0,a0,16 +80000158: fd9ff06f j 80000130 + +8000015c : +8000015c: f0100537 lui a0,0xf0100 +80000160: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +80000164: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff + +8000101c : +8000101c: ffff 0xffff +8000101e: ffff 0xffff diff --git a/src/test/resources/asm/I-EBREAK-01.elf.objdump b/src/test/resources/asm/I-EBREAK-01.elf.objdump new file mode 100644 index 0000000..9634d82 --- /dev/null +++ b/src/test/resources/asm/I-EBREAK-01.elf.objdump @@ -0,0 +1,69 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-EBREAK-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00000097 auipc ra,0x0 +80000004: 02c08093 addi ra,ra,44 # 8000002c <_trap_handler> +80000008: 30509ff3 csrrw t6,mtvec,ra +8000000c: 00001097 auipc ra,0x1 +80000010: ff408093 addi ra,ra,-12 # 80001000 +80000014: 11111137 lui sp,0x11111 +80000018: 11110113 addi sp,sp,273 # 11111111 <_start-0x6eeeeeef> +8000001c: 00100073 ebreak +80000020: 0000a023 sw zero,0(ra) +80000024: 305f9073 csrw mtvec,t6 +80000028: 0280006f j 80000050 + +8000002c <_trap_handler>: +8000002c: 34102f73 csrr t5,mepc +80000030: 004f0f13 addi t5,t5,4 +80000034: 341f1073 csrw mepc,t5 +80000038: 34202f73 csrr t5,mcause +8000003c: 01e0a023 sw t5,0(ra) +80000040: 0020a223 sw sp,4(ra) +80000044: 0000a423 sw zero,8(ra) +80000048: 00c08093 addi ra,ra,12 +8000004c: 30200073 mret + +80000050 : +80000050: 00001517 auipc a0,0x1 +80000054: fb050513 addi a0,a0,-80 # 80001000 +80000058: 00001597 auipc a1,0x1 +8000005c: fb858593 addi a1,a1,-72 # 80001010 <_end> +80000060: f0100637 lui a2,0xf0100 +80000064: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef1c> + +80000068 : +80000068: 02b50663 beq a0,a1,80000094 +8000006c: 00c52683 lw a3,12(a0) +80000070: 00d62023 sw a3,0(a2) +80000074: 00852683 lw a3,8(a0) +80000078: 00d62023 sw a3,0(a2) +8000007c: 00452683 lw a3,4(a0) +80000080: 00d62023 sw a3,0(a2) +80000084: 00052683 lw a3,0(a0) +80000088: 00d62023 sw a3,0(a2) +8000008c: 01050513 addi a0,a0,16 +80000090: fd9ff06f j 80000068 + +80000094 : +80000094: f0100537 lui a0,0xf0100 +80000098: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef10> +8000009c: 00052023 sw zero,0(a0) +800000a0: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff diff --git a/src/test/resources/asm/I-ECALL-01.elf.objdump b/src/test/resources/asm/I-ECALL-01.elf.objdump new file mode 100644 index 0000000..d98bfec --- /dev/null +++ b/src/test/resources/asm/I-ECALL-01.elf.objdump @@ -0,0 +1,69 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-ECALL-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00000097 auipc ra,0x0 +80000004: 02c08093 addi ra,ra,44 # 8000002c <_trap_handler> +80000008: 30509ff3 csrrw t6,mtvec,ra +8000000c: 00001097 auipc ra,0x1 +80000010: ff408093 addi ra,ra,-12 # 80001000 +80000014: 11111137 lui sp,0x11111 +80000018: 11110113 addi sp,sp,273 # 11111111 <_start-0x6eeeeeef> +8000001c: 00000073 ecall +80000020: 0000a023 sw zero,0(ra) +80000024: 305f9073 csrw mtvec,t6 +80000028: 0280006f j 80000050 + +8000002c <_trap_handler>: +8000002c: 34102f73 csrr t5,mepc +80000030: 004f0f13 addi t5,t5,4 +80000034: 341f1073 csrw mepc,t5 +80000038: 34202f73 csrr t5,mcause +8000003c: 01e0a023 sw t5,0(ra) +80000040: 0020a223 sw sp,4(ra) +80000044: 0000a423 sw zero,8(ra) +80000048: 00c08093 addi ra,ra,12 +8000004c: 30200073 mret + +80000050 : +80000050: 00001517 auipc a0,0x1 +80000054: fb050513 addi a0,a0,-80 # 80001000 +80000058: 00001597 auipc a1,0x1 +8000005c: fb858593 addi a1,a1,-72 # 80001010 <_end> +80000060: f0100637 lui a2,0xf0100 +80000064: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef1c> + +80000068 : +80000068: 02b50663 beq a0,a1,80000094 +8000006c: 00c52683 lw a3,12(a0) +80000070: 00d62023 sw a3,0(a2) +80000074: 00852683 lw a3,8(a0) +80000078: 00d62023 sw a3,0(a2) +8000007c: 00452683 lw a3,4(a0) +80000080: 00d62023 sw a3,0(a2) +80000084: 00052683 lw a3,0(a0) +80000088: 00d62023 sw a3,0(a2) +8000008c: 01050513 addi a0,a0,16 +80000090: fd9ff06f j 80000068 + +80000094 : +80000094: f0100537 lui a0,0xf0100 +80000098: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef10> +8000009c: 00052023 sw zero,0(a0) +800000a0: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff diff --git a/src/test/resources/asm/I-ENDIANESS-01.elf.objdump b/src/test/resources/asm/I-ENDIANESS-01.elf.objdump new file mode 100644 index 0000000..536bfd0 --- /dev/null +++ b/src/test/resources/asm/I-ENDIANESS-01.elf.objdump @@ -0,0 +1,80 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-ENDIANESS-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001817 auipc a6,0x1 +80000004: 00480813 addi a6,a6,4 # 80001004 +80000008: 00001897 auipc a7,0x1 +8000000c: 00888893 addi a7,a7,8 # 80001010 +80000010: 00082083 lw ra,0(a6) +80000014: 00085103 lhu sp,0(a6) +80000018: 00285183 lhu gp,2(a6) +8000001c: fff84203 lbu tp,-1(a6) +80000020: 00084283 lbu t0,0(a6) +80000024: 00184303 lbu t1,1(a6) +80000028: 00284383 lbu t2,2(a6) +8000002c: 00384403 lbu s0,3(a6) +80000030: 0018a023 sw ra,0(a7) +80000034: 0028a223 sw sp,4(a7) +80000038: 0038a423 sw gp,8(a7) +8000003c: 0048a623 sw tp,12(a7) +80000040: 0058a823 sw t0,16(a7) +80000044: 0068aa23 sw t1,20(a7) +80000048: 0078ac23 sw t2,24(a7) +8000004c: 0088ae23 sw s0,28(a7) +80000050: 00001517 auipc a0,0x1 +80000054: fc050513 addi a0,a0,-64 # 80001010 +80000058: 00001597 auipc a1,0x1 +8000005c: fd858593 addi a1,a1,-40 # 80001030 <_end> +80000060: f0100637 lui a2,0xf0100 +80000064: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feefc> + +80000068 : +80000068: 02b50663 beq a0,a1,80000094 +8000006c: 00c52683 lw a3,12(a0) +80000070: 00d62023 sw a3,0(a2) +80000074: 00852683 lw a3,8(a0) +80000078: 00d62023 sw a3,0(a2) +8000007c: 00452683 lw a3,4(a0) +80000080: 00d62023 sw a3,0(a2) +80000084: 00052683 lw a3,0(a0) +80000088: 00d62023 sw a3,0(a2) +8000008c: 01050513 addi a0,a0,16 +80000090: fd9ff06f j 80000068 + +80000094 : +80000094: f0100537 lui a0,0xf0100 +80000098: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feef0> +8000009c: 00052023 sw zero,0(a0) +800000a0: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 89abcdef jal s11,7ffbd09a <_start-0x42f66> + +80001004 : +80001004: 01234567 0x1234567 + ... + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff diff --git a/src/test/resources/asm/I-FENCE.I-01.elf.objdump b/src/test/resources/asm/I-FENCE.I-01.elf.objdump new file mode 100644 index 0000000..99e1ea7 --- /dev/null +++ b/src/test/resources/asm/I-FENCE.I-01.elf.objdump @@ -0,0 +1,76 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-FENCE.I-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001817 auipc a6,0x1 +80000004: 00480813 addi a6,a6,4 # 80001004 +80000008: 00001897 auipc a7,0x1 +8000000c: 00888893 addi a7,a7,8 # 80001010 +80000010: 00000193 li gp,0 +80000014: 00082083 lw ra,0(a6) +80000018: 00482103 lw sp,4(a6) +8000001c: 00001a17 auipc s4,0x1 +80000020: fe4a0a13 addi s4,s4,-28 # 80001000 +80000024: 00000a97 auipc s5,0x0 +80000028: 014a8a93 addi s5,s5,20 # 80000038 +8000002c: 000a2783 lw a5,0(s4) +80000030: 00faa023 sw a5,0(s5) +80000034: 0000100f fence.i + +80000038 : +80000038: 00000137 lui sp,0x0 +8000003c: 0018a023 sw ra,0(a7) +80000040: 0028a223 sw sp,4(a7) +80000044: 0038a423 sw gp,8(a7) +80000048: 00f8a623 sw a5,12(a7) +8000004c: 00001517 auipc a0,0x1 +80000050: fc450513 addi a0,a0,-60 # 80001010 +80000054: 00001597 auipc a1,0x1 +80000058: fcc58593 addi a1,a1,-52 # 80001020 <_end> +8000005c: f0100637 lui a2,0xf0100 +80000060: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +80000064 : +80000064: 02b50663 beq a0,a1,80000090 +80000068: 00c52683 lw a3,12(a0) +8000006c: 00d62023 sw a3,0(a2) +80000070: 00852683 lw a3,8(a0) +80000074: 00d62023 sw a3,0(a2) +80000078: 00452683 lw a3,4(a0) +8000007c: 00d62023 sw a3,0(a2) +80000080: 00052683 lw a3,0(a0) +80000084: 00d62023 sw a3,0(a2) +80000088: 01050513 addi a0,a0,16 +8000008c: fd9ff06f j 80000064 + +80000090 : +80000090: f0100537 lui a0,0xf0100 +80000094: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +80000098: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 001101b3 add gp,sp,ra + +80001004 : +80001004: 0030 addi a2,sp,8 +80001006: 0000 unimp +80001008: 0012 c.slli zero,0x4 +8000100a: 0000 unimp +8000100c: 0000 unimp + ... + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff diff --git a/src/test/resources/asm/I-IO.elf.objdump b/src/test/resources/asm/I-IO.elf.objdump new file mode 100644 index 0000000..73994c1 --- /dev/null +++ b/src/test/resources/asm/I-IO.elf.objdump @@ -0,0 +1,344 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-IO.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef1f> +80000028: 80000437 lui s0,0x80000 +8000002c: 00418233 add tp,gp,tp +80000030: 005182b3 add t0,gp,t0 +80000034: 00618333 add t1,gp,t1 +80000038: 007183b3 add t2,gp,t2 +8000003c: 00818433 add s0,gp,s0 +80000040: 00312023 sw gp,0(sp) +80000044: 00412223 sw tp,4(sp) +80000048: 00512423 sw t0,8(sp) +8000004c: 00612623 sw t1,12(sp) +80000050: 00712823 sw t2,16(sp) +80000054: 00812a23 sw s0,20(sp) +80000058: 00001097 auipc ra,0x1 +8000005c: fac08093 addi ra,ra,-84 # 80001004 +80000060: 00001117 auipc sp,0x1 +80000064: fe810113 addi sp,sp,-24 # 80001048 +80000068: 0000a403 lw s0,0(ra) +8000006c: 00000493 li s1,0 +80000070: 00100513 li a0,1 +80000074: fff00593 li a1,-1 +80000078: 80000637 lui a2,0x80000 +8000007c: fff60613 addi a2,a2,-1 # 7fffffff <_end+0xffffef1f> +80000080: 800006b7 lui a3,0x80000 +80000084: 009404b3 add s1,s0,s1 +80000088: 00a40533 add a0,s0,a0 +8000008c: 00b405b3 add a1,s0,a1 +80000090: 00c40633 add a2,s0,a2 +80000094: 00d406b3 add a3,s0,a3 +80000098: 00812023 sw s0,0(sp) +8000009c: 00912223 sw s1,4(sp) +800000a0: 00a12423 sw a0,8(sp) +800000a4: 00b12623 sw a1,12(sp) +800000a8: 00c12823 sw a2,16(sp) +800000ac: 00d12a23 sw a3,20(sp) +800000b0: 00001097 auipc ra,0x1 +800000b4: f5808093 addi ra,ra,-168 # 80001008 +800000b8: 00001117 auipc sp,0x1 +800000bc: fa810113 addi sp,sp,-88 # 80001060 +800000c0: 0000a683 lw a3,0(ra) +800000c4: 00000713 li a4,0 +800000c8: 00100793 li a5,1 +800000cc: fff00813 li a6,-1 +800000d0: 800008b7 lui a7,0x80000 +800000d4: fff88893 addi a7,a7,-1 # 7fffffff <_end+0xffffef1f> +800000d8: 80000937 lui s2,0x80000 +800000dc: 00e68733 add a4,a3,a4 +800000e0: 00f687b3 add a5,a3,a5 +800000e4: 01068833 add a6,a3,a6 +800000e8: 011688b3 add a7,a3,a7 +800000ec: 01268933 add s2,a3,s2 +800000f0: 00d12023 sw a3,0(sp) +800000f4: 00e12223 sw a4,4(sp) +800000f8: 00f12423 sw a5,8(sp) +800000fc: 01012623 sw a6,12(sp) +80000100: 01112823 sw a7,16(sp) +80000104: 01212a23 sw s2,20(sp) +80000108: 00001097 auipc ra,0x1 +8000010c: f0408093 addi ra,ra,-252 # 8000100c +80000110: 00001117 auipc sp,0x1 +80000114: f6810113 addi sp,sp,-152 # 80001078 +80000118: 0000a903 lw s2,0(ra) +8000011c: 00000993 li s3,0 +80000120: 00100a13 li s4,1 +80000124: fff00a93 li s5,-1 +80000128: 80000b37 lui s6,0x80000 +8000012c: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef1f> +80000130: 80000bb7 lui s7,0x80000 +80000134: 013909b3 add s3,s2,s3 +80000138: 01490a33 add s4,s2,s4 +8000013c: 01590ab3 add s5,s2,s5 +80000140: 01690b33 add s6,s2,s6 +80000144: 01790bb3 add s7,s2,s7 +80000148: 01212023 sw s2,0(sp) +8000014c: 01312223 sw s3,4(sp) +80000150: 01412423 sw s4,8(sp) +80000154: 01512623 sw s5,12(sp) +80000158: 01612823 sw s6,16(sp) +8000015c: 01712a23 sw s7,20(sp) +80000160: 00001097 auipc ra,0x1 +80000164: eb008093 addi ra,ra,-336 # 80001010 +80000168: 00001117 auipc sp,0x1 +8000016c: f2810113 addi sp,sp,-216 # 80001090 +80000170: 0000ab83 lw s7,0(ra) +80000174: 00000c13 li s8,0 +80000178: 00100c93 li s9,1 +8000017c: fff00d13 li s10,-1 +80000180: 80000db7 lui s11,0x80000 +80000184: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef1f> +80000188: 80000e37 lui t3,0x80000 +8000018c: 018b8c33 add s8,s7,s8 +80000190: 019b8cb3 add s9,s7,s9 +80000194: 01ab8d33 add s10,s7,s10 +80000198: 01bb8db3 add s11,s7,s11 +8000019c: 01cb8e33 add t3,s7,t3 +800001a0: 01712023 sw s7,0(sp) +800001a4: 01812223 sw s8,4(sp) +800001a8: 01912423 sw s9,8(sp) +800001ac: 01a12623 sw s10,12(sp) +800001b0: 01b12823 sw s11,16(sp) +800001b4: 01c12a23 sw t3,20(sp) +800001b8: 00001c97 auipc s9,0x1 +800001bc: e5cc8c93 addi s9,s9,-420 # 80001014 +800001c0: 00001d17 auipc s10,0x1 +800001c4: ee8d0d13 addi s10,s10,-280 # 800010a8 +800001c8: 000cae03 lw t3,0(s9) +800001cc: 00100d93 li s11,1 +800001d0: 01be0eb3 add t4,t3,s11 +800001d4: 01be8f33 add t5,t4,s11 +800001d8: 01bf0fb3 add t6,t5,s11 +800001dc: 01bf80b3 add ra,t6,s11 +800001e0: 01b08133 add sp,ra,s11 +800001e4: 01b101b3 add gp,sp,s11 +800001e8: 01bd2023 sw s11,0(s10) +800001ec: 01cd2223 sw t3,4(s10) +800001f0: 01dd2423 sw t4,8(s10) +800001f4: 01ed2623 sw t5,12(s10) +800001f8: 01fd2823 sw t6,16(s10) +800001fc: 001d2a23 sw ra,20(s10) +80000200: 002d2c23 sw sp,24(s10) +80000204: 003d2e23 sw gp,28(s10) +80000208: 00001097 auipc ra,0x1 +8000020c: e1008093 addi ra,ra,-496 # 80001018 +80000210: 00001117 auipc sp,0x1 +80000214: eb810113 addi sp,sp,-328 # 800010c8 +80000218: 0000ae03 lw t3,0(ra) +8000021c: f7ff9db7 lui s11,0xf7ff9 +80000220: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +80000224: 01be0033 add zero,t3,s11 +80000228: 00012023 sw zero,0(sp) +8000022c: 00001097 auipc ra,0x1 +80000230: df008093 addi ra,ra,-528 # 8000101c +80000234: 00001117 auipc sp,0x1 +80000238: e9810113 addi sp,sp,-360 # 800010cc +8000023c: 0000ae03 lw t3,0(ra) +80000240: f7ff9db7 lui s11,0xf7ff9 +80000244: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +80000248: 01be0033 add zero,t3,s11 +8000024c: 000002b3 add t0,zero,zero +80000250: 00012023 sw zero,0(sp) +80000254: 00512223 sw t0,4(sp) +80000258: 00001097 auipc ra,0x1 +8000025c: dc808093 addi ra,ra,-568 # 80001020 +80000260: 00001117 auipc sp,0x1 +80000264: e7410113 addi sp,sp,-396 # 800010d4 +80000268: 0000a183 lw gp,0(ra) +8000026c: 00018233 add tp,gp,zero +80000270: 000202b3 add t0,tp,zero +80000274: 00500333 add t1,zero,t0 +80000278: 00030733 add a4,t1,zero +8000027c: 000707b3 add a5,a4,zero +80000280: 00078833 add a6,a5,zero +80000284: 01000cb3 add s9,zero,a6 +80000288: 01900d33 add s10,zero,s9 +8000028c: 000d0db3 add s11,s10,zero +80000290: 00412023 sw tp,0(sp) +80000294: 01a12223 sw s10,4(sp) +80000298: 01b12423 sw s11,8(sp) +8000029c: 00001517 auipc a0,0x1 +800002a0: d9450513 addi a0,a0,-620 # 80001030 +800002a4: 00001597 auipc a1,0x1 +800002a8: e3c58593 addi a1,a1,-452 # 800010e0 <_end> +800002ac: f0100637 lui a2,0xf0100 +800002b0: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +800002b4 : +800002b4: 02b50663 beq a0,a1,800002e0 +800002b8: 00c52683 lw a3,12(a0) +800002bc: 00d62023 sw a3,0(a2) +800002c0: 00852683 lw a3,8(a0) +800002c4: 00d62023 sw a3,0(a2) +800002c8: 00452683 lw a3,4(a0) +800002cc: 00d62023 sw a3,0(a2) +800002d0: 00052683 lw a3,0(a0) +800002d4: 00d62023 sw a3,0(a2) +800002d8: 01050513 addi a0,a0,16 +800002dc: fd9ff06f j 800002b4 + +800002e0 : +800002e0: f0100537 lui a0,0xf0100 +800002e4: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +800002e8: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: abcd j 80001606 <_end+0x526> + ... + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 5814 lw a3,48(s0) +80001022: 3692 fld fa3,288(sp) + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff + +800010cc : +800010cc: ffff 0xffff +800010ce: ffff 0xffff +800010d0: ffff 0xffff +800010d2: ffff 0xffff + +800010d4 : +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-JAL-01.elf.objdump b/src/test/resources/asm/I-JAL-01.elf.objdump new file mode 100644 index 0000000..233f6af --- /dev/null +++ b/src/test/resources/asm/I-JAL-01.elf.objdump @@ -0,0 +1,227 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-JAL-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 01008093 addi ra,ra,16 # 80001010 +80000008: 12345137 lui sp,0x12345 +8000000c: 67810113 addi sp,sp,1656 # 12345678 <_start-0x6dcba988> +80000010: 0080006f j 80000018 <_start+0x18> +80000014: 00000113 li sp,0 +80000018: 0000a023 sw zero,0(ra) +8000001c: 0020a223 sw sp,4(ra) +80000020: 00001097 auipc ra,0x1 +80000024: ff808093 addi ra,ra,-8 # 80001018 +80000028: fff00113 li sp,-1 +8000002c: fff00193 li gp,-1 +80000030: 0fedd237 lui tp,0xfedd +80000034: ba920213 addi tp,tp,-1111 # fedcba9 <_start-0x70123457> +80000038: 0280006f j 80000060 <_start+0x60> +8000003c: 00000113 li sp,0 +80000040: 00000193 li gp,0 +80000044: 00000213 li tp,0 +80000048: 876541b7 lui gp,0x87654 +8000004c: 32118193 addi gp,gp,801 # 87654321 <_end+0x76532c1> +80000050: 0280006f j 80000078 <_start+0x78> +80000054: 00000113 li sp,0 +80000058: 00000193 li gp,0 +8000005c: 00000213 li tp,0 +80000060: 9abce137 lui sp,0x9abce +80000064: ef010113 addi sp,sp,-272 # 9abcdef0 <_end+0x1abcce90> +80000068: fe1ff06f j 80000048 <_start+0x48> +8000006c: 00000113 li sp,0 +80000070: 00000193 li gp,0 +80000074: 00000213 li tp,0 +80000078: 0000a023 sw zero,0(ra) +8000007c: 0020a223 sw sp,4(ra) +80000080: 0030a423 sw gp,8(ra) +80000084: 0040a623 sw tp,12(ra) +80000088: 00001497 auipc s1,0x1 +8000008c: f7848493 addi s1,s1,-136 # 80001000 +80000090: 00001517 auipc a0,0x1 +80000094: f9850513 addi a0,a0,-104 # 80001028 +80000098: fff00113 li sp,-1 +8000009c: fff00193 li gp,-1 +800000a0: fff00213 li tp,-1 +800000a4: fff00293 li t0,-1 +800000a8: 55555337 lui t1,0x55555 +800000ac: 55530313 addi t1,t1,1365 # 55555555 <_start-0x2aaaaaab> +800000b0: 0004ac83 lw s9,0(s1) +800000b4: 0044ac03 lw s8,4(s1) +800000b8: 01c000ef jal ra,800000d4 + +800000bc : +800000bc: 222221b7 lui gp,0x22222 +800000c0: 22218193 addi gp,gp,546 # 22222222 <_start-0x5dddddde> +800000c4: 03000fef jal t6,800000f4 + +800000c8 : +800000c8: 444442b7 lui t0,0x44444 +800000cc: 44428293 addi t0,t0,1092 # 44444444 <_start-0x3bbbbbbc> +800000d0: 0440006f j 80000114 +800000d4: 11111137 lui sp,0x11111 +800000d8: 11110113 addi sp,sp,273 # 11111111 <_start-0x6eeeeeef> +800000dc: 00008067 ret +800000e0: 00000113 li sp,0 +800000e4: 00000193 li gp,0 +800000e8: 00000213 li tp,0 +800000ec: 00000293 li t0,0 +800000f0: 00000313 li t1,0 +800000f4: 33333237 lui tp,0x33333 +800000f8: 33320213 addi tp,tp,819 # 33333333 <_start-0x4ccccccd> +800000fc: 000f8067 jr t6 +80000100: 00000113 li sp,0 +80000104: 00000193 li gp,0 +80000108: 00000213 li tp,0 +8000010c: 00000293 li t0,0 +80000110: 00000313 li t1,0 +80000114: 0190c3b3 xor t2,ra,s9 +80000118: 018fc433 xor s0,t6,s8 +8000011c: 00252023 sw sp,0(a0) +80000120: 00352223 sw gp,4(a0) +80000124: 00452423 sw tp,8(a0) +80000128: 00552623 sw t0,12(a0) +8000012c: 00652823 sw t1,16(a0) +80000130: 00752a23 sw t2,20(a0) +80000134: 00852c23 sw s0,24(a0) +80000138: 00001497 auipc s1,0x1 +8000013c: ed048493 addi s1,s1,-304 # 80001008 +80000140: 00001517 auipc a0,0x1 +80000144: f0450513 addi a0,a0,-252 # 80001044 +80000148: fff00113 li sp,-1 +8000014c: fff00193 li gp,-1 +80000150: fff00213 li tp,-1 +80000154: fff00293 li t0,-1 +80000158: fff00313 li t1,-1 +8000015c: 0004ac03 lw s8,0(s1) +80000160: 0044ac83 lw s9,4(s1) +80000164: 0240006f j 80000188 +80000168: 777771b7 lui gp,0x77777 +8000016c: 77718193 addi gp,gp,1911 # 77777777 <_start-0x8888889> +80000170: 000f8067 jr t6 +80000174: 00000113 li sp,0 +80000178: 00000193 li gp,0 +8000017c: 00000213 li tp,0 +80000180: 00000293 li t0,0 +80000184: 00000313 li t1,0 +80000188: 66666137 lui sp,0x66666 +8000018c: 66610113 addi sp,sp,1638 # 66666666 <_start-0x1999999a> +80000190: fd9fffef jal t6,80000168 + +80000194 : +80000194: 88889237 lui tp,0x88889 +80000198: 88820213 addi tp,tp,-1912 # 88888888 <_end+0x8887828> +8000019c: 010000ef jal ra,800001ac + +800001a0 : +800001a0: aaaab337 lui t1,0xaaaab +800001a4: aaa30313 addi t1,t1,-1366 # aaaaaaaa <_end+0x2aaa9a4a> +800001a8: 0240006f j 800001cc +800001ac: 9999a2b7 lui t0,0x9999a +800001b0: 99928293 addi t0,t0,-1639 # 99999999 <_end+0x19998939> +800001b4: 00008067 ret +800001b8: 00000113 li sp,0 +800001bc: 00000193 li gp,0 +800001c0: 00000213 li tp,0 +800001c4: 00000293 li t0,0 +800001c8: 00000313 li t1,0 +800001cc: 018fc3b3 xor t2,t6,s8 +800001d0: 0190c433 xor s0,ra,s9 +800001d4: 00252023 sw sp,0(a0) +800001d8: 00352223 sw gp,4(a0) +800001dc: 00452423 sw tp,8(a0) +800001e0: 00552623 sw t0,12(a0) +800001e4: 00652823 sw t1,16(a0) +800001e8: 00752a23 sw t2,20(a0) +800001ec: 00852c23 sw s0,24(a0) +800001f0: 00001517 auipc a0,0x1 +800001f4: e2050513 addi a0,a0,-480 # 80001010 +800001f8: 00001597 auipc a1,0x1 +800001fc: e6858593 addi a1,a1,-408 # 80001060 <_end> +80000200: f0100637 lui a2,0xf0100 +80000204: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feecc> + +80000208 : +80000208: 02b50663 beq a0,a1,80000234 +8000020c: 00c52683 lw a3,12(a0) +80000210: 00d62023 sw a3,0(a2) +80000214: 00852683 lw a3,8(a0) +80000218: 00d62023 sw a3,0(a2) +8000021c: 00452683 lw a3,4(a0) +80000220: 00d62023 sw a3,0(a2) +80000224: 00052683 lw a3,0(a0) +80000228: 00d62023 sw a3,0(a2) +8000022c: 01050513 addi a0,a0,16 +80000230: fd9ff06f j 80000208 + +80000234 : +80000234: f0100537 lui a0,0xf0100 +80000238: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feec0> +8000023c: 00052023 sw zero,0(a0) +80000240: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 00bc addi a5,sp,72 +80001002: 8000 0x8000 +80001004: 00c8 addi a0,sp,68 +80001006: 8000 0x8000 + +80001008 : +80001008: 0194 addi a3,sp,192 +8000100a: 8000 0x8000 +8000100c: 01a0 addi s0,sp,200 +8000100e: 8000 0x8000 + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff + +80001044 : +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff diff --git a/src/test/resources/asm/I-JALR-01.elf.objdump b/src/test/resources/asm/I-JALR-01.elf.objdump new file mode 100644 index 0000000..8505a9c --- /dev/null +++ b/src/test/resources/asm/I-JALR-01.elf.objdump @@ -0,0 +1,289 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-JALR-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 01008093 addi ra,ra,16 # 80001010 +80000008: 12345137 lui sp,0x12345 +8000000c: 67810113 addi sp,sp,1656 # 12345678 <_start-0x6dcba988> +80000010: 00000197 auipc gp,0x0 +80000014: 01018193 addi gp,gp,16 # 80000020 <_start+0x20> +80000018: 00018067 jr gp +8000001c: 00000113 li sp,0 +80000020: 0000a023 sw zero,0(ra) +80000024: 0020a223 sw sp,4(ra) +80000028: 00001097 auipc ra,0x1 +8000002c: ff008093 addi ra,ra,-16 # 80001018 +80000030: fff00113 li sp,-1 +80000034: fff00193 li gp,-1 +80000038: 0fedd237 lui tp,0xfedd +8000003c: ba920213 addi tp,tp,-1111 # fedcba9 <_start-0x70123457> +80000040: 00000f97 auipc t6,0x0 +80000044: 038f8f93 addi t6,t6,56 # 80000078 <_start+0x78> +80000048: 000f8067 jr t6 +8000004c: 00000113 li sp,0 +80000050: 00000193 li gp,0 +80000054: 00000213 li tp,0 +80000058: 876541b7 lui gp,0x87654 +8000005c: 32118193 addi gp,gp,801 # 87654321 <_end+0x76532b1> +80000060: 00000297 auipc t0,0x0 +80000064: 03828293 addi t0,t0,56 # 80000098 <_start+0x98> +80000068: 00028067 jr t0 +8000006c: 00000113 li sp,0 +80000070: 00000193 li gp,0 +80000074: 00000213 li tp,0 +80000078: 9abce137 lui sp,0x9abce +8000007c: ef010113 addi sp,sp,-272 # 9abcdef0 <_end+0x1abcce80> +80000080: 00000797 auipc a5,0x0 +80000084: fd878793 addi a5,a5,-40 # 80000058 <_start+0x58> +80000088: 00078067 jr a5 +8000008c: 00000113 li sp,0 +80000090: 00000193 li gp,0 +80000094: 00000213 li tp,0 +80000098: 0000a023 sw zero,0(ra) +8000009c: 0020a223 sw sp,4(ra) +800000a0: 0030a423 sw gp,8(ra) +800000a4: 0040a623 sw tp,12(ra) +800000a8: 00001497 auipc s1,0x1 +800000ac: f5848493 addi s1,s1,-168 # 80001000 +800000b0: 00001517 auipc a0,0x1 +800000b4: f7850513 addi a0,a0,-136 # 80001028 +800000b8: fff00113 li sp,-1 +800000bc: fff00193 li gp,-1 +800000c0: fff00213 li tp,-1 +800000c4: fff00293 li t0,-1 +800000c8: 55555337 lui t1,0x55555 +800000cc: 55530313 addi t1,t1,1365 # 55555555 <_start-0x2aaaaaab> +800000d0: 0004ac83 lw s9,0(s1) +800000d4: 0044ac03 lw s8,4(s1) +800000d8: 00000397 auipc t2,0x0 +800000dc: 03438393 addi t2,t2,52 # 8000010c +800000e0: 000380e7 jalr t2 + +800000e4 : +800000e4: 222221b7 lui gp,0x22222 +800000e8: 22218193 addi gp,gp,546 # 22222222 <_start-0x5dddddde> +800000ec: 00000417 auipc s0,0x0 +800000f0: 04040413 addi s0,s0,64 # 8000012c +800000f4: 00040fe7 jalr t6,s0 + +800000f8 : +800000f8: 444442b7 lui t0,0x44444 +800000fc: 44428293 addi t0,t0,1092 # 44444444 <_start-0x3bbbbbbc> +80000100: 00000f17 auipc t5,0x0 +80000104: 04cf0f13 addi t5,t5,76 # 8000014c +80000108: 000f0067 jr t5 +8000010c: 11111137 lui sp,0x11111 +80000110: 11110113 addi sp,sp,273 # 11111111 <_start-0x6eeeeeef> +80000114: 00008067 ret +80000118: 00000113 li sp,0 +8000011c: 00000193 li gp,0 +80000120: 00000213 li tp,0 +80000124: 00000293 li t0,0 +80000128: 00000313 li t1,0 +8000012c: 33333237 lui tp,0x33333 +80000130: 33320213 addi tp,tp,819 # 33333333 <_start-0x4ccccccd> +80000134: 000f8067 jr t6 +80000138: 00000113 li sp,0 +8000013c: 00000193 li gp,0 +80000140: 00000213 li tp,0 +80000144: 00000293 li t0,0 +80000148: 00000313 li t1,0 +8000014c: 0190c3b3 xor t2,ra,s9 +80000150: 018fc433 xor s0,t6,s8 +80000154: 00252023 sw sp,0(a0) +80000158: 00352223 sw gp,4(a0) +8000015c: 00452423 sw tp,8(a0) +80000160: 00552623 sw t0,12(a0) +80000164: 00652823 sw t1,16(a0) +80000168: 00752a23 sw t2,20(a0) +8000016c: 00852c23 sw s0,24(a0) +80000170: 00001497 auipc s1,0x1 +80000174: e9848493 addi s1,s1,-360 # 80001008 +80000178: 00001517 auipc a0,0x1 +8000017c: ecc50513 addi a0,a0,-308 # 80001044 +80000180: fff00113 li sp,-1 +80000184: fff00193 li gp,-1 +80000188: fff00213 li tp,-1 +8000018c: fff00293 li t0,-1 +80000190: fff00313 li t1,-1 +80000194: 0004ac03 lw s8,0(s1) +80000198: 0044ac83 lw s9,4(s1) +8000019c: 00000797 auipc a5,0x0 +800001a0: 02c78793 addi a5,a5,44 # 800001c8 +800001a4: 00078067 jr a5 +800001a8: 777771b7 lui gp,0x77777 +800001ac: 77718193 addi gp,gp,1911 # 77777777 <_start-0x8888889> +800001b0: 001f8067 jr 1(t6) +800001b4: 00000113 li sp,0 +800001b8: 00000193 li gp,0 +800001bc: 00000213 li tp,0 +800001c0: 00000293 li t0,0 +800001c4: 00000313 li t1,0 +800001c8: 66666137 lui sp,0x66666 +800001cc: 66610113 addi sp,sp,1638 # 66666666 <_start-0x1999999a> +800001d0: 00000f97 auipc t6,0x0 +800001d4: fd9f8f93 addi t6,t6,-39 # 800001a9 +800001d8: 000f8fe7 jalr t6,t6 + +800001dc : +800001dc: 88889237 lui tp,0x88889 +800001e0: 88820213 addi tp,tp,-1912 # 88888888 <_end+0x8887818> +800001e4: 00000097 auipc ra,0x0 +800001e8: 02108093 addi ra,ra,33 # 80000205 +800001ec: 000080e7 jalr ra + +800001f0 : +800001f0: aaaab337 lui t1,0xaaaab +800001f4: aaa30313 addi t1,t1,-1366 # aaaaaaaa <_end+0x2aaa9a3a> +800001f8: 00000f17 auipc t5,0x0 +800001fc: 02cf0f13 addi t5,t5,44 # 80000224 +80000200: 000f0067 jr t5 +80000204: 9999a2b7 lui t0,0x9999a +80000208: 99928293 addi t0,t0,-1639 # 99999999 <_end+0x19998929> +8000020c: 00108067 jr 1(ra) +80000210: 00000113 li sp,0 +80000214: 00000193 li gp,0 +80000218: 00000213 li tp,0 +8000021c: 00000293 li t0,0 +80000220: 00000313 li t1,0 +80000224: 018fc3b3 xor t2,t6,s8 +80000228: 0190c433 xor s0,ra,s9 +8000022c: 00252023 sw sp,0(a0) +80000230: 00352223 sw gp,4(a0) +80000234: 00452423 sw tp,8(a0) +80000238: 00552623 sw t0,12(a0) +8000023c: 00652823 sw t1,16(a0) +80000240: 00752a23 sw t2,20(a0) +80000244: 00852c23 sw s0,24(a0) +80000248: 00001097 auipc ra,0x1 +8000024c: e1808093 addi ra,ra,-488 # 80001060 +80000250: 11111237 lui tp,0x11111 +80000254: 11120213 addi tp,tp,273 # 11111111 <_start-0x6eeeeeef> +80000258: 00000197 auipc gp,0x0 +8000025c: 00f18193 addi gp,gp,15 # 80000267 +80000260: 00118067 jr 1(gp) +80000264: 00000213 li tp,0 +80000268: 222222b7 lui t0,0x22222 +8000026c: 22228293 addi t0,t0,546 # 22222222 <_start-0x5dddddde> +80000270: 00000197 auipc gp,0x0 +80000274: 01118193 addi gp,gp,17 # 80000281 +80000278: fff18067 jr -1(gp) +8000027c: 00000293 li t0,0 +80000280: 33333337 lui t1,0x33333 +80000284: 33330313 addi t1,t1,819 # 33333333 <_start-0x4ccccccd> +80000288: 00000197 auipc gp,0x0 +8000028c: 81118193 addi gp,gp,-2031 # 7ffffa99 <_start-0x567> +80000290: 7ff18067 jr 2047(gp) +80000294: 00000313 li t1,0 +80000298: 444443b7 lui t2,0x44444 +8000029c: 44438393 addi t2,t2,1092 # 44444444 <_start-0x3bbbbbbc> +800002a0: 00001197 auipc gp,0x1 +800002a4: 81018193 addi gp,gp,-2032 # 80000ab0 +800002a8: 80018067 jr -2048(gp) +800002ac: 00000393 li t2,0 +800002b0: 0040a023 sw tp,0(ra) +800002b4: 0050a223 sw t0,4(ra) +800002b8: 0060a423 sw t1,8(ra) +800002bc: 0070a623 sw t2,12(ra) +800002c0: 00001517 auipc a0,0x1 +800002c4: d5050513 addi a0,a0,-688 # 80001010 +800002c8: 00001597 auipc a1,0x1 +800002cc: da858593 addi a1,a1,-600 # 80001070 <_end> +800002d0: f0100637 lui a2,0xf0100 +800002d4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +800002d8 : +800002d8: 02b50663 beq a0,a1,80000304 +800002dc: 00c52683 lw a3,12(a0) +800002e0: 00d62023 sw a3,0(a2) +800002e4: 00852683 lw a3,8(a0) +800002e8: 00d62023 sw a3,0(a2) +800002ec: 00452683 lw a3,4(a0) +800002f0: 00d62023 sw a3,0(a2) +800002f4: 00052683 lw a3,0(a0) +800002f8: 00d62023 sw a3,0(a2) +800002fc: 01050513 addi a0,a0,16 +80000300: fd9ff06f j 800002d8 + +80000304 : +80000304: f0100537 lui a0,0xf0100 +80000308: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +8000030c: 00052023 sw zero,0(a0) +80000310: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 00e4 addi s1,sp,76 +80001002: 8000 0x8000 +80001004: 00f8 addi a4,sp,76 +80001006: 8000 0x8000 + +80001008 : +80001008: 01dc addi a5,sp,196 +8000100a: 8000 0x8000 +8000100c: 01f0 addi a2,sp,204 +8000100e: 8000 0x8000 + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff + +80001044 : +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff diff --git a/src/test/resources/asm/I-LB-01.elf.objdump b/src/test/resources/asm/I-LB-01.elf.objdump new file mode 100644 index 0000000..ab8c109 --- /dev/null +++ b/src/test/resources/asm/I-LB-01.elf.objdump @@ -0,0 +1,289 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-LB-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001f97 auipc t6,0x1 +80000004: 000f8f93 mv t6,t6 +80000008: 00001117 auipc sp,0x1 +8000000c: 03810113 addi sp,sp,56 # 80001040 +80000010: 000f8183 lb gp,0(t6) # 80001000 +80000014: 001f8203 lb tp,1(t6) +80000018: 002f8283 lb t0,2(t6) +8000001c: 003f8303 lb t1,3(t6) +80000020: 00312023 sw gp,0(sp) +80000024: 00412223 sw tp,4(sp) +80000028: 00512423 sw t0,8(sp) +8000002c: 00612623 sw t1,12(sp) +80000030: 00001c17 auipc s8,0x1 +80000034: fd5c0c13 addi s8,s8,-43 # 80001005 +80000038: 00001297 auipc t0,0x1 +8000003c: 01828293 addi t0,t0,24 # 80001050 +80000040: fffc0c83 lb s9,-1(s8) +80000044: 000c0d03 lb s10,0(s8) +80000048: 001c0d83 lb s11,1(s8) +8000004c: 002c0e03 lb t3,2(s8) +80000050: 0192a023 sw s9,0(t0) +80000054: 01a2a223 sw s10,4(t0) +80000058: 01b2a423 sw s11,8(t0) +8000005c: 01c2a623 sw t3,12(t0) +80000060: 00001397 auipc t2,0x1 +80000064: fa738393 addi t2,t2,-89 # 80001007 +80000068: 00001417 auipc s0,0x1 +8000006c: ff840413 addi s0,s0,-8 # 80001060 +80000070: 00138f03 lb t5,1(t2) +80000074: 00238f83 lb t6,2(t2) +80000078: 00338083 lb ra,3(t2) +8000007c: 00438103 lb sp,4(t2) +80000080: 01e42023 sw t5,0(s0) +80000084: 01f42223 sw t6,4(s0) +80000088: 00142423 sw ra,8(s0) +8000008c: 00242623 sw sp,12(s0) +80000090: 00001517 auipc a0,0x1 +80000094: 77c50513 addi a0,a0,1916 # 8000180c <_end+0x73c> +80000098: 00001597 auipc a1,0x1 +8000009c: fd858593 addi a1,a1,-40 # 80001070 +800000a0: 80050603 lb a2,-2048(a0) +800000a4: 80150683 lb a3,-2047(a0) +800000a8: 80250703 lb a4,-2046(a0) +800000ac: 80350783 lb a5,-2045(a0) +800000b0: 00c5a023 sw a2,0(a1) +800000b4: 00d5a223 sw a3,4(a1) +800000b8: 00e5a423 sw a4,8(a1) +800000bc: 00f5a623 sw a5,12(a1) +800000c0: 00000697 auipc a3,0x0 +800000c4: 75468693 addi a3,a3,1876 # 80000814 +800000c8: 00001717 auipc a4,0x1 +800000cc: fb870713 addi a4,a4,-72 # 80001080 +800000d0: 7fc68783 lb a5,2044(a3) +800000d4: 7fd68803 lb a6,2045(a3) +800000d8: 7fe68883 lb a7,2046(a3) +800000dc: 7ff68903 lb s2,2047(a3) +800000e0: 00f72023 sw a5,0(a4) +800000e4: 01072223 sw a6,4(a4) +800000e8: 01172423 sw a7,8(a4) +800000ec: 01272623 sw s2,12(a4) +800000f0: 00001817 auipc a6,0x1 +800000f4: f2880813 addi a6,a6,-216 # 80001018 +800000f8: 00001897 auipc a7,0x1 +800000fc: f9888893 addi a7,a7,-104 # 80001090 +80000100: ffc80903 lb s2,-4(a6) +80000104: ffd80983 lb s3,-3(a6) +80000108: ffe80a03 lb s4,-2(a6) +8000010c: fff80a83 lb s5,-1(a6) +80000110: 00080b03 lb s6,0(a6) +80000114: 00180b83 lb s7,1(a6) +80000118: 00280c03 lb s8,2(a6) +8000011c: 00380c83 lb s9,3(a6) +80000120: 00480d03 lb s10,4(a6) +80000124: 00580d83 lb s11,5(a6) +80000128: 00680e03 lb t3,6(a6) +8000012c: 00780e83 lb t4,7(a6) +80000130: 0128a023 sw s2,0(a7) +80000134: 0138a223 sw s3,4(a7) +80000138: 0148a423 sw s4,8(a7) +8000013c: 0158a623 sw s5,12(a7) +80000140: 0168a823 sw s6,16(a7) +80000144: 0178aa23 sw s7,20(a7) +80000148: 0188ac23 sw s8,24(a7) +8000014c: 0198ae23 sw s9,28(a7) +80000150: 03a8a023 sw s10,32(a7) +80000154: 03b8a223 sw s11,36(a7) +80000158: 03c8a423 sw t3,40(a7) +8000015c: 03d8a623 sw t4,44(a7) +80000160: 00001a97 auipc s5,0x1 +80000164: ec0a8a93 addi s5,s5,-320 # 80001020 +80000168: 00001b17 auipc s6,0x1 +8000016c: f58b0b13 addi s6,s6,-168 # 800010c0 +80000170: 000a8003 lb zero,0(s5) +80000174: 000b2023 sw zero,0(s6) +80000178: 00001a97 auipc s5,0x1 +8000017c: eaca8a93 addi s5,s5,-340 # 80001024 +80000180: 00001b17 auipc s6,0x1 +80000184: f44b0b13 addi s6,s6,-188 # 800010c4 +80000188: 000aab83 lw s7,0(s5) +8000018c: 000b8c03 lb s8,0(s7) +80000190: 000c0c93 mv s9,s8 +80000194: 019b2023 sw s9,0(s6) +80000198: 00001c97 auipc s9,0x1 +8000019c: e94c8c93 addi s9,s9,-364 # 8000102c +800001a0: 00001d17 auipc s10,0x1 +800001a4: f28d0d13 addi s10,s10,-216 # 800010c8 +800001a8: 000c8c83 lb s9,0(s9) +800001ac: 019d2023 sw s9,0(s10) +800001b0: 00001d97 auipc s11,0x1 +800001b4: e81d8d93 addi s11,s11,-383 # 80001031 +800001b8: 00001e17 auipc t3,0x1 +800001bc: f14e0e13 addi t3,t3,-236 # 800010cc +800001c0: fffd8d83 lb s11,-1(s11) +800001c4: 01be2023 sw s11,0(t3) +800001c8: 00001517 auipc a0,0x1 +800001cc: e7850513 addi a0,a0,-392 # 80001040 +800001d0: 00001597 auipc a1,0x1 +800001d4: f0058593 addi a1,a1,-256 # 800010d0 <_end> +800001d8: f0100637 lui a2,0xf0100 +800001dc: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001e0 : +800001e0: 02b50663 beq a0,a1,8000020c +800001e4: 00c52683 lw a3,12(a0) +800001e8: 00d62023 sw a3,0(a2) +800001ec: 00852683 lw a3,8(a0) +800001f0: 00d62023 sw a3,0(a2) +800001f4: 00452683 lw a3,4(a0) +800001f8: 00d62023 sw a3,0(a2) +800001fc: 00052683 lw a3,0(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 01050513 addi a0,a0,16 +80000208: fd9ff06f j 800001e0 + +8000020c : +8000020c: f0100537 lui a0,0xf0100 +80000210: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +80000214: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: f222 fsw fs0,36(sp) +80001002: 11f1 addi gp,gp,-4 + +80001004 : +80001004: 44f4 lw a3,76(s1) +80001006: 0xf666f333 + +80001008 : +80001008: f666 fsw fs9,44(sp) +8000100a: 55f5 li a1,-3 + +8000100c : +8000100c: 88f8 0x88f8 +8000100e: 0xaaaf777 + +80001010 : +80001010: 0aaa slli s5,s5,0xa +80001012: 9909 andi a0,a0,-30 +80001014: cc0c sw a1,24(s0) +80001016: 0xeee0bbb + +80001018 : +80001018: 0eee slli t4,t4,0x1b +8000101a: dd0d beqz a0,80000f54 +8000101c: 00f0 addi a2,sp,76 +8000101e: 0fff 0xfff + +80001020 : +80001020: 5678 lw a4,108(a2) +80001022: 1234 addi a3,sp,296 + +80001024 : +80001024: 1028 addi a0,sp,40 +80001026: 8000 0x8000 + +80001028 : +80001028: def0 sw a2,124(a3) +8000102a: 9abc 0x9abc + +8000102c : +8000102c: 3210 fld fa2,32(a2) +8000102e: 7654 flw fa3,44(a2) + +80001030 : +80001030: ba98 fsd fa4,48(a3) +80001032: fedc fsw fa5,60(a3) + ... + +80001040 : +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff + +80001070 : +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff + +800010c0 : +800010c0: ffff 0xffff +800010c2: ffff 0xffff + +800010c4 : +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff + +800010cc : +800010cc: ffff 0xffff +800010ce: ffff 0xffff diff --git a/src/test/resources/asm/I-LBU-01.elf.objdump b/src/test/resources/asm/I-LBU-01.elf.objdump new file mode 100644 index 0000000..9419861 --- /dev/null +++ b/src/test/resources/asm/I-LBU-01.elf.objdump @@ -0,0 +1,289 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-LBU-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001f97 auipc t6,0x1 +80000004: 000f8f93 mv t6,t6 +80000008: 00001117 auipc sp,0x1 +8000000c: 03810113 addi sp,sp,56 # 80001040 +80000010: 000fc183 lbu gp,0(t6) # 80001000 +80000014: 001fc203 lbu tp,1(t6) +80000018: 002fc283 lbu t0,2(t6) +8000001c: 003fc303 lbu t1,3(t6) +80000020: 00312023 sw gp,0(sp) +80000024: 00412223 sw tp,4(sp) +80000028: 00512423 sw t0,8(sp) +8000002c: 00612623 sw t1,12(sp) +80000030: 00001c17 auipc s8,0x1 +80000034: fd5c0c13 addi s8,s8,-43 # 80001005 +80000038: 00001297 auipc t0,0x1 +8000003c: 01828293 addi t0,t0,24 # 80001050 +80000040: fffc4c83 lbu s9,-1(s8) +80000044: 000c4d03 lbu s10,0(s8) +80000048: 001c4d83 lbu s11,1(s8) +8000004c: 002c4e03 lbu t3,2(s8) +80000050: 0192a023 sw s9,0(t0) +80000054: 01a2a223 sw s10,4(t0) +80000058: 01b2a423 sw s11,8(t0) +8000005c: 01c2a623 sw t3,12(t0) +80000060: 00001397 auipc t2,0x1 +80000064: fa738393 addi t2,t2,-89 # 80001007 +80000068: 00001417 auipc s0,0x1 +8000006c: ff840413 addi s0,s0,-8 # 80001060 +80000070: 0013cf03 lbu t5,1(t2) +80000074: 0023cf83 lbu t6,2(t2) +80000078: 0033c083 lbu ra,3(t2) +8000007c: 0043c103 lbu sp,4(t2) +80000080: 01e42023 sw t5,0(s0) +80000084: 01f42223 sw t6,4(s0) +80000088: 00142423 sw ra,8(s0) +8000008c: 00242623 sw sp,12(s0) +80000090: 00001517 auipc a0,0x1 +80000094: 77c50513 addi a0,a0,1916 # 8000180c <_end+0x73c> +80000098: 00001597 auipc a1,0x1 +8000009c: fd858593 addi a1,a1,-40 # 80001070 +800000a0: 80054603 lbu a2,-2048(a0) +800000a4: 80154683 lbu a3,-2047(a0) +800000a8: 80254703 lbu a4,-2046(a0) +800000ac: 80354783 lbu a5,-2045(a0) +800000b0: 00c5a023 sw a2,0(a1) +800000b4: 00d5a223 sw a3,4(a1) +800000b8: 00e5a423 sw a4,8(a1) +800000bc: 00f5a623 sw a5,12(a1) +800000c0: 00000697 auipc a3,0x0 +800000c4: 75468693 addi a3,a3,1876 # 80000814 +800000c8: 00001717 auipc a4,0x1 +800000cc: fb870713 addi a4,a4,-72 # 80001080 +800000d0: 7fc6c783 lbu a5,2044(a3) +800000d4: 7fd6c803 lbu a6,2045(a3) +800000d8: 7fe6c883 lbu a7,2046(a3) +800000dc: 7ff6c903 lbu s2,2047(a3) +800000e0: 00f72023 sw a5,0(a4) +800000e4: 01072223 sw a6,4(a4) +800000e8: 01172423 sw a7,8(a4) +800000ec: 01272623 sw s2,12(a4) +800000f0: 00001817 auipc a6,0x1 +800000f4: f2880813 addi a6,a6,-216 # 80001018 +800000f8: 00001897 auipc a7,0x1 +800000fc: f9888893 addi a7,a7,-104 # 80001090 +80000100: ffc84903 lbu s2,-4(a6) +80000104: ffd84983 lbu s3,-3(a6) +80000108: ffe84a03 lbu s4,-2(a6) +8000010c: fff84a83 lbu s5,-1(a6) +80000110: 00084b03 lbu s6,0(a6) +80000114: 00184b83 lbu s7,1(a6) +80000118: 00284c03 lbu s8,2(a6) +8000011c: 00384c83 lbu s9,3(a6) +80000120: 00484d03 lbu s10,4(a6) +80000124: 00584d83 lbu s11,5(a6) +80000128: 00684e03 lbu t3,6(a6) +8000012c: 00784e83 lbu t4,7(a6) +80000130: 0128a023 sw s2,0(a7) +80000134: 0138a223 sw s3,4(a7) +80000138: 0148a423 sw s4,8(a7) +8000013c: 0158a623 sw s5,12(a7) +80000140: 0168a823 sw s6,16(a7) +80000144: 0178aa23 sw s7,20(a7) +80000148: 0188ac23 sw s8,24(a7) +8000014c: 0198ae23 sw s9,28(a7) +80000150: 03a8a023 sw s10,32(a7) +80000154: 03b8a223 sw s11,36(a7) +80000158: 03c8a423 sw t3,40(a7) +8000015c: 03d8a623 sw t4,44(a7) +80000160: 00001a97 auipc s5,0x1 +80000164: ec0a8a93 addi s5,s5,-320 # 80001020 +80000168: 00001b17 auipc s6,0x1 +8000016c: f58b0b13 addi s6,s6,-168 # 800010c0 +80000170: 000ac003 lbu zero,0(s5) +80000174: 000b2023 sw zero,0(s6) +80000178: 00001a97 auipc s5,0x1 +8000017c: eaca8a93 addi s5,s5,-340 # 80001024 +80000180: 00001b17 auipc s6,0x1 +80000184: f44b0b13 addi s6,s6,-188 # 800010c4 +80000188: 000aab83 lw s7,0(s5) +8000018c: 000bcc03 lbu s8,0(s7) +80000190: 000c0c93 mv s9,s8 +80000194: 019b2023 sw s9,0(s6) +80000198: 00001c97 auipc s9,0x1 +8000019c: e94c8c93 addi s9,s9,-364 # 8000102c +800001a0: 00001d17 auipc s10,0x1 +800001a4: f28d0d13 addi s10,s10,-216 # 800010c8 +800001a8: 000ccc83 lbu s9,0(s9) +800001ac: 019d2023 sw s9,0(s10) +800001b0: 00001d97 auipc s11,0x1 +800001b4: e81d8d93 addi s11,s11,-383 # 80001031 +800001b8: 00001e17 auipc t3,0x1 +800001bc: f14e0e13 addi t3,t3,-236 # 800010cc +800001c0: fffdcd83 lbu s11,-1(s11) +800001c4: 01be2023 sw s11,0(t3) +800001c8: 00001517 auipc a0,0x1 +800001cc: e7850513 addi a0,a0,-392 # 80001040 +800001d0: 00001597 auipc a1,0x1 +800001d4: f0058593 addi a1,a1,-256 # 800010d0 <_end> +800001d8: f0100637 lui a2,0xf0100 +800001dc: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001e0 : +800001e0: 02b50663 beq a0,a1,8000020c +800001e4: 00c52683 lw a3,12(a0) +800001e8: 00d62023 sw a3,0(a2) +800001ec: 00852683 lw a3,8(a0) +800001f0: 00d62023 sw a3,0(a2) +800001f4: 00452683 lw a3,4(a0) +800001f8: 00d62023 sw a3,0(a2) +800001fc: 00052683 lw a3,0(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 01050513 addi a0,a0,16 +80000208: fd9ff06f j 800001e0 + +8000020c : +8000020c: f0100537 lui a0,0xf0100 +80000210: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +80000214: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: f222 fsw fs0,36(sp) +80001002: 11f1 addi gp,gp,-4 + +80001004 : +80001004: 44f4 lw a3,76(s1) +80001006: 0xf666f333 + +80001008 : +80001008: f666 fsw fs9,44(sp) +8000100a: 55f5 li a1,-3 + +8000100c : +8000100c: 88f8 0x88f8 +8000100e: 0xaaaf777 + +80001010 : +80001010: 0aaa slli s5,s5,0xa +80001012: 9909 andi a0,a0,-30 +80001014: cc0c sw a1,24(s0) +80001016: 0xeee0bbb + +80001018 : +80001018: 0eee slli t4,t4,0x1b +8000101a: dd0d beqz a0,80000f54 +8000101c: 00f0 addi a2,sp,76 +8000101e: 0fff 0xfff + +80001020 : +80001020: 5678 lw a4,108(a2) +80001022: 1234 addi a3,sp,296 + +80001024 : +80001024: 1028 addi a0,sp,40 +80001026: 8000 0x8000 + +80001028 : +80001028: def0 sw a2,124(a3) +8000102a: 9abc 0x9abc + +8000102c : +8000102c: 3210 fld fa2,32(a2) +8000102e: 7654 flw fa3,44(a2) + +80001030 : +80001030: ba98 fsd fa4,48(a3) +80001032: fedc fsw fa5,60(a3) + ... + +80001040 : +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff + +80001070 : +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff + +800010c0 : +800010c0: ffff 0xffff +800010c2: ffff 0xffff + +800010c4 : +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff + +800010cc : +800010cc: ffff 0xffff +800010ce: ffff 0xffff diff --git a/src/test/resources/asm/I-LH-01.elf.objdump b/src/test/resources/asm/I-LH-01.elf.objdump new file mode 100644 index 0000000..d917bae --- /dev/null +++ b/src/test/resources/asm/I-LH-01.elf.objdump @@ -0,0 +1,225 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-LH-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001f97 auipc t6,0x1 +80000004: 000f8f93 mv t6,t6 +80000008: 00001117 auipc sp,0x1 +8000000c: 03810113 addi sp,sp,56 # 80001040 +80000010: 000f9183 lh gp,0(t6) # 80001000 +80000014: 002f9203 lh tp,2(t6) +80000018: 00312023 sw gp,0(sp) +8000001c: 00412223 sw tp,4(sp) +80000020: 00001c17 auipc s8,0x1 +80000024: fe5c0c13 addi s8,s8,-27 # 80001005 +80000028: 00001297 auipc t0,0x1 +8000002c: 02028293 addi t0,t0,32 # 80001048 +80000030: fffc1c83 lh s9,-1(s8) +80000034: 001c1d03 lh s10,1(s8) +80000038: 0192a023 sw s9,0(t0) +8000003c: 01a2a223 sw s10,4(t0) +80000040: 00001397 auipc t2,0x1 +80000044: fc738393 addi t2,t2,-57 # 80001007 +80000048: 00001417 auipc s0,0x1 +8000004c: 00840413 addi s0,s0,8 # 80001050 +80000050: 00139f03 lh t5,1(t2) +80000054: 00339f83 lh t6,3(t2) +80000058: 01e42023 sw t5,0(s0) +8000005c: 01f42223 sw t6,4(s0) +80000060: 00001517 auipc a0,0x1 +80000064: 7ac50513 addi a0,a0,1964 # 8000180c <_end+0x77c> +80000068: 00001597 auipc a1,0x1 +8000006c: ff058593 addi a1,a1,-16 # 80001058 +80000070: 80051603 lh a2,-2048(a0) +80000074: 80251683 lh a3,-2046(a0) +80000078: 00c5a023 sw a2,0(a1) +8000007c: 00d5a223 sw a3,4(a1) +80000080: 00000697 auipc a3,0x0 +80000084: 79368693 addi a3,a3,1939 # 80000813 +80000088: 00001717 auipc a4,0x1 +8000008c: fd870713 addi a4,a4,-40 # 80001060 +80000090: 7fd69783 lh a5,2045(a3) +80000094: 7ff69803 lh a6,2047(a3) +80000098: 00f72023 sw a5,0(a4) +8000009c: 01072223 sw a6,4(a4) +800000a0: 00001817 auipc a6,0x1 +800000a4: f7880813 addi a6,a6,-136 # 80001018 +800000a8: 00001897 auipc a7,0x1 +800000ac: fc088893 addi a7,a7,-64 # 80001068 +800000b0: ffc81903 lh s2,-4(a6) +800000b4: ffe81983 lh s3,-2(a6) +800000b8: 00081a03 lh s4,0(a6) +800000bc: 00281a83 lh s5,2(a6) +800000c0: 00481b03 lh s6,4(a6) +800000c4: 00681b83 lh s7,6(a6) +800000c8: 0128a023 sw s2,0(a7) +800000cc: 0138a223 sw s3,4(a7) +800000d0: 0148a423 sw s4,8(a7) +800000d4: 0158a623 sw s5,12(a7) +800000d8: 0168a823 sw s6,16(a7) +800000dc: 0178aa23 sw s7,20(a7) +800000e0: 00001a97 auipc s5,0x1 +800000e4: f40a8a93 addi s5,s5,-192 # 80001020 +800000e8: 00001b17 auipc s6,0x1 +800000ec: f98b0b13 addi s6,s6,-104 # 80001080 +800000f0: 000a9003 lh zero,0(s5) +800000f4: 000b2023 sw zero,0(s6) +800000f8: 00001a97 auipc s5,0x1 +800000fc: f2ca8a93 addi s5,s5,-212 # 80001024 +80000100: 00001b17 auipc s6,0x1 +80000104: f84b0b13 addi s6,s6,-124 # 80001084 +80000108: 000aab83 lw s7,0(s5) +8000010c: 000b9c03 lh s8,0(s7) +80000110: 000c0c93 mv s9,s8 +80000114: 019b2023 sw s9,0(s6) +80000118: 00001c97 auipc s9,0x1 +8000011c: f14c8c93 addi s9,s9,-236 # 8000102c +80000120: 00001d17 auipc s10,0x1 +80000124: f68d0d13 addi s10,s10,-152 # 80001088 +80000128: 000c9c83 lh s9,0(s9) +8000012c: 019d2023 sw s9,0(s10) +80000130: 00001d97 auipc s11,0x1 +80000134: f01d8d93 addi s11,s11,-255 # 80001031 +80000138: 00001e17 auipc t3,0x1 +8000013c: f54e0e13 addi t3,t3,-172 # 8000108c +80000140: fffd9d83 lh s11,-1(s11) +80000144: 01be2023 sw s11,0(t3) +80000148: 00001517 auipc a0,0x1 +8000014c: ef850513 addi a0,a0,-264 # 80001040 +80000150: 00001597 auipc a1,0x1 +80000154: f4058593 addi a1,a1,-192 # 80001090 <_end> +80000158: f0100637 lui a2,0xf0100 +8000015c: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee9c> + +80000160 : +80000160: 02b50663 beq a0,a1,8000018c +80000164: 00c52683 lw a3,12(a0) +80000168: 00d62023 sw a3,0(a2) +8000016c: 00852683 lw a3,8(a0) +80000170: 00d62023 sw a3,0(a2) +80000174: 00452683 lw a3,4(a0) +80000178: 00d62023 sw a3,0(a2) +8000017c: 00052683 lw a3,0(a0) +80000180: 00d62023 sw a3,0(a2) +80000184: 01050513 addi a0,a0,16 +80000188: fd9ff06f j 80000160 + +8000018c : +8000018c: f0100537 lui a0,0xf0100 +80000190: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee90> +80000194: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: f222 fsw fs0,36(sp) +80001002: 11f1 addi gp,gp,-4 + +80001004 : +80001004: 44f4 lw a3,76(s1) +80001006: 0xf666f333 + +80001008 : +80001008: f666 fsw fs9,44(sp) +8000100a: 55f5 li a1,-3 + +8000100c : +8000100c: 88f8 0x88f8 +8000100e: 0xaaaf777 + +80001010 : +80001010: 0aaa slli s5,s5,0xa +80001012: 9909 andi a0,a0,-30 +80001014: cc0c sw a1,24(s0) +80001016: 0xeee0bbb + +80001018 : +80001018: 0eee slli t4,t4,0x1b +8000101a: dd0d beqz a0,80000f54 +8000101c: 00f0 addi a2,sp,76 +8000101e: 0fff 0xfff + +80001020 : +80001020: 5678 lw a4,108(a2) +80001022: 1234 addi a3,sp,296 + +80001024 : +80001024: 1028 addi a0,sp,40 +80001026: 8000 0x8000 + +80001028 : +80001028: def0 sw a2,124(a3) +8000102a: 9abc 0x9abc + +8000102c : +8000102c: 3210 fld fa2,32(a2) +8000102e: 7654 flw fa3,44(a2) + +80001030 : +80001030: ba98 fsd fa4,48(a3) +80001032: fedc fsw fa5,60(a3) + ... + +80001040 : +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff + +80001058 : +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff + +80001068 : +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff + +80001084 : +80001084: ffff 0xffff +80001086: ffff 0xffff + +80001088 : +80001088: ffff 0xffff +8000108a: ffff 0xffff + +8000108c : +8000108c: ffff 0xffff +8000108e: ffff 0xffff diff --git a/src/test/resources/asm/I-LHU-01.elf.objdump b/src/test/resources/asm/I-LHU-01.elf.objdump new file mode 100644 index 0000000..e5d2430 --- /dev/null +++ b/src/test/resources/asm/I-LHU-01.elf.objdump @@ -0,0 +1,225 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-LHU-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001f97 auipc t6,0x1 +80000004: 000f8f93 mv t6,t6 +80000008: 00001117 auipc sp,0x1 +8000000c: 03810113 addi sp,sp,56 # 80001040 +80000010: 000fd183 lhu gp,0(t6) # 80001000 +80000014: 002fd203 lhu tp,2(t6) +80000018: 00312023 sw gp,0(sp) +8000001c: 00412223 sw tp,4(sp) +80000020: 00001c17 auipc s8,0x1 +80000024: fe5c0c13 addi s8,s8,-27 # 80001005 +80000028: 00001297 auipc t0,0x1 +8000002c: 02028293 addi t0,t0,32 # 80001048 +80000030: fffc5c83 lhu s9,-1(s8) +80000034: 001c5d03 lhu s10,1(s8) +80000038: 0192a023 sw s9,0(t0) +8000003c: 01a2a223 sw s10,4(t0) +80000040: 00001397 auipc t2,0x1 +80000044: fc738393 addi t2,t2,-57 # 80001007 +80000048: 00001417 auipc s0,0x1 +8000004c: 00840413 addi s0,s0,8 # 80001050 +80000050: 0013df03 lhu t5,1(t2) +80000054: 0033df83 lhu t6,3(t2) +80000058: 01e42023 sw t5,0(s0) +8000005c: 01f42223 sw t6,4(s0) +80000060: 00001517 auipc a0,0x1 +80000064: 7ac50513 addi a0,a0,1964 # 8000180c <_end+0x77c> +80000068: 00001597 auipc a1,0x1 +8000006c: ff058593 addi a1,a1,-16 # 80001058 +80000070: 80055603 lhu a2,-2048(a0) +80000074: 80255683 lhu a3,-2046(a0) +80000078: 00c5a023 sw a2,0(a1) +8000007c: 00d5a223 sw a3,4(a1) +80000080: 00000697 auipc a3,0x0 +80000084: 79368693 addi a3,a3,1939 # 80000813 +80000088: 00001717 auipc a4,0x1 +8000008c: fd870713 addi a4,a4,-40 # 80001060 +80000090: 7fd6d783 lhu a5,2045(a3) +80000094: 7ff6d803 lhu a6,2047(a3) +80000098: 00f72023 sw a5,0(a4) +8000009c: 01072223 sw a6,4(a4) +800000a0: 00001817 auipc a6,0x1 +800000a4: f7880813 addi a6,a6,-136 # 80001018 +800000a8: 00001897 auipc a7,0x1 +800000ac: fc088893 addi a7,a7,-64 # 80001068 +800000b0: ffc85903 lhu s2,-4(a6) +800000b4: ffe85983 lhu s3,-2(a6) +800000b8: 00085a03 lhu s4,0(a6) +800000bc: 00285a83 lhu s5,2(a6) +800000c0: 00485b03 lhu s6,4(a6) +800000c4: 00685b83 lhu s7,6(a6) +800000c8: 0128a023 sw s2,0(a7) +800000cc: 0138a223 sw s3,4(a7) +800000d0: 0148a423 sw s4,8(a7) +800000d4: 0158a623 sw s5,12(a7) +800000d8: 0168a823 sw s6,16(a7) +800000dc: 0178aa23 sw s7,20(a7) +800000e0: 00001a97 auipc s5,0x1 +800000e4: f40a8a93 addi s5,s5,-192 # 80001020 +800000e8: 00001b17 auipc s6,0x1 +800000ec: f98b0b13 addi s6,s6,-104 # 80001080 +800000f0: 000ad003 lhu zero,0(s5) +800000f4: 000b2023 sw zero,0(s6) +800000f8: 00001a97 auipc s5,0x1 +800000fc: f2ca8a93 addi s5,s5,-212 # 80001024 +80000100: 00001b17 auipc s6,0x1 +80000104: f84b0b13 addi s6,s6,-124 # 80001084 +80000108: 000aab83 lw s7,0(s5) +8000010c: 000bdc03 lhu s8,0(s7) +80000110: 000c0c93 mv s9,s8 +80000114: 019b2023 sw s9,0(s6) +80000118: 00001c97 auipc s9,0x1 +8000011c: f14c8c93 addi s9,s9,-236 # 8000102c +80000120: 00001d17 auipc s10,0x1 +80000124: f68d0d13 addi s10,s10,-152 # 80001088 +80000128: 000cdc83 lhu s9,0(s9) +8000012c: 019d2023 sw s9,0(s10) +80000130: 00001d97 auipc s11,0x1 +80000134: f01d8d93 addi s11,s11,-255 # 80001031 +80000138: 00001e17 auipc t3,0x1 +8000013c: f54e0e13 addi t3,t3,-172 # 8000108c +80000140: fffddd83 lhu s11,-1(s11) +80000144: 01be2023 sw s11,0(t3) +80000148: 00001517 auipc a0,0x1 +8000014c: ef850513 addi a0,a0,-264 # 80001040 +80000150: 00001597 auipc a1,0x1 +80000154: f4058593 addi a1,a1,-192 # 80001090 <_end> +80000158: f0100637 lui a2,0xf0100 +8000015c: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee9c> + +80000160 : +80000160: 02b50663 beq a0,a1,8000018c +80000164: 00c52683 lw a3,12(a0) +80000168: 00d62023 sw a3,0(a2) +8000016c: 00852683 lw a3,8(a0) +80000170: 00d62023 sw a3,0(a2) +80000174: 00452683 lw a3,4(a0) +80000178: 00d62023 sw a3,0(a2) +8000017c: 00052683 lw a3,0(a0) +80000180: 00d62023 sw a3,0(a2) +80000184: 01050513 addi a0,a0,16 +80000188: fd9ff06f j 80000160 + +8000018c : +8000018c: f0100537 lui a0,0xf0100 +80000190: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee90> +80000194: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: f222 fsw fs0,36(sp) +80001002: 11f1 addi gp,gp,-4 + +80001004 : +80001004: 44f4 lw a3,76(s1) +80001006: 0xf666f333 + +80001008 : +80001008: f666 fsw fs9,44(sp) +8000100a: 55f5 li a1,-3 + +8000100c : +8000100c: 88f8 0x88f8 +8000100e: 0xaaaf777 + +80001010 : +80001010: 0aaa slli s5,s5,0xa +80001012: 9909 andi a0,a0,-30 +80001014: cc0c sw a1,24(s0) +80001016: 0xeee0bbb + +80001018 : +80001018: 0eee slli t4,t4,0x1b +8000101a: dd0d beqz a0,80000f54 +8000101c: 00f0 addi a2,sp,76 +8000101e: 0fff 0xfff + +80001020 : +80001020: 5678 lw a4,108(a2) +80001022: 1234 addi a3,sp,296 + +80001024 : +80001024: 1028 addi a0,sp,40 +80001026: 8000 0x8000 + +80001028 : +80001028: def0 sw a2,124(a3) +8000102a: 9abc 0x9abc + +8000102c : +8000102c: 3210 fld fa2,32(a2) +8000102e: 7654 flw fa3,44(a2) + +80001030 : +80001030: ba98 fsd fa4,48(a3) +80001032: fedc fsw fa5,60(a3) + ... + +80001040 : +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff + +80001058 : +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff + +80001068 : +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff + +80001084 : +80001084: ffff 0xffff +80001086: ffff 0xffff + +80001088 : +80001088: ffff 0xffff +8000108a: ffff 0xffff + +8000108c : +8000108c: ffff 0xffff +8000108e: ffff 0xffff diff --git a/src/test/resources/asm/I-LUI-01.elf.objdump b/src/test/resources/asm/I-LUI-01.elf.objdump new file mode 100644 index 0000000..0d35aba --- /dev/null +++ b/src/test/resources/asm/I-LUI-01.elf.objdump @@ -0,0 +1,128 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-LUI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001797 auipc a5,0x1 +80000004: 01078793 addi a5,a5,16 # 80001010 +80000008: 000000b7 lui ra,0x0 +8000000c: 000011b7 lui gp,0x1 +80000010: fffff2b7 lui t0,0xfffff +80000014: 7ffffeb7 lui t4,0x7ffff +80000018: 80000fb7 lui t6,0x80000 +8000001c: 0017a023 sw ra,0(a5) +80000020: 0037a223 sw gp,4(a5) +80000024: 0057a423 sw t0,8(a5) +80000028: 01d7a623 sw t4,12(a5) +8000002c: 01f7a823 sw t6,16(a5) +80000030: 00001797 auipc a5,0x1 +80000034: fd078793 addi a5,a5,-48 # 80001000 +80000038: 00001817 auipc a6,0x1 +8000003c: fec80813 addi a6,a6,-20 # 80001024 +80000040: 0007a103 lw sp,0(a5) +80000044: 0007a203 lw tp,0(a5) +80000048: 0007a303 lw t1,0(a5) +8000004c: 0007ae03 lw t3,0(a5) +80000050: 0007af03 lw t5,0(a5) +80000054: 80000137 lui sp,0x80000 +80000058: 7ffff237 lui tp,0x7ffff +8000005c: 00000337 lui t1,0x0 +80000060: 00001e37 lui t3,0x1 +80000064: ffffff37 lui t5,0xfffff +80000068: 00282023 sw sp,0(a6) +8000006c: 00482223 sw tp,4(a6) +80000070: 00682423 sw t1,8(a6) +80000074: 01c82623 sw t3,12(a6) +80000078: 01e82823 sw t5,16(a6) +8000007c: 00001897 auipc a7,0x1 +80000080: fbc88893 addi a7,a7,-68 # 80001038 +80000084: 427270b7 lui ra,0x42727 +80000088: e6f08093 addi ra,ra,-401 # 42726e6f <_start-0x3d8d9191> +8000008c: 123457b7 lui a5,0x12345 +80000090: 67878793 addi a5,a5,1656 # 12345678 <_start-0x6dcba988> +80000094: 9abcef37 lui t5,0x9abce +80000098: ef0f0f13 addi t5,t5,-272 # 9abcdef0 <_end+0x1abccea0> +8000009c: 42727137 lui sp,0x42727 +800000a0: e6f10113 addi sp,sp,-401 # 42726e6f <_start-0x3d8d9191> +800000a4: 12345837 lui a6,0x12345 +800000a8: 67880813 addi a6,a6,1656 # 12345678 <_start-0x6dcba988> +800000ac: 9abcefb7 lui t6,0x9abce +800000b0: ef0f8f93 addi t6,t6,-272 # 9abcdef0 <_end+0x1abccea0> +800000b4: 0018a023 sw ra,0(a7) +800000b8: 00f8a223 sw a5,4(a7) +800000bc: 01e8a423 sw t5,8(a7) +800000c0: 0028a623 sw sp,12(a7) +800000c4: 0108a823 sw a6,16(a7) +800000c8: 01f8aa23 sw t6,20(a7) +800000cc: 00001517 auipc a0,0x1 +800000d0: f4450513 addi a0,a0,-188 # 80001010 +800000d4: 00001597 auipc a1,0x1 +800000d8: f7c58593 addi a1,a1,-132 # 80001050 <_end> +800000dc: f0100637 lui a2,0xf0100 +800000e0: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feedc> + +800000e4 : +800000e4: 02b50663 beq a0,a1,80000110 +800000e8: 00c52683 lw a3,12(a0) +800000ec: 00d62023 sw a3,0(a2) +800000f0: 00852683 lw a3,8(a0) +800000f4: 00d62023 sw a3,0(a2) +800000f8: 00452683 lw a3,4(a0) +800000fc: 00d62023 sw a3,0(a2) +80000100: 00052683 lw a3,0(a0) +80000104: 00d62023 sw a3,0(a2) +80000108: 01050513 addi a0,a0,16 +8000010c: fd9ff06f j 800000e4 + +80000110 : +80000110: f0100537 lui a0,0xf0100 +80000114: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feed0> +80000118: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 1111 addi sp,sp,-28 +80001002: 1111 addi sp,sp,-28 + ... + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff + +80001024 : +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff diff --git a/src/test/resources/asm/I-LW-01.elf.objdump b/src/test/resources/asm/I-LW-01.elf.objdump new file mode 100644 index 0000000..8d033c8 --- /dev/null +++ b/src/test/resources/asm/I-LW-01.elf.objdump @@ -0,0 +1,193 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-LW-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001f97 auipc t6,0x1 +80000004: 000f8f93 mv t6,t6 +80000008: 00001117 auipc sp,0x1 +8000000c: 03810113 addi sp,sp,56 # 80001040 +80000010: 000fa183 lw gp,0(t6) # 80001000 +80000014: 00312023 sw gp,0(sp) +80000018: 00001c17 auipc s8,0x1 +8000001c: fedc0c13 addi s8,s8,-19 # 80001005 +80000020: 00001297 auipc t0,0x1 +80000024: 02428293 addi t0,t0,36 # 80001044 +80000028: fffc2c83 lw s9,-1(s8) +8000002c: 0192a023 sw s9,0(t0) +80000030: 00001397 auipc t2,0x1 +80000034: fd738393 addi t2,t2,-41 # 80001007 +80000038: 00001417 auipc s0,0x1 +8000003c: 01040413 addi s0,s0,16 # 80001048 +80000040: 0013af83 lw t6,1(t2) +80000044: 01f42023 sw t6,0(s0) +80000048: 00001517 auipc a0,0x1 +8000004c: 7c450513 addi a0,a0,1988 # 8000180c <_end+0x79c> +80000050: 00001597 auipc a1,0x1 +80000054: ffc58593 addi a1,a1,-4 # 8000104c +80000058: 80052603 lw a2,-2048(a0) +8000005c: 00c5a023 sw a2,0(a1) +80000060: 00000697 auipc a3,0x0 +80000064: 7b168693 addi a3,a3,1969 # 80000811 +80000068: 00001717 auipc a4,0x1 +8000006c: fe870713 addi a4,a4,-24 # 80001050 +80000070: 7ff6a783 lw a5,2047(a3) +80000074: 00f72023 sw a5,0(a4) +80000078: 00001817 auipc a6,0x1 +8000007c: fa080813 addi a6,a6,-96 # 80001018 +80000080: 00001897 auipc a7,0x1 +80000084: fd488893 addi a7,a7,-44 # 80001054 +80000088: ffc82903 lw s2,-4(a6) +8000008c: 00082983 lw s3,0(a6) +80000090: 00482a03 lw s4,4(a6) +80000094: 0128a023 sw s2,0(a7) +80000098: 0138a223 sw s3,4(a7) +8000009c: 0148a423 sw s4,8(a7) +800000a0: 00001a97 auipc s5,0x1 +800000a4: f80a8a93 addi s5,s5,-128 # 80001020 +800000a8: 00001b17 auipc s6,0x1 +800000ac: fb8b0b13 addi s6,s6,-72 # 80001060 +800000b0: 000aa003 lw zero,0(s5) +800000b4: 000b2023 sw zero,0(s6) +800000b8: 00001a97 auipc s5,0x1 +800000bc: f6ca8a93 addi s5,s5,-148 # 80001024 +800000c0: 00001b17 auipc s6,0x1 +800000c4: fa4b0b13 addi s6,s6,-92 # 80001064 +800000c8: 000aab83 lw s7,0(s5) +800000cc: 000bac03 lw s8,0(s7) +800000d0: 000c0c93 mv s9,s8 +800000d4: 019b2023 sw s9,0(s6) +800000d8: 00001c97 auipc s9,0x1 +800000dc: f54c8c93 addi s9,s9,-172 # 8000102c +800000e0: 00001d17 auipc s10,0x1 +800000e4: f88d0d13 addi s10,s10,-120 # 80001068 +800000e8: 000cac83 lw s9,0(s9) +800000ec: 019d2023 sw s9,0(s10) +800000f0: 00001d97 auipc s11,0x1 +800000f4: f41d8d93 addi s11,s11,-191 # 80001031 +800000f8: 00001e17 auipc t3,0x1 +800000fc: f74e0e13 addi t3,t3,-140 # 8000106c +80000100: fffdad83 lw s11,-1(s11) +80000104: 01be2023 sw s11,0(t3) +80000108: 00001517 auipc a0,0x1 +8000010c: f3850513 addi a0,a0,-200 # 80001040 +80000110: 00001597 auipc a1,0x1 +80000114: f6058593 addi a1,a1,-160 # 80001070 <_end> +80000118: f0100637 lui a2,0xf0100 +8000011c: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +80000120 : +80000120: 02b50663 beq a0,a1,8000014c +80000124: 00c52683 lw a3,12(a0) +80000128: 00d62023 sw a3,0(a2) +8000012c: 00852683 lw a3,8(a0) +80000130: 00d62023 sw a3,0(a2) +80000134: 00452683 lw a3,4(a0) +80000138: 00d62023 sw a3,0(a2) +8000013c: 00052683 lw a3,0(a0) +80000140: 00d62023 sw a3,0(a2) +80000144: 01050513 addi a0,a0,16 +80000148: fd9ff06f j 80000120 + +8000014c : +8000014c: f0100537 lui a0,0xf0100 +80000150: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000154: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: f222 fsw fs0,36(sp) +80001002: 11f1 addi gp,gp,-4 + +80001004 : +80001004: 44f4 lw a3,76(s1) +80001006: 0xf666f333 + +80001008 : +80001008: f666 fsw fs9,44(sp) +8000100a: 55f5 li a1,-3 + +8000100c : +8000100c: 88f8 0x88f8 +8000100e: 0xaaaf777 + +80001010 : +80001010: 0aaa slli s5,s5,0xa +80001012: 9909 andi a0,a0,-30 +80001014: cc0c sw a1,24(s0) +80001016: 0xeee0bbb + +80001018 : +80001018: 0eee slli t4,t4,0x1b +8000101a: dd0d beqz a0,80000f54 +8000101c: 00f0 addi a2,sp,76 +8000101e: 0fff 0xfff + +80001020 : +80001020: 5678 lw a4,108(a2) +80001022: 1234 addi a3,sp,296 + +80001024 : +80001024: 1028 addi a0,sp,40 +80001026: 8000 0x8000 + +80001028 : +80001028: def0 sw a2,124(a3) +8000102a: 9abc 0x9abc + +8000102c : +8000102c: 3210 fld fa2,32(a2) +8000102e: 7654 flw fa3,44(a2) + +80001030 : +80001030: ba98 fsd fa4,48(a3) +80001032: fedc fsw fa5,60(a3) + ... + +80001040 : +80001040: ffff 0xffff +80001042: ffff 0xffff + +80001044 : +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff + +8000104c : +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff + +80001054 : +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff + +80001064 : +80001064: ffff 0xffff +80001066: ffff 0xffff + +80001068 : +80001068: ffff 0xffff +8000106a: ffff 0xffff + +8000106c : +8000106c: ffff 0xffff +8000106e: ffff 0xffff diff --git a/src/test/resources/asm/I-MISALIGN_JMP-01.elf.objdump b/src/test/resources/asm/I-MISALIGN_JMP-01.elf.objdump new file mode 100644 index 0000000..f08f7b4 --- /dev/null +++ b/src/test/resources/asm/I-MISALIGN_JMP-01.elf.objdump @@ -0,0 +1,268 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-MISALIGN_JMP-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00000097 auipc ra,0x0 +80000004: 20808093 addi ra,ra,520 # 80000208 <_trap_handler> +80000008: 30509ff3 csrrw t6,mtvec,ra +8000000c: 30127073 csrci misa,4 +80000010: 00001097 auipc ra,0x1 +80000014: ff008093 addi ra,ra,-16 # 80001000 +80000018: 11111137 lui sp,0x11111 +8000001c: 11110113 addi sp,sp,273 # 11111111 <_start-0x6eeeeeef> +80000020: 00a0006f j 8000002a <_start+0x2a> +80000024: 00000113 li sp,0 +80000028: 00001097 auipc ra,0x1 +8000002c: fe408093 addi ra,ra,-28 # 8000100c +80000030: 22222137 lui sp,0x22222 +80000034: 22210113 addi sp,sp,546 # 22222222 <_start-0x5dddddde> +80000038: 00000217 auipc tp,0x0 +8000003c: 01120213 addi tp,tp,17 # 80000049 <_start+0x49> +80000040: 00020067 jr tp +80000044: 00000113 li sp,0 +80000048: 0020a023 sw sp,0(ra) +8000004c: 00408093 addi ra,ra,4 +80000050: 33333137 lui sp,0x33333 +80000054: 33310113 addi sp,sp,819 # 33333333 <_start-0x4ccccccd> +80000058: 00000217 auipc tp,0x0 +8000005c: 01020213 addi tp,tp,16 # 80000068 <_start+0x68> +80000060: 00120067 jr 1(tp) # 1 <_start-0x7fffffff> +80000064: 00000113 li sp,0 +80000068: 0020a023 sw sp,0(ra) +8000006c: 00408093 addi ra,ra,4 +80000070: 44444137 lui sp,0x44444 +80000074: 44410113 addi sp,sp,1092 # 44444444 <_start-0x3bbbbbbc> +80000078: 00000217 auipc tp,0x0 +8000007c: 01420213 addi tp,tp,20 # 8000008c <_start+0x8c> +80000080: ffd20067 jr -3(tp) # fffffffd <_end+0x7fffef6d> +80000084: 00000113 li sp,0 +80000088: 0020a023 sw sp,0(ra) +8000008c: 00408093 addi ra,ra,4 +80000090: 00001097 auipc ra,0x1 +80000094: f8808093 addi ra,ra,-120 # 80001018 +80000098: 55555137 lui sp,0x55555 +8000009c: 55510113 addi sp,sp,1365 # 55555555 <_start-0x2aaaaaab> +800000a0: 00000217 auipc tp,0x0 +800000a4: 01220213 addi tp,tp,18 # 800000b2 <_start+0xb2> +800000a8: 00020067 jr tp +800000ac: 00000113 li sp,0 +800000b0: 66666137 lui sp,0x66666 +800000b4: 66610113 addi sp,sp,1638 # 66666666 <_start-0x1999999a> +800000b8: 00000217 auipc tp,0x0 +800000bc: 01320213 addi tp,tp,19 # 800000cb <_start+0xcb> +800000c0: 00020067 jr tp +800000c4: 00000113 li sp,0 +800000c8: 77777137 lui sp,0x77777 +800000cc: 77710113 addi sp,sp,1911 # 77777777 <_start-0x8888889> +800000d0: 00000217 auipc tp,0x0 +800000d4: 01020213 addi tp,tp,16 # 800000e0 <_start+0xe0> +800000d8: 00220067 jr 2(tp) # 2 <_start-0x7ffffffe> +800000dc: 00000113 li sp,0 +800000e0: 88889137 lui sp,0x88889 +800000e4: 88810113 addi sp,sp,-1912 # 88888888 <_end+0x88877f8> +800000e8: 00000217 auipc tp,0x0 +800000ec: 01020213 addi tp,tp,16 # 800000f8 <_start+0xf8> +800000f0: 00320067 jr 3(tp) # 3 <_start-0x7ffffffd> +800000f4: 00000113 li sp,0 +800000f8: 00001097 auipc ra,0x1 +800000fc: f5008093 addi ra,ra,-176 # 80001048 +80000100: 00500293 li t0,5 +80000104: 00600313 li t1,6 +80000108: 00628763 beq t0,t1,80000116 <_start+0x116> +8000010c: 9999a137 lui sp,0x9999a +80000110: 99910113 addi sp,sp,-1639 # 99999999 <_end+0x19998909> +80000114: 00000013 nop +80000118: 00000013 nop +8000011c: 00528563 beq t0,t0,80000126 <_start+0x126> +80000120: 00000113 li sp,0 +80000124: 00001097 auipc ra,0x1 +80000128: f3008093 addi ra,ra,-208 # 80001054 +8000012c: 00500293 li t0,5 +80000130: 00600313 li t1,6 +80000134: 00529763 bne t0,t0,80000142 <_start+0x142> +80000138: aaaab137 lui sp,0xaaaab +8000013c: aaa10113 addi sp,sp,-1366 # aaaaaaaa <_end+0x2aaa9a1a> +80000140: 00000013 nop +80000144: 00000013 nop +80000148: 00629563 bne t0,t1,80000152 <_start+0x152> +8000014c: 00000113 li sp,0 +80000150: 00001097 auipc ra,0x1 +80000154: f1008093 addi ra,ra,-240 # 80001060 +80000158: 00500293 li t0,5 +8000015c: 00600313 li t1,6 +80000160: 00534763 blt t1,t0,8000016e <_start+0x16e> +80000164: bbbbc137 lui sp,0xbbbbc +80000168: bbb10113 addi sp,sp,-1093 # bbbbbbbb <_end+0x3bbbab2b> +8000016c: 00000013 nop +80000170: 00000013 nop +80000174: 0062c563 blt t0,t1,8000017e <_start+0x17e> +80000178: 00000113 li sp,0 +8000017c: 00001097 auipc ra,0x1 +80000180: ef008093 addi ra,ra,-272 # 8000106c +80000184: 00500293 li t0,5 +80000188: 00600313 li t1,6 +8000018c: 00536763 bltu t1,t0,8000019a <_start+0x19a> +80000190: ccccd137 lui sp,0xccccd +80000194: ccc10113 addi sp,sp,-820 # cccccccc <_end+0x4cccbc3c> +80000198: 00000013 nop +8000019c: 00000013 nop +800001a0: 0062e563 bltu t0,t1,800001aa <_start+0x1aa> +800001a4: 00000113 li sp,0 +800001a8: 00001097 auipc ra,0x1 +800001ac: ed008093 addi ra,ra,-304 # 80001078 +800001b0: 00500293 li t0,5 +800001b4: 00600313 li t1,6 +800001b8: 0062d763 ble t1,t0,800001c6 <_start+0x1c6> +800001bc: dddde137 lui sp,0xdddde +800001c0: ddd10113 addi sp,sp,-547 # dddddddd <_end+0x5dddcd4d> +800001c4: 00000013 nop +800001c8: 00000013 nop +800001cc: 00535563 ble t0,t1,800001d6 <_start+0x1d6> +800001d0: 00000113 li sp,0 +800001d4: 00001097 auipc ra,0x1 +800001d8: eb008093 addi ra,ra,-336 # 80001084 +800001dc: 00500293 li t0,5 +800001e0: 00600313 li t1,6 +800001e4: 0062f763 bleu t1,t0,800001f2 <_start+0x1f2> +800001e8: eeeef137 lui sp,0xeeeef +800001ec: eee10113 addi sp,sp,-274 # eeeeeeee <_end+0x6eeede5e> +800001f0: 00000013 nop +800001f4: 00000013 nop +800001f8: 00537563 bleu t0,t1,80000202 <_start+0x202> +800001fc: 00000113 li sp,0 +80000200: 305f9073 csrw mtvec,t6 +80000204: 0300006f j 80000234 + +80000208 <_trap_handler>: +80000208: 34302f73 csrr t5,mbadaddr +8000020c: ffef0f13 addi t5,t5,-2 +80000210: 341f1073 csrw mepc,t5 +80000214: 34302f73 csrr t5,mbadaddr +80000218: 003f7f13 andi t5,t5,3 +8000021c: 01e0a023 sw t5,0(ra) +80000220: 34202f73 csrr t5,mcause +80000224: 01e0a223 sw t5,4(ra) +80000228: 0020a423 sw sp,8(ra) +8000022c: 00c08093 addi ra,ra,12 +80000230: 30200073 mret + +80000234 : +80000234: 00001517 auipc a0,0x1 +80000238: dcc50513 addi a0,a0,-564 # 80001000 +8000023c: 00001597 auipc a1,0x1 +80000240: e5458593 addi a1,a1,-428 # 80001090 <_end> +80000244: f0100637 lui a2,0xf0100 +80000248: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee9c> + +8000024c : +8000024c: 02b50663 beq a0,a1,80000278 +80000250: 00c52683 lw a3,12(a0) +80000254: 00d62023 sw a3,0(a2) +80000258: 00852683 lw a3,8(a0) +8000025c: 00d62023 sw a3,0(a2) +80000260: 00452683 lw a3,4(a0) +80000264: 00d62023 sw a3,0(a2) +80000268: 00052683 lw a3,0(a0) +8000026c: 00d62023 sw a3,0(a2) +80000270: 01050513 addi a0,a0,16 +80000274: fd9ff06f j 8000024c + +80000278 : +80000278: f0100537 lui a0,0xf0100 +8000027c: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee90> +80000280: 00052023 sw zero,0(a0) + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff + +80001054 : +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff + +8000106c : +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff + +80001084 : +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff diff --git a/src/test/resources/asm/I-MISALIGN_LDST-01.elf.objdump b/src/test/resources/asm/I-MISALIGN_LDST-01.elf.objdump new file mode 100644 index 0000000..cfb5c06 --- /dev/null +++ b/src/test/resources/asm/I-MISALIGN_LDST-01.elf.objdump @@ -0,0 +1,242 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-MISALIGN_LDST-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00000097 auipc ra,0x0 +80000004: 14408093 addi ra,ra,324 # 80000144 <_trap_handler> +80000008: 30509ff3 csrrw t6,mtvec,ra +8000000c: 00001197 auipc gp,0x1 +80000010: ff418193 addi gp,gp,-12 # 80001000 +80000014: 00001117 auipc sp,0x1 +80000018: ffc10113 addi sp,sp,-4 # 80001010 +8000001c: 00001097 auipc ra,0x1 +80000020: 00408093 addi ra,ra,4 # 80001020 +80000024: 00500293 li t0,5 +80000028: 00600313 li t1,6 +8000002c: 0001a203 lw tp,0(gp) +80000030: 00412023 sw tp,0(sp) +80000034: 0011a203 lw tp,1(gp) +80000038: 00412223 sw tp,4(sp) +8000003c: 0021a203 lw tp,2(gp) +80000040: 00412423 sw tp,8(sp) +80000044: 0031a203 lw tp,3(gp) +80000048: 00412623 sw tp,12(sp) +8000004c: 00001197 auipc gp,0x1 +80000050: fb818193 addi gp,gp,-72 # 80001004 +80000054: 00001117 auipc sp,0x1 +80000058: fe410113 addi sp,sp,-28 # 80001038 +8000005c: 00001097 auipc ra,0x1 +80000060: ffc08093 addi ra,ra,-4 # 80001058 +80000064: 00500293 li t0,5 +80000068: 00600313 li t1,6 +8000006c: 00019203 lh tp,0(gp) +80000070: 00412023 sw tp,0(sp) +80000074: 00119203 lh tp,1(gp) +80000078: 00412223 sw tp,4(sp) +8000007c: 00219203 lh tp,2(gp) +80000080: 00412423 sw tp,8(sp) +80000084: 00319203 lh tp,3(gp) +80000088: 00412623 sw tp,12(sp) +8000008c: 0001d203 lhu tp,0(gp) +80000090: 00412823 sw tp,16(sp) +80000094: 0011d203 lhu tp,1(gp) +80000098: 00412a23 sw tp,20(sp) +8000009c: 0021d203 lhu tp,2(gp) +800000a0: 00412c23 sw tp,24(sp) +800000a4: 0031d203 lhu tp,3(gp) +800000a8: 00412e23 sw tp,28(sp) +800000ac: 00001117 auipc sp,0x1 +800000b0: fcc10113 addi sp,sp,-52 # 80001078 +800000b4: 00001097 auipc ra,0x1 +800000b8: fd408093 addi ra,ra,-44 # 80001088 +800000bc: 00000313 li t1,0 +800000c0: 9999a2b7 lui t0,0x9999a +800000c4: 99928293 addi t0,t0,-1639 # 99999999 <_end+0x199988d9> +800000c8: 00512023 sw t0,0(sp) +800000cc: 00512223 sw t0,4(sp) +800000d0: 00512423 sw t0,8(sp) +800000d4: 00512623 sw t0,12(sp) +800000d8: 00612023 sw t1,0(sp) +800000dc: 00410113 addi sp,sp,4 +800000e0: 006120a3 sw t1,1(sp) +800000e4: 00410113 addi sp,sp,4 +800000e8: 00612123 sw t1,2(sp) +800000ec: 00410113 addi sp,sp,4 +800000f0: 006121a3 sw t1,3(sp) +800000f4: 00001117 auipc sp,0x1 +800000f8: fac10113 addi sp,sp,-84 # 800010a0 +800000fc: 00001097 auipc ra,0x1 +80000100: fb408093 addi ra,ra,-76 # 800010b0 +80000104: 00000313 li t1,0 +80000108: 9999a2b7 lui t0,0x9999a +8000010c: 99928293 addi t0,t0,-1639 # 99999999 <_end+0x199988d9> +80000110: 00512023 sw t0,0(sp) +80000114: 00512223 sw t0,4(sp) +80000118: 00512423 sw t0,8(sp) +8000011c: 00512623 sw t0,12(sp) +80000120: 00611023 sh t1,0(sp) +80000124: 00410113 addi sp,sp,4 +80000128: 006110a3 sh t1,1(sp) +8000012c: 00410113 addi sp,sp,4 +80000130: 00611123 sh t1,2(sp) +80000134: 00410113 addi sp,sp,4 +80000138: 006111a3 sh t1,3(sp) +8000013c: 305f9073 csrw mtvec,t6 +80000140: 02c0006f j 8000016c + +80000144 <_trap_handler>: +80000144: 34102f73 csrr t5,mepc +80000148: 004f0f13 addi t5,t5,4 +8000014c: 341f1073 csrw mepc,t5 +80000150: 34302f73 csrr t5,mbadaddr +80000154: 003f7f13 andi t5,t5,3 +80000158: 01e0a023 sw t5,0(ra) +8000015c: 34202f73 csrr t5,mcause +80000160: 01e0a223 sw t5,4(ra) +80000164: 00808093 addi ra,ra,8 +80000168: 30200073 mret + +8000016c : +8000016c: 00001517 auipc a0,0x1 +80000170: ea450513 addi a0,a0,-348 # 80001010 +80000174: 00001597 auipc a1,0x1 +80000178: f4c58593 addi a1,a1,-180 # 800010c0 <_end> +8000017c: f0100637 lui a2,0xf0100 +80000180: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee6c> + +80000184 : +80000184: 02b50663 beq a0,a1,800001b0 +80000188: 00c52683 lw a3,12(a0) +8000018c: 00d62023 sw a3,0(a2) +80000190: 00852683 lw a3,8(a0) +80000194: 00d62023 sw a3,0(a2) +80000198: 00452683 lw a3,4(a0) +8000019c: 00d62023 sw a3,0(a2) +800001a0: 00052683 lw a3,0(a0) +800001a4: 00d62023 sw a3,0(a2) +800001a8: 01050513 addi a0,a0,16 +800001ac: fd9ff06f j 80000184 + +800001b0 : +800001b0: f0100537 lui a0,0xf0100 +800001b4: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee60> +800001b8: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: b1c1 j 80000cc0 +80001002: 91a1 srli a1,a1,0x28 + +80001004 : +80001004: f202 fsw ft0,36(sp) +80001006: d2e2 sw s8,100(sp) + ... + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff + +80001058 : +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff + +80001088 : +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff + +800010b0 : +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff diff --git a/src/test/resources/asm/I-NOP-01.elf.objdump b/src/test/resources/asm/I-NOP-01.elf.objdump new file mode 100644 index 0000000..7b02fd1 --- /dev/null +++ b/src/test/resources/asm/I-NOP-01.elf.objdump @@ -0,0 +1,183 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-NOP-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00200113 li sp,2 +8000000c: 00300193 li gp,3 +80000010: 00400213 li tp,4 +80000014: 00500293 li t0,5 +80000018: 00600313 li t1,6 +8000001c: 00700393 li t2,7 +80000020: 00800413 li s0,8 +80000024: 00900493 li s1,9 +80000028: 00a00513 li a0,10 +8000002c: 00b00593 li a1,11 +80000030: 00c00613 li a2,12 +80000034: 00d00693 li a3,13 +80000038: 00e00713 li a4,14 +8000003c: 00f00793 li a5,15 +80000040: 01000813 li a6,16 +80000044: 01100893 li a7,17 +80000048: 01200913 li s2,18 +8000004c: 01300993 li s3,19 +80000050: 01400a13 li s4,20 +80000054: 01500a93 li s5,21 +80000058: 01600b13 li s6,22 +8000005c: 01700b93 li s7,23 +80000060: 01800c13 li s8,24 +80000064: 01900c93 li s9,25 +80000068: 01a00d13 li s10,26 +8000006c: 01b00d93 li s11,27 +80000070: 01c00e13 li t3,28 +80000074: 01d00e93 li t4,29 +80000078: 01e00f13 li t5,30 +8000007c: 01f00f93 li t6,31 +80000080: 00000013 nop +80000084: 00000013 nop +80000088: 00000013 nop +8000008c: 00000013 nop +80000090: 00000013 nop +80000094: 00000013 nop +80000098: 0000a023 sw zero,0(ra) # 80001000 +8000009c: 0020a223 sw sp,4(ra) +800000a0: 0030a423 sw gp,8(ra) +800000a4: 0040a623 sw tp,12(ra) +800000a8: 0050a823 sw t0,16(ra) +800000ac: 0060aa23 sw t1,20(ra) +800000b0: 0070ac23 sw t2,24(ra) +800000b4: 0080ae23 sw s0,28(ra) +800000b8: 0290a023 sw s1,32(ra) +800000bc: 02a0a223 sw a0,36(ra) +800000c0: 02b0a423 sw a1,40(ra) +800000c4: 02c0a623 sw a2,44(ra) +800000c8: 02d0a823 sw a3,48(ra) +800000cc: 02e0aa23 sw a4,52(ra) +800000d0: 02f0ac23 sw a5,56(ra) +800000d4: 0300ae23 sw a6,60(ra) +800000d8: 0510a023 sw a7,64(ra) +800000dc: 0520a223 sw s2,68(ra) +800000e0: 0530a423 sw s3,72(ra) +800000e4: 0540a623 sw s4,76(ra) +800000e8: 0550a823 sw s5,80(ra) +800000ec: 0560aa23 sw s6,84(ra) +800000f0: 0570ac23 sw s7,88(ra) +800000f4: 0580ae23 sw s8,92(ra) +800000f8: 0790a023 sw s9,96(ra) +800000fc: 07a0a223 sw s10,100(ra) +80000100: 07b0a423 sw s11,104(ra) +80000104: 07c0a623 sw t3,108(ra) +80000108: 07d0a823 sw t4,112(ra) +8000010c: 07e0aa23 sw t5,116(ra) +80000110: 07f0ac23 sw t6,120(ra) +80000114: 00001197 auipc gp,0x1 +80000118: f6818193 addi gp,gp,-152 # 8000107c +8000011c: 00000417 auipc s0,0x0 +80000120: 00000013 nop +80000124: 00000013 nop +80000128: 00000013 nop +8000012c: 00000013 nop +80000130: 00000013 nop +80000134: 00000497 auipc s1,0x0 +80000138: 408484b3 sub s1,s1,s0 +8000013c: 0091a023 sw s1,0(gp) +80000140: 00001517 auipc a0,0x1 +80000144: ec050513 addi a0,a0,-320 # 80001000 +80000148: 00001597 auipc a1,0x1 +8000014c: f3858593 addi a1,a1,-200 # 80001080 <_end> +80000150: f0100637 lui a2,0xf0100 +80000154: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feeac> + +80000158 : +80000158: 02b50663 beq a0,a1,80000184 +8000015c: 00c52683 lw a3,12(a0) +80000160: 00d62023 sw a3,0(a2) +80000164: 00852683 lw a3,8(a0) +80000168: 00d62023 sw a3,0(a2) +8000016c: 00452683 lw a3,4(a0) +80000170: 00d62023 sw a3,0(a2) +80000174: 00052683 lw a3,0(a0) +80000178: 00d62023 sw a3,0(a2) +8000017c: 01050513 addi a0,a0,16 +80000180: fd9ff06f j 80000158 + +80000184 : +80000184: f0100537 lui a0,0xf0100 +80000188: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feea0> +8000018c: 00052023 sw zero,0(a0) +80000190: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff + +8000107c : +8000107c: ffff 0xffff +8000107e: ffff 0xffff diff --git a/src/test/resources/asm/I-OR-01.elf.objdump b/src/test/resources/asm/I-OR-01.elf.objdump new file mode 100644 index 0000000..b8d87b9 --- /dev/null +++ b/src/test/resources/asm/I-OR-01.elf.objdump @@ -0,0 +1,350 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-OR-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef1f> +80000028: 80000437 lui s0,0x80000 +8000002c: 0041e233 or tp,gp,tp +80000030: 0051e2b3 or t0,gp,t0 +80000034: 0061e333 or t1,gp,t1 +80000038: 0071e3b3 or t2,gp,t2 +8000003c: 0081e433 or s0,gp,s0 +80000040: 00312023 sw gp,0(sp) +80000044: 00412223 sw tp,4(sp) +80000048: 00512423 sw t0,8(sp) +8000004c: 00612623 sw t1,12(sp) +80000050: 00712823 sw t2,16(sp) +80000054: 00812a23 sw s0,20(sp) +80000058: 00001097 auipc ra,0x1 +8000005c: fac08093 addi ra,ra,-84 # 80001004 +80000060: 00001117 auipc sp,0x1 +80000064: fe810113 addi sp,sp,-24 # 80001048 +80000068: 0000a403 lw s0,0(ra) +8000006c: 00000493 li s1,0 +80000070: 00100513 li a0,1 +80000074: fff00593 li a1,-1 +80000078: 80000637 lui a2,0x80000 +8000007c: fff60613 addi a2,a2,-1 # 7fffffff <_end+0xffffef1f> +80000080: 800006b7 lui a3,0x80000 +80000084: 009464b3 or s1,s0,s1 +80000088: 00a46533 or a0,s0,a0 +8000008c: 00b465b3 or a1,s0,a1 +80000090: 00c46633 or a2,s0,a2 +80000094: 00d466b3 or a3,s0,a3 +80000098: 00812023 sw s0,0(sp) +8000009c: 00912223 sw s1,4(sp) +800000a0: 00a12423 sw a0,8(sp) +800000a4: 00b12623 sw a1,12(sp) +800000a8: 00c12823 sw a2,16(sp) +800000ac: 00d12a23 sw a3,20(sp) +800000b0: 00001097 auipc ra,0x1 +800000b4: f5808093 addi ra,ra,-168 # 80001008 +800000b8: 00001117 auipc sp,0x1 +800000bc: fa810113 addi sp,sp,-88 # 80001060 +800000c0: 0000a683 lw a3,0(ra) +800000c4: 00000713 li a4,0 +800000c8: 00100793 li a5,1 +800000cc: fff00813 li a6,-1 +800000d0: 800008b7 lui a7,0x80000 +800000d4: fff88893 addi a7,a7,-1 # 7fffffff <_end+0xffffef1f> +800000d8: 80000937 lui s2,0x80000 +800000dc: 00e6e733 or a4,a3,a4 +800000e0: 00f6e7b3 or a5,a3,a5 +800000e4: 0106e833 or a6,a3,a6 +800000e8: 0116e8b3 or a7,a3,a7 +800000ec: 0126e933 or s2,a3,s2 +800000f0: 00d12023 sw a3,0(sp) +800000f4: 00e12223 sw a4,4(sp) +800000f8: 00f12423 sw a5,8(sp) +800000fc: 01012623 sw a6,12(sp) +80000100: 01112823 sw a7,16(sp) +80000104: 01212a23 sw s2,20(sp) +80000108: 00001097 auipc ra,0x1 +8000010c: f0408093 addi ra,ra,-252 # 8000100c +80000110: 00001117 auipc sp,0x1 +80000114: f6810113 addi sp,sp,-152 # 80001078 +80000118: 0000a903 lw s2,0(ra) +8000011c: 00000993 li s3,0 +80000120: 00100a13 li s4,1 +80000124: fff00a93 li s5,-1 +80000128: 80000b37 lui s6,0x80000 +8000012c: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef1f> +80000130: 80000bb7 lui s7,0x80000 +80000134: 013969b3 or s3,s2,s3 +80000138: 01496a33 or s4,s2,s4 +8000013c: 01596ab3 or s5,s2,s5 +80000140: 01696b33 or s6,s2,s6 +80000144: 01796bb3 or s7,s2,s7 +80000148: 01212023 sw s2,0(sp) +8000014c: 01312223 sw s3,4(sp) +80000150: 01412423 sw s4,8(sp) +80000154: 01512623 sw s5,12(sp) +80000158: 01612823 sw s6,16(sp) +8000015c: 01712a23 sw s7,20(sp) +80000160: 00001097 auipc ra,0x1 +80000164: eb008093 addi ra,ra,-336 # 80001010 +80000168: 00001117 auipc sp,0x1 +8000016c: f2810113 addi sp,sp,-216 # 80001090 +80000170: 0000ab83 lw s7,0(ra) +80000174: 00000c13 li s8,0 +80000178: 00100c93 li s9,1 +8000017c: fff00d13 li s10,-1 +80000180: 80000db7 lui s11,0x80000 +80000184: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef1f> +80000188: 80000e37 lui t3,0x80000 +8000018c: 018bec33 or s8,s7,s8 +80000190: 019becb3 or s9,s7,s9 +80000194: 01abed33 or s10,s7,s10 +80000198: 01bbedb3 or s11,s7,s11 +8000019c: 01cbee33 or t3,s7,t3 +800001a0: 01712023 sw s7,0(sp) +800001a4: 01812223 sw s8,4(sp) +800001a8: 01912423 sw s9,8(sp) +800001ac: 01a12623 sw s10,12(sp) +800001b0: 01b12823 sw s11,16(sp) +800001b4: 01c12a23 sw t3,20(sp) +800001b8: 00001c97 auipc s9,0x1 +800001bc: e5cc8c93 addi s9,s9,-420 # 80001014 +800001c0: 00001d17 auipc s10,0x1 +800001c4: ee8d0d13 addi s10,s10,-280 # 800010a8 +800001c8: 000cae03 lw t3,0(s9) +800001cc: 01000213 li tp,16 +800001d0: 02000293 li t0,32 +800001d4: 04000313 li t1,64 +800001d8: 08000393 li t2,128 +800001dc: 10000413 li s0,256 +800001e0: 80000493 li s1,-2048 +800001e4: 004e6eb3 or t4,t3,tp +800001e8: 005eef33 or t5,t4,t0 +800001ec: 006f6fb3 or t6,t5,t1 +800001f0: 007fe0b3 or ra,t6,t2 +800001f4: 0080e133 or sp,ra,s0 +800001f8: 009161b3 or gp,sp,s1 +800001fc: 004d2023 sw tp,0(s10) +80000200: 01cd2223 sw t3,4(s10) +80000204: 01dd2423 sw t4,8(s10) +80000208: 01ed2623 sw t5,12(s10) +8000020c: 01fd2823 sw t6,16(s10) +80000210: 001d2a23 sw ra,20(s10) +80000214: 002d2c23 sw sp,24(s10) +80000218: 003d2e23 sw gp,28(s10) +8000021c: 00001097 auipc ra,0x1 +80000220: dfc08093 addi ra,ra,-516 # 80001018 +80000224: 00001117 auipc sp,0x1 +80000228: ea410113 addi sp,sp,-348 # 800010c8 +8000022c: 0000ae03 lw t3,0(ra) +80000230: f7ff9db7 lui s11,0xf7ff9 +80000234: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +80000238: 01be6033 or zero,t3,s11 +8000023c: 00012023 sw zero,0(sp) +80000240: 00001097 auipc ra,0x1 +80000244: ddc08093 addi ra,ra,-548 # 8000101c +80000248: 00001117 auipc sp,0x1 +8000024c: e8410113 addi sp,sp,-380 # 800010cc +80000250: 0000ae03 lw t3,0(ra) +80000254: f7ff9db7 lui s11,0xf7ff9 +80000258: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +8000025c: 01be6033 or zero,t3,s11 +80000260: 000062b3 or t0,zero,zero +80000264: 00012023 sw zero,0(sp) +80000268: 00512223 sw t0,4(sp) +8000026c: 00001097 auipc ra,0x1 +80000270: db408093 addi ra,ra,-588 # 80001020 +80000274: 00001117 auipc sp,0x1 +80000278: e6010113 addi sp,sp,-416 # 800010d4 +8000027c: 0000a183 lw gp,0(ra) +80000280: 0001e233 or tp,gp,zero +80000284: 000262b3 or t0,tp,zero +80000288: 00506333 or t1,zero,t0 +8000028c: 00036733 or a4,t1,zero +80000290: 000767b3 or a5,a4,zero +80000294: 0007e833 or a6,a5,zero +80000298: 01006cb3 or s9,zero,a6 +8000029c: 01906d33 or s10,zero,s9 +800002a0: 000d6db3 or s11,s10,zero +800002a4: 00412023 sw tp,0(sp) +800002a8: 01a12223 sw s10,4(sp) +800002ac: 01b12423 sw s11,8(sp) +800002b0: 00001517 auipc a0,0x1 +800002b4: d8050513 addi a0,a0,-640 # 80001030 +800002b8: 00001597 auipc a1,0x1 +800002bc: e2858593 addi a1,a1,-472 # 800010e0 <_end> +800002c0: f0100637 lui a2,0xf0100 +800002c4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +800002c8 : +800002c8: 02b50663 beq a0,a1,800002f4 +800002cc: 00c52683 lw a3,12(a0) +800002d0: 00d62023 sw a3,0(a2) +800002d4: 00852683 lw a3,8(a0) +800002d8: 00d62023 sw a3,0(a2) +800002dc: 00452683 lw a3,4(a0) +800002e0: 00d62023 sw a3,0(a2) +800002e4: 00052683 lw a3,0(a0) +800002e8: 00d62023 sw a3,0(a2) +800002ec: 01050513 addi a0,a0,16 +800002f0: fd9ff06f j 800002c8 + +800002f4 : +800002f4: f0100537 lui a0,0xf0100 +800002f8: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +800002fc: 00052023 sw zero,0(a0) +80000300: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: 000d c.nop 3 + ... + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 5814 lw a3,48(s0) +80001022: 3692 fld fa3,288(sp) + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff + +800010cc : +800010cc: ffff 0xffff +800010ce: ffff 0xffff +800010d0: ffff 0xffff +800010d2: ffff 0xffff + +800010d4 : +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-ORI-01.elf.objdump b/src/test/resources/asm/I-ORI-01.elf.objdump new file mode 100644 index 0000000..ab49e01 --- /dev/null +++ b/src/test/resources/asm/I-ORI-01.elf.objdump @@ -0,0 +1,310 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-ORI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 0011e213 ori tp,gp,1 +80000018: 7ff1e293 ori t0,gp,2047 +8000001c: fff1e313 ori t1,gp,-1 +80000020: 0001e393 ori t2,gp,0 +80000024: 8001e413 ori s0,gp,-2048 +80000028: 00312023 sw gp,0(sp) +8000002c: 00412223 sw tp,4(sp) +80000030: 00512423 sw t0,8(sp) +80000034: 00612623 sw t1,12(sp) +80000038: 00712823 sw t2,16(sp) +8000003c: 00812a23 sw s0,20(sp) +80000040: 00001097 auipc ra,0x1 +80000044: fc408093 addi ra,ra,-60 # 80001004 +80000048: 00001117 auipc sp,0x1 +8000004c: 00010113 mv sp,sp +80000050: 0000a403 lw s0,0(ra) +80000054: 00146493 ori s1,s0,1 +80000058: 7ff46513 ori a0,s0,2047 +8000005c: fff46593 ori a1,s0,-1 +80000060: 00046613 ori a2,s0,0 +80000064: 80046693 ori a3,s0,-2048 +80000068: 00812023 sw s0,0(sp) # 80001048 +8000006c: 00912223 sw s1,4(sp) +80000070: 00a12423 sw a0,8(sp) +80000074: 00b12623 sw a1,12(sp) +80000078: 00c12823 sw a2,16(sp) +8000007c: 00d12a23 sw a3,20(sp) +80000080: 00001097 auipc ra,0x1 +80000084: f8808093 addi ra,ra,-120 # 80001008 +80000088: 00001117 auipc sp,0x1 +8000008c: fd810113 addi sp,sp,-40 # 80001060 +80000090: 0000a683 lw a3,0(ra) +80000094: 0016e713 ori a4,a3,1 +80000098: 7ff6e793 ori a5,a3,2047 +8000009c: fff6e813 ori a6,a3,-1 +800000a0: 0006e893 ori a7,a3,0 +800000a4: 8006e913 ori s2,a3,-2048 +800000a8: 00d12023 sw a3,0(sp) +800000ac: 00e12223 sw a4,4(sp) +800000b0: 00f12423 sw a5,8(sp) +800000b4: 01012623 sw a6,12(sp) +800000b8: 01112823 sw a7,16(sp) +800000bc: 01212a23 sw s2,20(sp) +800000c0: 00001097 auipc ra,0x1 +800000c4: f4c08093 addi ra,ra,-180 # 8000100c +800000c8: 00001117 auipc sp,0x1 +800000cc: fb010113 addi sp,sp,-80 # 80001078 +800000d0: 0000a903 lw s2,0(ra) +800000d4: 00196993 ori s3,s2,1 +800000d8: 7ff96a13 ori s4,s2,2047 +800000dc: fff96a93 ori s5,s2,-1 +800000e0: 00096b13 ori s6,s2,0 +800000e4: 80096b93 ori s7,s2,-2048 +800000e8: 01212023 sw s2,0(sp) +800000ec: 01312223 sw s3,4(sp) +800000f0: 01412423 sw s4,8(sp) +800000f4: 01512623 sw s5,12(sp) +800000f8: 01612823 sw s6,16(sp) +800000fc: 01712a23 sw s7,20(sp) +80000100: 00001097 auipc ra,0x1 +80000104: f1008093 addi ra,ra,-240 # 80001010 +80000108: 00001117 auipc sp,0x1 +8000010c: f8810113 addi sp,sp,-120 # 80001090 +80000110: 0000ab83 lw s7,0(ra) +80000114: 001bec13 ori s8,s7,1 +80000118: 7ffbec93 ori s9,s7,2047 +8000011c: fffbed13 ori s10,s7,-1 +80000120: 000bed93 ori s11,s7,0 +80000124: 800bee13 ori t3,s7,-2048 +80000128: 01712023 sw s7,0(sp) +8000012c: 01812223 sw s8,4(sp) +80000130: 01912423 sw s9,8(sp) +80000134: 01a12623 sw s10,12(sp) +80000138: 01b12823 sw s11,16(sp) +8000013c: 01c12a23 sw t3,20(sp) +80000140: 00001d17 auipc s10,0x1 +80000144: ed4d0d13 addi s10,s10,-300 # 80001014 +80000148: 00001d97 auipc s11,0x1 +8000014c: f60d8d93 addi s11,s11,-160 # 800010a8 +80000150: 000d2e03 lw t3,0(s10) +80000154: 010e6e93 ori t4,t3,16 +80000158: 020eef13 ori t5,t4,32 +8000015c: 040f6f93 ori t6,t5,64 +80000160: 080fe093 ori ra,t6,128 +80000164: 1000e113 ori sp,ra,256 +80000168: 80016193 ori gp,sp,-2048 +8000016c: 01cda023 sw t3,0(s11) +80000170: 01dda223 sw t4,4(s11) +80000174: 01eda423 sw t5,8(s11) +80000178: 01fda623 sw t6,12(s11) +8000017c: 001da823 sw ra,16(s11) +80000180: 002daa23 sw sp,20(s11) +80000184: 003dac23 sw gp,24(s11) +80000188: 00001097 auipc ra,0x1 +8000018c: e9008093 addi ra,ra,-368 # 80001018 +80000190: 00001117 auipc sp,0x1 +80000194: f3410113 addi sp,sp,-204 # 800010c4 +80000198: 0000a283 lw t0,0(ra) +8000019c: 0012e013 ori zero,t0,1 +800001a0: 00012023 sw zero,0(sp) +800001a4: 00001097 auipc ra,0x1 +800001a8: e7808093 addi ra,ra,-392 # 8000101c +800001ac: 00001117 auipc sp,0x1 +800001b0: f1c10113 addi sp,sp,-228 # 800010c8 +800001b4: 0000a283 lw t0,0(ra) +800001b8: 0012e013 ori zero,t0,1 +800001bc: 00106293 ori t0,zero,1 +800001c0: 00012023 sw zero,0(sp) +800001c4: 00512223 sw t0,4(sp) +800001c8: 00001097 auipc ra,0x1 +800001cc: e5808093 addi ra,ra,-424 # 80001020 +800001d0: 00001117 auipc sp,0x1 +800001d4: f0010113 addi sp,sp,-256 # 800010d0 +800001d8: 0000a183 lw gp,0(ra) +800001dc: 0001e213 ori tp,gp,0 +800001e0: 00026293 ori t0,tp,0 +800001e4: 0002e313 ori t1,t0,0 +800001e8: 00036713 ori a4,t1,0 +800001ec: 00076793 ori a5,a4,0 +800001f0: 0007e813 ori a6,a5,0 +800001f4: 00086c93 ori s9,a6,0 +800001f8: 000ced13 ori s10,s9,0 +800001fc: 000d6d93 ori s11,s10,0 +80000200: 00312023 sw gp,0(sp) +80000204: 00412223 sw tp,4(sp) +80000208: 01a12423 sw s10,8(sp) +8000020c: 01b12623 sw s11,12(sp) +80000210: 00001517 auipc a0,0x1 +80000214: e2050513 addi a0,a0,-480 # 80001030 +80000218: 00001597 auipc a1,0x1 +8000021c: ec858593 addi a1,a1,-312 # 800010e0 <_end> +80000220: f0100637 lui a2,0xf0100 +80000224: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +80000228 : +80000228: 02b50663 beq a0,a1,80000254 +8000022c: 00c52683 lw a3,12(a0) +80000230: 00d62023 sw a3,0(a2) +80000234: 00852683 lw a3,8(a0) +80000238: 00d62023 sw a3,0(a2) +8000023c: 00452683 lw a3,4(a0) +80000240: 00d62023 sw a3,0(a2) +80000244: 00052683 lw a3,0(a0) +80000248: 00d62023 sw a3,0(a2) +8000024c: 01050513 addi a0,a0,16 +80000250: fd9ff06f j 80000228 + +80000254 : +80000254: f0100537 lui a0,0xf0100 +80000258: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +8000025c: 00052023 sw zero,0(a0) +80000260: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: 000d c.nop 3 + ... + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 5814 lw a3,48(s0) +80001022: 3692 fld fa3,288(sp) + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff + +800010c4 : +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff +800010cc: ffff 0xffff +800010ce: ffff 0xffff + +800010d0 : +800010d0: ffff 0xffff +800010d2: ffff 0xffff +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-RF_size-01.elf.objdump b/src/test/resources/asm/I-RF_size-01.elf.objdump new file mode 100644 index 0000000..f617c7d --- /dev/null +++ b/src/test/resources/asm/I-RF_size-01.elf.objdump @@ -0,0 +1,218 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-RF_size-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001817 auipc a6,0x1 +80000004: 00080813 mv a6,a6 +80000008: 42727037 lui zero,0x42727 +8000000c: e6f00013 li zero,-401 +80000010: 563330b7 lui ra,0x56333 +80000014: 24908093 addi ra,ra,585 # 56333249 <_start-0x29cccdb7> +80000018: 2d562137 lui sp,0x2d562 +8000001c: 05210113 addi sp,sp,82 # 2d562052 <_start-0x52a9dfae> +80000020: 526971b7 lui gp,0x52697 +80000024: 36318193 addi gp,gp,867 # 52697363 <_start-0x2d968c9d> +80000028: 736b8237 lui tp,0x736b8 +8000002c: 92020213 addi tp,tp,-1760 # 736b7920 <_start-0xc9486e0> +80000030: 737462b7 lui t0,0x73746 +80000034: 57228293 addi t0,t0,1394 # 73746572 <_start-0xc8b9a8e> +80000038: 6e205337 lui t1,0x6e205 +8000003c: e6f30313 addi t1,t1,-401 # 6e204e6f <_start-0x11dfb191> +80000040: 4d6973b7 lui t2,0x4d697 +80000044: c6138393 addi t2,t2,-927 # 4d696c61 <_start-0x3296939f> +80000048: 6f646437 lui s0,0x6f646 +8000004c: 17340413 addi s0,s0,371 # 6f646173 <_start-0x109b9e8d> +80000050: 6b7944b7 lui s1,0x6b794 +80000054: 06348493 addi s1,s1,99 # 6b794063 <_start-0x1486bf9d> +80000058: 74657537 lui a0,0x74657 +8000005c: 27350513 addi a0,a0,627 # 74657273 <_start-0xb9a8d8d> +80000060: 286e75b7 lui a1,0x286e7 +80000064: f7358593 addi a1,a1,-141 # 286e6f73 <_start-0x5791908d> +80000068: 656b2637 lui a2,0x656b2 +8000006c: 04860613 addi a2,a2,72 # 656b2048 <_start-0x1a94dfb8> +80000070: 205266b7 lui a3,0x20526 +80000074: 16468693 addi a3,a3,356 # 20526164 <_start-0x5fad9e9c> +80000078: 6f6d3737 lui a4,0x6f6d3 +8000007c: 92c70713 addi a4,a4,-1748 # 6f6d292c <_start-0x1092d6d4> +80000080: 697037b7 lui a5,0x69703 +80000084: e6378793 addi a5,a5,-413 # 69702e63 <_start-0x168fd19d> +80000088: 00082023 sw zero,0(a6) # 80001000 +8000008c: 00182223 sw ra,4(a6) +80000090: 00282423 sw sp,8(a6) +80000094: 00382623 sw gp,12(a6) +80000098: 00482823 sw tp,16(a6) +8000009c: 00582a23 sw t0,20(a6) +800000a0: 00682c23 sw t1,24(a6) +800000a4: 00782e23 sw t2,28(a6) +800000a8: 02882023 sw s0,32(a6) +800000ac: 02982223 sw s1,36(a6) +800000b0: 02a82423 sw a0,40(a6) +800000b4: 02b82623 sw a1,44(a6) +800000b8: 02c82823 sw a2,48(a6) +800000bc: 02d82a23 sw a3,52(a6) +800000c0: 02e82c23 sw a4,56(a6) +800000c4: 02f82e23 sw a5,60(a6) +800000c8: 00001217 auipc tp,0x1 +800000cc: f7820213 addi tp,tp,-136 # 80001040 +800000d0: 636f6837 lui a6,0x636f6 +800000d4: 46180813 addi a6,a6,1121 # 636f6461 <_start-0x1c909b9f> +800000d8: 6a6578b7 lui a7,0x6a657 +800000dc: b4088893 addi a7,a7,-1216 # 6a656b40 <_start-0x159a94c0> +800000e0: 20287937 lui s2,0x20287 +800000e4: 86190913 addi s2,s2,-1951 # 20286861 <_start-0x5fd7979f> +800000e8: 616a69b7 lui s3,0x616a6 +800000ec: 56b98993 addi s3,s3,1387 # 616a656b <_start-0x1e959a95> +800000f0: 61766a37 lui s4,0x61766 +800000f4: 520a0a13 addi s4,s4,1312 # 61766520 <_start-0x1e899ae0> +800000f8: 2e205ab7 lui s5,0x2e205 +800000fc: c65a8a93 addi s5,s5,-923 # 2e204c65 <_start-0x51dfb39b> +80000100: 636f7b37 lui s6,0x636f7 +80000104: d29b0b13 addi s6,s6,-727 # 636f6d29 <_start-0x1c9092d7> +80000108: 73697bb7 lui s7,0x73697 +8000010c: 02eb8b93 addi s7,s7,46 # 7369702e <_start-0xc968fd2> +80000110: 66208c37 lui s8,0x66208 +80000114: 96fc0c13 addi s8,s8,-1681 # 6620796f <_start-0x19df8691> +80000118: 67652cb7 lui s9,0x67652 +8000011c: 069c8c93 addi s9,s9,105 # 67652069 <_start-0x189adf97> +80000120: 65737d37 lui s10,0x65737 +80000124: 361d0d13 addi s10,s10,865 # 65737361 <_start-0x1a8c8c9f> +80000128: 75732db7 lui s11,0x75732 +8000012c: 06dd8d93 addi s11,s11,109 # 7573206d <_start-0xa8cdf93> +80000130: 3a291e37 lui t3,0x3a291 +80000134: d0ae0e13 addi t3,t3,-758 # 3a290d0a <_start-0x45d6f2f6> +80000138: 68697eb7 lui t4,0x68697 +8000013c: 320e8e93 addi t4,t4,800 # 68697320 <_start-0x17968ce0> +80000140: 61642f37 lui t5,0x61642 +80000144: 074f0f13 addi t5,t5,116 # 61642074 <_start-0x1e9bdf8c> +80000148: 75207fb7 lui t6,0x75207 +8000014c: 265f8f93 addi t6,t6,613 # 75207265 <_start-0xadf8d9b> +80000150: 01022023 sw a6,0(tp) # 0 <_start-0x80000000> +80000154: 01122223 sw a7,4(tp) # 4 <_start-0x7ffffffc> +80000158: 01222423 sw s2,8(tp) # 8 <_start-0x7ffffff8> +8000015c: 01322623 sw s3,12(tp) # c <_start-0x7ffffff4> +80000160: 01422823 sw s4,16(tp) # 10 <_start-0x7ffffff0> +80000164: 01522a23 sw s5,20(tp) # 14 <_start-0x7fffffec> +80000168: 01622c23 sw s6,24(tp) # 18 <_start-0x7fffffe8> +8000016c: 01722e23 sw s7,28(tp) # 1c <_start-0x7fffffe4> +80000170: 03822023 sw s8,32(tp) # 20 <_start-0x7fffffe0> +80000174: 03922223 sw s9,36(tp) # 24 <_start-0x7fffffdc> +80000178: 03a22423 sw s10,40(tp) # 28 <_start-0x7fffffd8> +8000017c: 03b22623 sw s11,44(tp) # 2c <_start-0x7fffffd4> +80000180: 03c22823 sw t3,48(tp) # 30 <_start-0x7fffffd0> +80000184: 03d22a23 sw t4,52(tp) # 34 <_start-0x7fffffcc> +80000188: 03e22c23 sw t5,56(tp) # 38 <_start-0x7fffffc8> +8000018c: 03f22e23 sw t6,60(tp) # 3c <_start-0x7fffffc4> +80000190: 00001217 auipc tp,0x1 +80000194: ef020213 addi tp,tp,-272 # 80001080 +80000198: 00022023 sw zero,0(tp) # 0 <_start-0x80000000> +8000019c: 00122223 sw ra,4(tp) # 4 <_start-0x7ffffffc> +800001a0: 00222423 sw sp,8(tp) # 8 <_start-0x7ffffff8> +800001a4: 00322623 sw gp,12(tp) # c <_start-0x7ffffff4> +800001a8: 00001517 auipc a0,0x1 +800001ac: e5850513 addi a0,a0,-424 # 80001000 +800001b0: 00001597 auipc a1,0x1 +800001b4: ee058593 addi a1,a1,-288 # 80001090 <_end> +800001b8: f0100637 lui a2,0xf0100 +800001bc: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee9c> + +800001c0 : +800001c0: 02b50663 beq a0,a1,800001ec +800001c4: 00c52683 lw a3,12(a0) +800001c8: 00d62023 sw a3,0(a2) +800001cc: 00852683 lw a3,8(a0) +800001d0: 00d62023 sw a3,0(a2) +800001d4: 00452683 lw a3,4(a0) +800001d8: 00d62023 sw a3,0(a2) +800001dc: 00052683 lw a3,0(a0) +800001e0: 00d62023 sw a3,0(a2) +800001e4: 01050513 addi a0,a0,16 +800001e8: fd9ff06f j 800001c0 + +800001ec : +800001ec: f0100537 lui a0,0xf0100 +800001f0: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee90> +800001f4: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff + +80001040 : +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff diff --git a/src/test/resources/asm/I-RF_width-01.elf.objdump b/src/test/resources/asm/I-RF_width-01.elf.objdump new file mode 100644 index 0000000..5e12641 --- /dev/null +++ b/src/test/resources/asm/I-RF_width-01.elf.objdump @@ -0,0 +1,262 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-RF_width-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001817 auipc a6,0x1 +80000004: 00080813 mv a6,a6 +80000008: 00100013 li zero,1 +8000000c: 00100093 li ra,1 +80000010: 00100113 li sp,1 +80000014: 00100193 li gp,1 +80000018: 00100213 li tp,1 +8000001c: 00100293 li t0,1 +80000020: 00100313 li t1,1 +80000024: 00100393 li t2,1 +80000028: 00100413 li s0,1 +8000002c: 00100493 li s1,1 +80000030: 00100513 li a0,1 +80000034: 00100593 li a1,1 +80000038: 00100613 li a2,1 +8000003c: 00100693 li a3,1 +80000040: 00100713 li a4,1 +80000044: 00100793 li a5,1 +80000048: 01f09093 slli ra,ra,0x1f +8000004c: 0000c463 bltz ra,80000054 <_start+0x54> +80000050: 00000093 li ra,0 +80000054: 01f11113 slli sp,sp,0x1f +80000058: 00014463 bltz sp,80000060 <_start+0x60> +8000005c: 00000113 li sp,0 +80000060: 01f19193 slli gp,gp,0x1f +80000064: 0001c463 bltz gp,8000006c <_start+0x6c> +80000068: 00000193 li gp,0 +8000006c: 01f21213 slli tp,tp,0x1f +80000070: 00024463 bltz tp,80000078 <_start+0x78> +80000074: 00000213 li tp,0 +80000078: 01f29293 slli t0,t0,0x1f +8000007c: 0002c463 bltz t0,80000084 <_start+0x84> +80000080: 00000293 li t0,0 +80000084: 01f31313 slli t1,t1,0x1f +80000088: 00034463 bltz t1,80000090 <_start+0x90> +8000008c: 00000313 li t1,0 +80000090: 01f39393 slli t2,t2,0x1f +80000094: 0003c463 bltz t2,8000009c <_start+0x9c> +80000098: 00000393 li t2,0 +8000009c: 01f41413 slli s0,s0,0x1f +800000a0: 00044463 bltz s0,800000a8 <_start+0xa8> +800000a4: 00000413 li s0,0 +800000a8: 01f49493 slli s1,s1,0x1f +800000ac: 0004c463 bltz s1,800000b4 <_start+0xb4> +800000b0: 00000493 li s1,0 +800000b4: 01f51513 slli a0,a0,0x1f +800000b8: 00054463 bltz a0,800000c0 <_start+0xc0> +800000bc: 00000513 li a0,0 +800000c0: 01f59593 slli a1,a1,0x1f +800000c4: 0005c463 bltz a1,800000cc <_start+0xcc> +800000c8: 00000593 li a1,0 +800000cc: 01f61613 slli a2,a2,0x1f +800000d0: 00064463 bltz a2,800000d8 <_start+0xd8> +800000d4: 00000613 li a2,0 +800000d8: 01f69693 slli a3,a3,0x1f +800000dc: 0006c463 bltz a3,800000e4 <_start+0xe4> +800000e0: 00000693 li a3,0 +800000e4: 01f71713 slli a4,a4,0x1f +800000e8: 00074463 bltz a4,800000f0 <_start+0xf0> +800000ec: 00000713 li a4,0 +800000f0: 01f79793 slli a5,a5,0x1f +800000f4: 0007c463 bltz a5,800000fc <_start+0xfc> +800000f8: 00000793 li a5,0 +800000fc: 00082023 sw zero,0(a6) # 80001000 +80000100: 00182223 sw ra,4(a6) +80000104: 00282423 sw sp,8(a6) +80000108: 00382623 sw gp,12(a6) +8000010c: 00482823 sw tp,16(a6) +80000110: 00582a23 sw t0,20(a6) +80000114: 00682c23 sw t1,24(a6) +80000118: 00782e23 sw t2,28(a6) +8000011c: 02882023 sw s0,32(a6) +80000120: 02982223 sw s1,36(a6) +80000124: 02a82423 sw a0,40(a6) +80000128: 02b82623 sw a1,44(a6) +8000012c: 02c82823 sw a2,48(a6) +80000130: 02d82a23 sw a3,52(a6) +80000134: 02e82c23 sw a4,56(a6) +80000138: 02f82e23 sw a5,60(a6) +8000013c: 00001097 auipc ra,0x1 +80000140: f0408093 addi ra,ra,-252 # 80001040 +80000144: 00100813 li a6,1 +80000148: 00100893 li a7,1 +8000014c: 00100913 li s2,1 +80000150: 00100993 li s3,1 +80000154: 00100a13 li s4,1 +80000158: 00100a93 li s5,1 +8000015c: 00100b13 li s6,1 +80000160: 00100b93 li s7,1 +80000164: 00100c13 li s8,1 +80000168: 00100c93 li s9,1 +8000016c: 00100d13 li s10,1 +80000170: 00100d93 li s11,1 +80000174: 00100e13 li t3,1 +80000178: 00100e93 li t4,1 +8000017c: 00100f13 li t5,1 +80000180: 00100f93 li t6,1 +80000184: 01f81813 slli a6,a6,0x1f +80000188: 00084463 bltz a6,80000190 <_start+0x190> +8000018c: 00000813 li a6,0 +80000190: 01f89893 slli a7,a7,0x1f +80000194: 0008c463 bltz a7,8000019c <_start+0x19c> +80000198: 00000893 li a7,0 +8000019c: 01f91913 slli s2,s2,0x1f +800001a0: 00094463 bltz s2,800001a8 <_start+0x1a8> +800001a4: 00000913 li s2,0 +800001a8: 01f99993 slli s3,s3,0x1f +800001ac: 0009c463 bltz s3,800001b4 <_start+0x1b4> +800001b0: 00000993 li s3,0 +800001b4: 01fa1a13 slli s4,s4,0x1f +800001b8: 000a4463 bltz s4,800001c0 <_start+0x1c0> +800001bc: 00000a13 li s4,0 +800001c0: 01fa9a93 slli s5,s5,0x1f +800001c4: 000ac463 bltz s5,800001cc <_start+0x1cc> +800001c8: 00000a93 li s5,0 +800001cc: 01fb1b13 slli s6,s6,0x1f +800001d0: 000b4463 bltz s6,800001d8 <_start+0x1d8> +800001d4: 00000b13 li s6,0 +800001d8: 01fb9b93 slli s7,s7,0x1f +800001dc: 000bc463 bltz s7,800001e4 <_start+0x1e4> +800001e0: 00000b93 li s7,0 +800001e4: 01fc1c13 slli s8,s8,0x1f +800001e8: 000c4463 bltz s8,800001f0 <_start+0x1f0> +800001ec: 00000c13 li s8,0 +800001f0: 01fc9c93 slli s9,s9,0x1f +800001f4: 000cc463 bltz s9,800001fc <_start+0x1fc> +800001f8: 00000c93 li s9,0 +800001fc: 01fd1d13 slli s10,s10,0x1f +80000200: 000d4463 bltz s10,80000208 <_start+0x208> +80000204: 00000d13 li s10,0 +80000208: 01fd9d93 slli s11,s11,0x1f +8000020c: 000dc463 bltz s11,80000214 <_start+0x214> +80000210: 00000d93 li s11,0 +80000214: 01fe1e13 slli t3,t3,0x1f +80000218: 000e4463 bltz t3,80000220 <_start+0x220> +8000021c: 00000e13 li t3,0 +80000220: 01fe9e93 slli t4,t4,0x1f +80000224: 000ec463 bltz t4,8000022c <_start+0x22c> +80000228: 00000e93 li t4,0 +8000022c: 01ff1f13 slli t5,t5,0x1f +80000230: 000f4463 bltz t5,80000238 <_start+0x238> +80000234: 00000f13 li t5,0 +80000238: 01ff9f93 slli t6,t6,0x1f +8000023c: 000fc463 bltz t6,80000244 <_start+0x244> +80000240: 00000f93 li t6,0 +80000244: 0100a023 sw a6,0(ra) +80000248: 0110a223 sw a7,4(ra) +8000024c: 0120a423 sw s2,8(ra) +80000250: 0130a623 sw s3,12(ra) +80000254: 0140a823 sw s4,16(ra) +80000258: 0150aa23 sw s5,20(ra) +8000025c: 0160ac23 sw s6,24(ra) +80000260: 0170ae23 sw s7,28(ra) +80000264: 0380a023 sw s8,32(ra) +80000268: 0390a223 sw s9,36(ra) +8000026c: 03a0a423 sw s10,40(ra) +80000270: 03b0a623 sw s11,44(ra) +80000274: 03c0a823 sw t3,48(ra) +80000278: 03d0aa23 sw t4,52(ra) +8000027c: 03e0ac23 sw t5,56(ra) +80000280: 03f0ae23 sw t6,60(ra) +80000284: 00001517 auipc a0,0x1 +80000288: d7c50513 addi a0,a0,-644 # 80001000 +8000028c: 00001597 auipc a1,0x1 +80000290: df458593 addi a1,a1,-524 # 80001080 <_end> +80000294: f0100637 lui a2,0xf0100 +80000298: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feeac> + +8000029c : +8000029c: 02b50663 beq a0,a1,800002c8 +800002a0: 00c52683 lw a3,12(a0) +800002a4: 00d62023 sw a3,0(a2) +800002a8: 00852683 lw a3,8(a0) +800002ac: 00d62023 sw a3,0(a2) +800002b0: 00452683 lw a3,4(a0) +800002b4: 00d62023 sw a3,0(a2) +800002b8: 00052683 lw a3,0(a0) +800002bc: 00d62023 sw a3,0(a2) +800002c0: 01050513 addi a0,a0,16 +800002c4: fd9ff06f j 8000029c + +800002c8 : +800002c8: f0100537 lui a0,0xf0100 +800002cc: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feea0> +800002d0: 00052023 sw zero,0(a0) + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff + +80001040 : +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff diff --git a/src/test/resources/asm/I-RF_x0-01.elf.objdump b/src/test/resources/asm/I-RF_x0-01.elf.objdump new file mode 100644 index 0000000..2c7cd9e --- /dev/null +++ b/src/test/resources/asm/I-RF_x0-01.elf.objdump @@ -0,0 +1,135 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-RF_x0-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001f97 auipc t6,0x1 +80000004: 010f8f93 addi t6,t6,16 # 80001010 +80000008: abcde037 lui zero,0xabcde +8000000c: 00100013 li zero,1 +80000010: 7f006013 ori zero,zero,2032 +80000014: 53f07013 andi zero,zero,1343 +80000018: 80304013 xori zero,zero,-2045 +8000001c: 00501013 slli zero,zero,0x5 +80000020: 40205013 srai zero,zero,0x2 +80000024: 00405013 srli zero,zero,0x4 +80000028: 000fa023 sw zero,0(t6) +8000002c: 00001f97 auipc t6,0x1 +80000030: fe8f8f93 addi t6,t6,-24 # 80001014 +80000034: 00100093 li ra,1 +80000038: 7f000113 li sp,2032 +8000003c: 53f00193 li gp,1343 +80000040: 80300213 li tp,-2045 +80000044: 00500293 li t0,5 +80000048: 00200313 li t1,2 +8000004c: 00400393 li t2,4 +80000050: 01800413 li s0,24 +80000054: abcde017 auipc zero,0xabcde +80000058: 00100033 add zero,zero,ra +8000005c: 00206033 or zero,zero,sp +80000060: 00307033 and zero,zero,gp +80000064: 00404033 xor zero,zero,tp +80000068: 00501033 sll zero,zero,t0 +8000006c: 40605033 sra zero,zero,t1 +80000070: 00705033 srl zero,zero,t2 +80000074: 40800033 neg zero,s0 +80000078: 000fa023 sw zero,0(t6) +8000007c: 00001f97 auipc t6,0x1 +80000080: f9cf8f93 addi t6,t6,-100 # 80001018 +80000084: 00100093 li ra,1 +80000088: 00200113 li sp,2 +8000008c: 0020a033 slt zero,ra,sp +80000090: 000fa023 sw zero,0(t6) +80000094: 0020b033 sltu zero,ra,sp +80000098: 000fa223 sw zero,4(t6) +8000009c: 0020a013 slti zero,ra,2 +800000a0: 000fa423 sw zero,8(t6) +800000a4: 0020b013 sltiu zero,ra,2 +800000a8: 000fa623 sw zero,12(t6) +800000ac: 00001f97 auipc t6,0x1 +800000b0: f7cf8f93 addi t6,t6,-132 # 80001028 +800000b4: 0040006f j 800000b8 <_start+0xb8> +800000b8: 000fa023 sw zero,0(t6) +800000bc: 00000097 auipc ra,0x0 +800000c0: 00c08093 addi ra,ra,12 # 800000c8 <_start+0xc8> +800000c4: 00008067 ret +800000c8: 000fa223 sw zero,4(t6) +800000cc: 00001097 auipc ra,0x1 +800000d0: f3408093 addi ra,ra,-204 # 80001000 +800000d4: 00001f97 auipc t6,0x1 +800000d8: f5cf8f93 addi t6,t6,-164 # 80001030 +800000dc: 0000a003 lw zero,0(ra) +800000e0: 000fa023 sw zero,0(t6) +800000e4: 00009003 lh zero,0(ra) +800000e8: 000fa223 sw zero,4(t6) +800000ec: 00008003 lb zero,0(ra) +800000f0: 000fa423 sw zero,8(t6) +800000f4: 0000c003 lbu zero,0(ra) +800000f8: 000fa623 sw zero,12(t6) +800000fc: 00001517 auipc a0,0x1 +80000100: f1450513 addi a0,a0,-236 # 80001010 +80000104: 00001597 auipc a1,0x1 +80000108: f3c58593 addi a1,a1,-196 # 80001040 <_end> +8000010c: f0100637 lui a2,0xf0100 +80000110: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feeec> + +80000114 : +80000114: 02b50663 beq a0,a1,80000140 +80000118: 00c52683 lw a3,12(a0) +8000011c: 00d62023 sw a3,0(a2) +80000120: 00852683 lw a3,8(a0) +80000124: 00d62023 sw a3,0(a2) +80000128: 00452683 lw a3,4(a0) +8000012c: 00d62023 sw a3,0(a2) +80000130: 00052683 lw a3,0(a0) +80000134: 00d62023 sw a3,0(a2) +80000138: 01050513 addi a0,a0,16 +8000013c: fd9ff06f j 80000114 + +80000140 : +80000140: f0100537 lui a0,0xf0100 +80000144: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feee0> +80000148: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 42524e4f fnmadd.d ft8,ft4,ft5,fs0,rmm + ... + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff diff --git a/src/test/resources/asm/I-SB-01.elf.objdump b/src/test/resources/asm/I-SB-01.elf.objdump new file mode 100644 index 0000000..4a710d9 --- /dev/null +++ b/src/test/resources/asm/I-SB-01.elf.objdump @@ -0,0 +1,225 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SB-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 01008093 addi ra,ra,16 # 80001010 +80000008: aaaacfb7 lui t6,0xaaaac +8000000c: bbbf8f93 addi t6,t6,-1093 # aaaabbbb <_end+0x2aaaab6b> +80000010: 01f0a023 sw t6,0(ra) +80000014: 11f1f137 lui sp,0x11f1f +80000018: 22210113 addi sp,sp,546 # 11f1f222 <_start-0x6e0e0dde> +8000001c: 00208023 sb sp,0(ra) +80000020: 00001297 auipc t0,0x1 +80000024: ff528293 addi t0,t0,-11 # 80001015 +80000028: fe02afa3 sw zero,-1(t0) +8000002c: f3334cb7 lui s9,0xf3334 +80000030: 4f4c8c93 addi s9,s9,1268 # f33344f4 <_end+0x733334a4> +80000034: ff928fa3 sb s9,-1(t0) +80000038: 00001417 auipc s0,0x1 +8000003c: fdf40413 addi s0,s0,-33 # 80001017 +80000040: 000420a3 sw zero,1(s0) +80000044: 55f5ffb7 lui t6,0x55f5f +80000048: 666f8f93 addi t6,t6,1638 # 55f5f666 <_start-0x2a0a099a> +8000004c: 01f400a3 sb t6,1(s0) +80000050: 00001597 auipc a1,0x1 +80000054: 7cc58593 addi a1,a1,1996 # 8000181c <_end+0x7cc> +80000058: 8005a023 sw zero,-2048(a1) +8000005c: f7779637 lui a2,0xf7779 +80000060: 8f860613 addi a2,a2,-1800 # f77788f8 <_end+0x777778a8> +80000064: 80c58023 sb a2,-2048(a1) +80000068: 00000717 auipc a4,0x0 +8000006c: 7b970713 addi a4,a4,1977 # 80000821 +80000070: 7e072fa3 sw zero,2047(a4) +80000074: 990917b7 lui a5,0x99091 +80000078: aaa78793 addi a5,a5,-1366 # 99090aaa <_end+0x1908fa5a> +8000007c: 7ef70fa3 sb a5,2047(a4) +80000080: 00001897 auipc a7,0x1 +80000084: fa888893 addi a7,a7,-88 # 80001028 +80000088: 11111937 lui s2,0x11111 +8000008c: 10c90913 addi s2,s2,268 # 1111110c <_start-0x6eeeeef4> +80000090: 222229b7 lui s3,0x22222 +80000094: 2cc98993 addi s3,s3,716 # 222222cc <_start-0x5ddddd34> +80000098: 33333a37 lui s4,0x33333 +8000009c: 3bba0a13 addi s4,s4,955 # 333333bb <_start-0x4ccccc45> +800000a0: 44444ab7 lui s5,0x44444 +800000a4: 40ba8a93 addi s5,s5,1035 # 4444440b <_start-0x3bbbbbf5> +800000a8: 55555b37 lui s6,0x55555 +800000ac: 5eeb0b13 addi s6,s6,1518 # 555555ee <_start-0x2aaaaa12> +800000b0: 66666bb7 lui s7,0x66666 +800000b4: 60eb8b93 addi s7,s7,1550 # 6666660e <_start-0x199999f2> +800000b8: 77777c37 lui s8,0x77777 +800000bc: 70dc0c13 addi s8,s8,1805 # 7777770d <_start-0x88888f3> +800000c0: 88889cb7 lui s9,0x88889 +800000c4: 8ddc8c93 addi s9,s9,-1827 # 888888dd <_end+0x888788d> +800000c8: 9999ad37 lui s10,0x9999a +800000cc: 9f0d0d13 addi s10,s10,-1552 # 999999f0 <_end+0x199989a0> +800000d0: aaaabdb7 lui s11,0xaaaab +800000d4: a00d8d93 addi s11,s11,-1536 # aaaaaa00 <_end+0x2aaa99b0> +800000d8: bbbbce37 lui t3,0xbbbbc +800000dc: bffe0e13 addi t3,t3,-1025 # bbbbbbff <_end+0x3bbbabaf> +800000e0: ccccdeb7 lui t4,0xccccd +800000e4: c0fe8e93 addi t4,t4,-1009 # cccccc0f <_end+0x4cccbbbf> +800000e8: ff288e23 sb s2,-4(a7) +800000ec: ff388ea3 sb s3,-3(a7) +800000f0: ff488f23 sb s4,-2(a7) +800000f4: ff588fa3 sb s5,-1(a7) +800000f8: 01688023 sb s6,0(a7) +800000fc: 017880a3 sb s7,1(a7) +80000100: 01888123 sb s8,2(a7) +80000104: 019881a3 sb s9,3(a7) +80000108: 01a88223 sb s10,4(a7) +8000010c: 01b882a3 sb s11,5(a7) +80000110: 01c88323 sb t3,6(a7) +80000114: 01d883a3 sb t4,7(a7) +80000118: 00001b17 auipc s6,0x1 +8000011c: f18b0b13 addi s6,s6,-232 # 80001030 +80000120: 876540b7 lui ra,0x87654 +80000124: 32108093 addi ra,ra,801 # 87654321 <_end+0x76532d1> +80000128: 001b2023 sw ra,0(s6) +8000012c: 12345037 lui zero,0x12345 +80000130: 67800013 li zero,1656 +80000134: 000b0023 sb zero,0(s6) +80000138: 00001a97 auipc s5,0x1 +8000013c: ec8a8a93 addi s5,s5,-312 # 80001000 +80000140: 000aa083 lw ra,0(s5) +80000144: 0000a023 sw zero,0(ra) +80000148: 112239b7 lui s3,0x11223 +8000014c: 34498993 addi s3,s3,836 # 11223344 <_start-0x6eddccbc> +80000150: 000aab83 lw s7,0(s5) +80000154: 013b8023 sb s3,0(s7) +80000158: 00001b97 auipc s7,0x1 +8000015c: eacb8b93 addi s7,s7,-340 # 80001004 +80000160: 00001c17 auipc s8,0x1 +80000164: ed8c0c13 addi s8,s8,-296 # 80001038 +80000168: 000c2023 sw zero,0(s8) +8000016c: 000bac83 lw s9,0(s7) +80000170: 019c0023 sb s9,0(s8) +80000174: 00001d17 auipc s10,0x1 +80000178: ec8d0d13 addi s10,s10,-312 # 8000103c +8000017c: 000d2023 sw zero,0(s10) +80000180: 76543cb7 lui s9,0x76543 +80000184: 210c8c93 addi s9,s9,528 # 76543210 <_start-0x9abcdf0> +80000188: 019d0023 sb s9,0(s10) +8000018c: 00000c93 li s9,0 +80000190: 00001e17 auipc t3,0x1 +80000194: eb0e0e13 addi t3,t3,-336 # 80001040 +80000198: 000e2023 sw zero,0(t3) +8000019c: 89abddb7 lui s11,0x89abd +800001a0: defd8d93 addi s11,s11,-529 # 89abcdef <_end+0x9abbd9f> +800001a4: 01be0023 sb s11,0(t3) +800001a8: ffce0e13 addi t3,t3,-4 +800001ac: 00001e97 auipc t4,0x1 +800001b0: e98e8e93 addi t4,t4,-360 # 80001044 +800001b4: 000ea023 sw zero,0(t4) +800001b8: 000ea223 sw zero,4(t4) +800001bc: 14726db7 lui s11,0x14726 +800001c0: 836d8d93 addi s11,s11,-1994 # 14725836 <_start-0x6b8da7ca> +800001c4: 01be8023 sb s11,0(t4) +800001c8: 000eaf03 lw t5,0(t4) +800001cc: 01ee8223 sb t5,4(t4) +800001d0: 00001097 auipc ra,0x1 +800001d4: e7c08093 addi ra,ra,-388 # 8000104c +800001d8: 0000a023 sw zero,0(ra) +800001dc: 96385137 lui sp,0x96385 +800001e0: 20110113 addi sp,sp,513 # 96385201 <_end+0x163841b1> +800001e4: 258151b7 lui gp,0x25815 +800001e8: 96318193 addi gp,gp,-1693 # 25814963 <_start-0x5a7eb69d> +800001ec: 00208023 sb sp,0(ra) +800001f0: 00308023 sb gp,0(ra) +800001f4: 00001517 auipc a0,0x1 +800001f8: e1c50513 addi a0,a0,-484 # 80001010 +800001fc: 00001597 auipc a1,0x1 +80000200: e5458593 addi a1,a1,-428 # 80001050 <_end> +80000204: f0100637 lui a2,0xf0100 +80000208: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feedc> + +8000020c : +8000020c: 02b50663 beq a0,a1,80000238 +80000210: 00c52683 lw a3,12(a0) +80000214: 00d62023 sw a3,0(a2) +80000218: 00852683 lw a3,8(a0) +8000021c: 00d62023 sw a3,0(a2) +80000220: 00452683 lw a3,4(a0) +80000224: 00d62023 sw a3,0(a2) +80000228: 00052683 lw a3,0(a0) +8000022c: 00d62023 sw a3,0(a2) +80000230: 01050513 addi a0,a0,16 +80000234: fd9ff06f j 8000020c + +80000238 : +80000238: f0100537 lui a0,0xf0100 +8000023c: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feed0> +80000240: 00052023 sw zero,0(a0) + +Disassembly of section .data: + +80001000 : +80001000: 1034 addi a3,sp,40 +80001002: 8000 0x8000 + +80001004 : +80001004: def0 sw a2,124(a3) +80001006: 9abc 0x9abc + ... + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff + +8000101c : +8000101c: ffff 0xffff +8000101e: ffff 0xffff + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff + +80001034 : +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff + +80001040 : +80001040: ffff 0xffff +80001042: ffff 0xffff + +80001044 : +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff + +8000104c : +8000104c: ffff 0xffff +8000104e: ffff 0xffff diff --git a/src/test/resources/asm/I-SH-01.elf.objdump b/src/test/resources/asm/I-SH-01.elf.objdump new file mode 100644 index 0000000..9edde9b --- /dev/null +++ b/src/test/resources/asm/I-SH-01.elf.objdump @@ -0,0 +1,208 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SH-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 01008093 addi ra,ra,16 # 80001010 +80000008: aaaacfb7 lui t6,0xaaaac +8000000c: bbbf8f93 addi t6,t6,-1093 # aaaabbbb <_end+0x2aaaab6b> +80000010: 01f0a023 sw t6,0(ra) +80000014: 11f1f137 lui sp,0x11f1f +80000018: 22210113 addi sp,sp,546 # 11f1f222 <_start-0x6e0e0dde> +8000001c: 00209023 sh sp,0(ra) +80000020: 00001297 auipc t0,0x1 +80000024: ff528293 addi t0,t0,-11 # 80001015 +80000028: fe02afa3 sw zero,-1(t0) +8000002c: f3334cb7 lui s9,0xf3334 +80000030: 4f4c8c93 addi s9,s9,1268 # f33344f4 <_end+0x733334a4> +80000034: ff929fa3 sh s9,-1(t0) +80000038: 00001417 auipc s0,0x1 +8000003c: fdf40413 addi s0,s0,-33 # 80001017 +80000040: 000420a3 sw zero,1(s0) +80000044: 55f5ffb7 lui t6,0x55f5f +80000048: 666f8f93 addi t6,t6,1638 # 55f5f666 <_start-0x2a0a099a> +8000004c: 01f410a3 sh t6,1(s0) +80000050: 00001597 auipc a1,0x1 +80000054: 7cc58593 addi a1,a1,1996 # 8000181c <_end+0x7cc> +80000058: 8005a023 sw zero,-2048(a1) +8000005c: f7779637 lui a2,0xf7779 +80000060: 8f860613 addi a2,a2,-1800 # f77788f8 <_end+0x777778a8> +80000064: 80c59023 sh a2,-2048(a1) +80000068: 00000717 auipc a4,0x0 +8000006c: 7b970713 addi a4,a4,1977 # 80000821 +80000070: 7e072fa3 sw zero,2047(a4) +80000074: 990917b7 lui a5,0x99091 +80000078: aaa78793 addi a5,a5,-1366 # 99090aaa <_end+0x1908fa5a> +8000007c: 7ef71fa3 sh a5,2047(a4) +80000080: 00001897 auipc a7,0x1 +80000084: fa888893 addi a7,a7,-88 # 80001028 +80000088: 1111d937 lui s2,0x1111d +8000008c: c0c90913 addi s2,s2,-1012 # 1111cc0c <_start-0x6eee33f4> +80000090: 222219b7 lui s3,0x22221 +80000094: bbb98993 addi s3,s3,-1093 # 22220bbb <_start-0x5dddf445> +80000098: 33331a37 lui s4,0x33331 +8000009c: eeea0a13 addi s4,s4,-274 # 33330eee <_start-0x4cccf112> +800000a0: 4444eab7 lui s5,0x4444e +800000a4: d0da8a93 addi s5,s5,-755 # 4444dd0d <_start-0x3bbb22f3> +800000a8: 77770b37 lui s6,0x77770 +800000ac: 0f0b0b13 addi s6,s6,240 # 777700f0 <_start-0x888ff10> +800000b0: 66661bb7 lui s7,0x66661 +800000b4: fffb8b93 addi s7,s7,-1 # 66660fff <_start-0x1999f001> +800000b8: ff289e23 sh s2,-4(a7) +800000bc: ff389f23 sh s3,-2(a7) +800000c0: 01489023 sh s4,0(a7) +800000c4: 01589123 sh s5,2(a7) +800000c8: 01689223 sh s6,4(a7) +800000cc: 01789323 sh s7,6(a7) +800000d0: 00001b17 auipc s6,0x1 +800000d4: f60b0b13 addi s6,s6,-160 # 80001030 +800000d8: 876540b7 lui ra,0x87654 +800000dc: 32108093 addi ra,ra,801 # 87654321 <_end+0x76532d1> +800000e0: 001b2023 sw ra,0(s6) +800000e4: 12345037 lui zero,0x12345 +800000e8: 67800013 li zero,1656 +800000ec: 000b1023 sh zero,0(s6) +800000f0: 00001a97 auipc s5,0x1 +800000f4: f10a8a93 addi s5,s5,-240 # 80001000 +800000f8: 000aa083 lw ra,0(s5) +800000fc: 0000a023 sw zero,0(ra) +80000100: 112239b7 lui s3,0x11223 +80000104: 34498993 addi s3,s3,836 # 11223344 <_start-0x6eddccbc> +80000108: 000aab83 lw s7,0(s5) +8000010c: 013b9023 sh s3,0(s7) +80000110: 00001b97 auipc s7,0x1 +80000114: ef4b8b93 addi s7,s7,-268 # 80001004 +80000118: 00001c17 auipc s8,0x1 +8000011c: f20c0c13 addi s8,s8,-224 # 80001038 +80000120: 000c2023 sw zero,0(s8) +80000124: 000bac83 lw s9,0(s7) +80000128: 019c1023 sh s9,0(s8) +8000012c: 00001d17 auipc s10,0x1 +80000130: f10d0d13 addi s10,s10,-240 # 8000103c +80000134: 000d2023 sw zero,0(s10) +80000138: 76543cb7 lui s9,0x76543 +8000013c: 210c8c93 addi s9,s9,528 # 76543210 <_start-0x9abcdf0> +80000140: 019d1023 sh s9,0(s10) +80000144: 00000c93 li s9,0 +80000148: 00001e17 auipc t3,0x1 +8000014c: ef8e0e13 addi t3,t3,-264 # 80001040 +80000150: 000e2023 sw zero,0(t3) +80000154: 89abddb7 lui s11,0x89abd +80000158: defd8d93 addi s11,s11,-529 # 89abcdef <_end+0x9abbd9f> +8000015c: 01be1023 sh s11,0(t3) +80000160: ffce0e13 addi t3,t3,-4 +80000164: 00001e97 auipc t4,0x1 +80000168: ee0e8e93 addi t4,t4,-288 # 80001044 +8000016c: 000ea023 sw zero,0(t4) +80000170: 000ea223 sw zero,4(t4) +80000174: 14726db7 lui s11,0x14726 +80000178: 836d8d93 addi s11,s11,-1994 # 14725836 <_start-0x6b8da7ca> +8000017c: 01be9023 sh s11,0(t4) +80000180: 000eaf03 lw t5,0(t4) +80000184: 01ee9223 sh t5,4(t4) +80000188: 00001097 auipc ra,0x1 +8000018c: ec408093 addi ra,ra,-316 # 8000104c +80000190: 0000a023 sw zero,0(ra) +80000194: 96385137 lui sp,0x96385 +80000198: 20110113 addi sp,sp,513 # 96385201 <_end+0x163841b1> +8000019c: 258151b7 lui gp,0x25815 +800001a0: 96318193 addi gp,gp,-1693 # 25814963 <_start-0x5a7eb69d> +800001a4: 00209023 sh sp,0(ra) +800001a8: 00309023 sh gp,0(ra) +800001ac: 00001517 auipc a0,0x1 +800001b0: e6450513 addi a0,a0,-412 # 80001010 +800001b4: 00001597 auipc a1,0x1 +800001b8: e9c58593 addi a1,a1,-356 # 80001050 <_end> +800001bc: f0100637 lui a2,0xf0100 +800001c0: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feedc> + +800001c4 : +800001c4: 02b50663 beq a0,a1,800001f0 +800001c8: 00c52683 lw a3,12(a0) +800001cc: 00d62023 sw a3,0(a2) +800001d0: 00852683 lw a3,8(a0) +800001d4: 00d62023 sw a3,0(a2) +800001d8: 00452683 lw a3,4(a0) +800001dc: 00d62023 sw a3,0(a2) +800001e0: 00052683 lw a3,0(a0) +800001e4: 00d62023 sw a3,0(a2) +800001e8: 01050513 addi a0,a0,16 +800001ec: fd9ff06f j 800001c4 + +800001f0 : +800001f0: f0100537 lui a0,0xf0100 +800001f4: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feed0> +800001f8: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 1034 addi a3,sp,40 +80001002: 8000 0x8000 + +80001004 : +80001004: def0 sw a2,124(a3) +80001006: 9abc 0x9abc + ... + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff + +8000101c : +8000101c: ffff 0xffff +8000101e: ffff 0xffff + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff + +80001034 : +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff + +80001040 : +80001040: ffff 0xffff +80001042: ffff 0xffff + +80001044 : +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff + +8000104c : +8000104c: ffff 0xffff +8000104e: ffff 0xffff diff --git a/src/test/resources/asm/I-SLL-01.elf.objdump b/src/test/resources/asm/I-SLL-01.elf.objdump new file mode 100644 index 0000000..a17b69c --- /dev/null +++ b/src/test/resources/asm/I-SLL-01.elf.objdump @@ -0,0 +1,340 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SLL-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00100213 li tp,1 +80000018: 00f00293 li t0,15 +8000001c: 01f00313 li t1,31 +80000020: 00000393 li t2,0 +80000024: 01000413 li s0,16 +80000028: 00419233 sll tp,gp,tp +8000002c: 005192b3 sll t0,gp,t0 +80000030: 00619333 sll t1,gp,t1 +80000034: 007193b3 sll t2,gp,t2 +80000038: 00819433 sll s0,gp,s0 +8000003c: 00312023 sw gp,0(sp) +80000040: 00412223 sw tp,4(sp) +80000044: 00512423 sw t0,8(sp) +80000048: 00612623 sw t1,12(sp) +8000004c: 00712823 sw t2,16(sp) +80000050: 00812a23 sw s0,20(sp) +80000054: 00001097 auipc ra,0x1 +80000058: fb008093 addi ra,ra,-80 # 80001004 +8000005c: 00001117 auipc sp,0x1 +80000060: fec10113 addi sp,sp,-20 # 80001048 +80000064: 0000a403 lw s0,0(ra) +80000068: 00100493 li s1,1 +8000006c: 00f00513 li a0,15 +80000070: 01f00593 li a1,31 +80000074: 00000613 li a2,0 +80000078: 01000693 li a3,16 +8000007c: 009414b3 sll s1,s0,s1 +80000080: 00a41533 sll a0,s0,a0 +80000084: 00b415b3 sll a1,s0,a1 +80000088: 00c41633 sll a2,s0,a2 +8000008c: 00d416b3 sll a3,s0,a3 +80000090: 00812023 sw s0,0(sp) +80000094: 00912223 sw s1,4(sp) +80000098: 00a12423 sw a0,8(sp) +8000009c: 00b12623 sw a1,12(sp) +800000a0: 00c12823 sw a2,16(sp) +800000a4: 00d12a23 sw a3,20(sp) +800000a8: 00001097 auipc ra,0x1 +800000ac: f6008093 addi ra,ra,-160 # 80001008 +800000b0: 00001117 auipc sp,0x1 +800000b4: fb010113 addi sp,sp,-80 # 80001060 +800000b8: 0000a683 lw a3,0(ra) +800000bc: 00100713 li a4,1 +800000c0: 00f00793 li a5,15 +800000c4: 01f00813 li a6,31 +800000c8: 00000893 li a7,0 +800000cc: 01000913 li s2,16 +800000d0: 00e69733 sll a4,a3,a4 +800000d4: 00f697b3 sll a5,a3,a5 +800000d8: 01069833 sll a6,a3,a6 +800000dc: 011698b3 sll a7,a3,a7 +800000e0: 01269933 sll s2,a3,s2 +800000e4: 00d12023 sw a3,0(sp) +800000e8: 00e12223 sw a4,4(sp) +800000ec: 00f12423 sw a5,8(sp) +800000f0: 01012623 sw a6,12(sp) +800000f4: 01112823 sw a7,16(sp) +800000f8: 01212a23 sw s2,20(sp) +800000fc: 00001617 auipc a2,0x1 +80000100: f1060613 addi a2,a2,-240 # 8000100c +80000104: 00001697 auipc a3,0x1 +80000108: f7468693 addi a3,a3,-140 # 80001078 +8000010c: 00062903 lw s2,0(a2) +80000110: 00100993 li s3,1 +80000114: 00f00a13 li s4,15 +80000118: 01f00a93 li s5,31 +8000011c: 00000b13 li s6,0 +80000120: 01000b93 li s7,16 +80000124: 013919b3 sll s3,s2,s3 +80000128: 01491a33 sll s4,s2,s4 +8000012c: 01591ab3 sll s5,s2,s5 +80000130: 01691b33 sll s6,s2,s6 +80000134: 01791bb3 sll s7,s2,s7 +80000138: 0126a023 sw s2,0(a3) +8000013c: 0136a223 sw s3,4(a3) +80000140: 0146a423 sw s4,8(a3) +80000144: 0156a623 sw s5,12(a3) +80000148: 0166a823 sw s6,16(a3) +8000014c: 0176aa23 sw s7,20(a3) +80000150: 00001617 auipc a2,0x1 +80000154: ec060613 addi a2,a2,-320 # 80001010 +80000158: 00001697 auipc a3,0x1 +8000015c: f3868693 addi a3,a3,-200 # 80001090 +80000160: 00062b83 lw s7,0(a2) +80000164: 00100c13 li s8,1 +80000168: 00f00c93 li s9,15 +8000016c: 01f00d13 li s10,31 +80000170: 00000d93 li s11,0 +80000174: 01000e13 li t3,16 +80000178: 018b9c33 sll s8,s7,s8 +8000017c: 019b9cb3 sll s9,s7,s9 +80000180: 01ab9d33 sll s10,s7,s10 +80000184: 01bb9db3 sll s11,s7,s11 +80000188: 01cb9e33 sll t3,s7,t3 +8000018c: 0176a023 sw s7,0(a3) +80000190: 0186a223 sw s8,4(a3) +80000194: 0196a423 sw s9,8(a3) +80000198: 01a6a623 sw s10,12(a3) +8000019c: 01b6a823 sw s11,16(a3) +800001a0: 01c6aa23 sw t3,20(a3) +800001a4: 00001c97 auipc s9,0x1 +800001a8: e70c8c93 addi s9,s9,-400 # 80001014 +800001ac: 00001d17 auipc s10,0x1 +800001b0: efcd0d13 addi s10,s10,-260 # 800010a8 +800001b4: 000cae03 lw t3,0(s9) +800001b8: 00100d93 li s11,1 +800001bc: 01be1eb3 sll t4,t3,s11 +800001c0: 01be9f33 sll t5,t4,s11 +800001c4: 01bf1fb3 sll t6,t5,s11 +800001c8: 01bf90b3 sll ra,t6,s11 +800001cc: 01b09133 sll sp,ra,s11 +800001d0: 01b111b3 sll gp,sp,s11 +800001d4: 01cd2023 sw t3,0(s10) +800001d8: 01dd2223 sw t4,4(s10) +800001dc: 01ed2423 sw t5,8(s10) +800001e0: 01fd2623 sw t6,12(s10) +800001e4: 001d2823 sw ra,16(s10) +800001e8: 002d2a23 sw sp,20(s10) +800001ec: 003d2c23 sw gp,24(s10) +800001f0: 00001097 auipc ra,0x1 +800001f4: e2808093 addi ra,ra,-472 # 80001018 +800001f8: 00001117 auipc sp,0x1 +800001fc: ecc10113 addi sp,sp,-308 # 800010c4 +80000200: 0000a283 lw t0,0(ra) +80000204: 00100d93 li s11,1 +80000208: 01b29033 sll zero,t0,s11 +8000020c: 00012023 sw zero,0(sp) +80000210: 00001097 auipc ra,0x1 +80000214: e0c08093 addi ra,ra,-500 # 8000101c +80000218: 00001117 auipc sp,0x1 +8000021c: eb010113 addi sp,sp,-336 # 800010c8 +80000220: 0000a283 lw t0,0(ra) +80000224: 00100d93 li s11,1 +80000228: 01b29033 sll zero,t0,s11 +8000022c: 01b012b3 sll t0,zero,s11 +80000230: 00012023 sw zero,0(sp) +80000234: 00512223 sw t0,4(sp) +80000238: 00001097 auipc ra,0x1 +8000023c: de808093 addi ra,ra,-536 # 80001020 +80000240: 00001117 auipc sp,0x1 +80000244: e9010113 addi sp,sp,-368 # 800010d0 +80000248: 0000a183 lw gp,0(ra) +8000024c: 10000237 lui tp,0x10000 +80000250: fe020213 addi tp,tp,-32 # fffffe0 <_start-0x70000020> +80000254: 100002b7 lui t0,0x10000 +80000258: fe128293 addi t0,t0,-31 # fffffe1 <_start-0x7000001f> +8000025c: 10000337 lui t1,0x10000 +80000260: fef30313 addi t1,t1,-17 # fffffef <_start-0x70000011> +80000264: 100003b7 lui t2,0x10000 +80000268: fff38393 addi t2,t2,-1 # fffffff <_start-0x70000001> +8000026c: 00419233 sll tp,gp,tp +80000270: 005192b3 sll t0,gp,t0 +80000274: 00619333 sll t1,gp,t1 +80000278: 007193b3 sll t2,gp,t2 +8000027c: 00412023 sw tp,0(sp) +80000280: 00512223 sw t0,4(sp) +80000284: 00612423 sw t1,8(sp) +80000288: 00712623 sw t2,12(sp) +8000028c: 00001517 auipc a0,0x1 +80000290: da450513 addi a0,a0,-604 # 80001030 +80000294: 00001597 auipc a1,0x1 +80000298: e4c58593 addi a1,a1,-436 # 800010e0 <_end> +8000029c: f0100637 lui a2,0xf0100 +800002a0: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +800002a4 : +800002a4: 02b50663 beq a0,a1,800002d0 +800002a8: 00c52683 lw a3,12(a0) +800002ac: 00d62023 sw a3,0(a2) +800002b0: 00852683 lw a3,8(a0) +800002b4: 00d62023 sw a3,0(a2) +800002b8: 00452683 lw a3,4(a0) +800002bc: 00d62023 sw a3,0(a2) +800002c0: 00052683 lw a3,0(a0) +800002c4: 00d62023 sw a3,0(a2) +800002c8: 01050513 addi a0,a0,16 +800002cc: fd9ff06f j 800002a4 + +800002d0 : +800002d0: f0100537 lui a0,0xf0100 +800002d4: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +800002d8: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ef10 fsw fa2,24(a4) +80001016: abcd j 80001608 <_end+0x528> + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 4321 li t1,8 +80001022: 8765 srai a4,a4,0x19 + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff + +800010c4 : +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff +800010cc: ffff 0xffff +800010ce: ffff 0xffff + +800010d0 : +800010d0: ffff 0xffff +800010d2: ffff 0xffff +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-SLLI-01.elf.objdump b/src/test/resources/asm/I-SLLI-01.elf.objdump new file mode 100644 index 0000000..6151dfd --- /dev/null +++ b/src/test/resources/asm/I-SLLI-01.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SLLI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00119213 slli tp,gp,0x1 +80000018: 00f19293 slli t0,gp,0xf +8000001c: 01f19313 slli t1,gp,0x1f +80000020: 00019393 slli t2,gp,0x0 +80000024: 01019413 slli s0,gp,0x10 +80000028: 00312023 sw gp,0(sp) +8000002c: 00412223 sw tp,4(sp) +80000030: 00512423 sw t0,8(sp) +80000034: 00612623 sw t1,12(sp) +80000038: 00712823 sw t2,16(sp) +8000003c: 00812a23 sw s0,20(sp) +80000040: 00001097 auipc ra,0x1 +80000044: fc408093 addi ra,ra,-60 # 80001004 +80000048: 00001117 auipc sp,0x1 +8000004c: ff010113 addi sp,sp,-16 # 80001038 +80000050: 0000a403 lw s0,0(ra) +80000054: 00141493 slli s1,s0,0x1 +80000058: 00f41513 slli a0,s0,0xf +8000005c: 01f41593 slli a1,s0,0x1f +80000060: 00041613 slli a2,s0,0x0 +80000064: 01041693 slli a3,s0,0x10 +80000068: 00812023 sw s0,0(sp) +8000006c: 00912223 sw s1,4(sp) +80000070: 00a12423 sw a0,8(sp) +80000074: 00b12623 sw a1,12(sp) +80000078: 00c12823 sw a2,16(sp) +8000007c: 00d12a23 sw a3,20(sp) +80000080: 00001097 auipc ra,0x1 +80000084: f8808093 addi ra,ra,-120 # 80001008 +80000088: 00001117 auipc sp,0x1 +8000008c: fc810113 addi sp,sp,-56 # 80001050 +80000090: 0000a683 lw a3,0(ra) +80000094: 00169713 slli a4,a3,0x1 +80000098: 00f69793 slli a5,a3,0xf +8000009c: 01f69813 slli a6,a3,0x1f +800000a0: 00069893 slli a7,a3,0x0 +800000a4: 01069913 slli s2,a3,0x10 +800000a8: 00d12023 sw a3,0(sp) +800000ac: 00e12223 sw a4,4(sp) +800000b0: 00f12423 sw a5,8(sp) +800000b4: 01012623 sw a6,12(sp) +800000b8: 01112823 sw a7,16(sp) +800000bc: 01212a23 sw s2,20(sp) +800000c0: 00001617 auipc a2,0x1 +800000c4: f4c60613 addi a2,a2,-180 # 8000100c +800000c8: 00001697 auipc a3,0x1 +800000cc: fa068693 addi a3,a3,-96 # 80001068 +800000d0: 00062903 lw s2,0(a2) +800000d4: 00191993 slli s3,s2,0x1 +800000d8: 00f91a13 slli s4,s2,0xf +800000dc: 01f91a93 slli s5,s2,0x1f +800000e0: 00091b13 slli s6,s2,0x0 +800000e4: 01091b93 slli s7,s2,0x10 +800000e8: 0126a023 sw s2,0(a3) +800000ec: 0136a223 sw s3,4(a3) +800000f0: 0146a423 sw s4,8(a3) +800000f4: 0156a623 sw s5,12(a3) +800000f8: 0166a823 sw s6,16(a3) +800000fc: 0176aa23 sw s7,20(a3) +80000100: 00001617 auipc a2,0x1 +80000104: f1060613 addi a2,a2,-240 # 80001010 +80000108: 00001697 auipc a3,0x1 +8000010c: f7868693 addi a3,a3,-136 # 80001080 +80000110: 00062b83 lw s7,0(a2) +80000114: 001b9c13 slli s8,s7,0x1 +80000118: 00fb9c93 slli s9,s7,0xf +8000011c: 01fb9d13 slli s10,s7,0x1f +80000120: 000b9d93 slli s11,s7,0x0 +80000124: 010b9e13 slli t3,s7,0x10 +80000128: 0176a023 sw s7,0(a3) +8000012c: 0186a223 sw s8,4(a3) +80000130: 0196a423 sw s9,8(a3) +80000134: 01a6a623 sw s10,12(a3) +80000138: 01b6a823 sw s11,16(a3) +8000013c: 01c6aa23 sw t3,20(a3) +80000140: 00001d17 auipc s10,0x1 +80000144: ed4d0d13 addi s10,s10,-300 # 80001014 +80000148: 00001d97 auipc s11,0x1 +8000014c: f50d8d93 addi s11,s11,-176 # 80001098 +80000150: 000d2e03 lw t3,0(s10) +80000154: 001e1e93 slli t4,t3,0x1 +80000158: 001e9f13 slli t5,t4,0x1 +8000015c: 001f1f93 slli t6,t5,0x1 +80000160: 001f9093 slli ra,t6,0x1 +80000164: 00109113 slli sp,ra,0x1 +80000168: 00111193 slli gp,sp,0x1 +8000016c: 01cda023 sw t3,0(s11) +80000170: 01dda223 sw t4,4(s11) +80000174: 01eda423 sw t5,8(s11) +80000178: 01fda623 sw t6,12(s11) +8000017c: 001da823 sw ra,16(s11) +80000180: 002daa23 sw sp,20(s11) +80000184: 003dac23 sw gp,24(s11) +80000188: 00001097 auipc ra,0x1 +8000018c: e9008093 addi ra,ra,-368 # 80001018 +80000190: 00001117 auipc sp,0x1 +80000194: f2410113 addi sp,sp,-220 # 800010b4 +80000198: 0000a283 lw t0,0(ra) +8000019c: 00129013 slli zero,t0,0x1 +800001a0: 00012023 sw zero,0(sp) +800001a4: 00001097 auipc ra,0x1 +800001a8: e7808093 addi ra,ra,-392 # 8000101c +800001ac: 00001117 auipc sp,0x1 +800001b0: f0c10113 addi sp,sp,-244 # 800010b8 +800001b4: 0000a283 lw t0,0(ra) +800001b8: 00129013 slli zero,t0,0x1 +800001bc: 00101293 slli t0,zero,0x1 +800001c0: 00012023 sw zero,0(sp) +800001c4: 00512223 sw t0,4(sp) +800001c8: 00001517 auipc a0,0x1 +800001cc: e5850513 addi a0,a0,-424 # 80001020 +800001d0: 00001597 auipc a1,0x1 +800001d4: ef058593 addi a1,a1,-272 # 800010c0 <_end> +800001d8: f0100637 lui a2,0xf0100 +800001dc: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee6c> + +800001e0 : +800001e0: 02b50663 beq a0,a1,8000020c +800001e4: 00c52683 lw a3,12(a0) +800001e8: 00d62023 sw a3,0(a2) +800001ec: 00852683 lw a3,8(a0) +800001f0: 00d62023 sw a3,0(a2) +800001f4: 00452683 lw a3,4(a0) +800001f8: 00d62023 sw a3,0(a2) +800001fc: 00052683 lw a3,0(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 01050513 addi a0,a0,16 +80000208: fd9ff06f j 800001e0 + +8000020c : +8000020c: f0100537 lui a0,0xf0100 +80000210: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee60> +80000214: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ef10 fsw fa2,24(a4) +80001016: abcd j 80001608 <_end+0x548> + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff + +80001068 : +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff + +80001098 : +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff + +800010b8 : +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff diff --git a/src/test/resources/asm/I-SLT-01.elf.objdump b/src/test/resources/asm/I-SLT-01.elf.objdump new file mode 100644 index 0000000..b5d2b59 --- /dev/null +++ b/src/test/resources/asm/I-SLT-01.elf.objdump @@ -0,0 +1,332 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SLT-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00100213 li tp,1 +80000018: 800002b7 lui t0,0x80000 +8000001c: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffef1f> +80000020: fff00313 li t1,-1 +80000024: 00000393 li t2,0 +80000028: 80000437 lui s0,0x80000 +8000002c: 0041a233 slt tp,gp,tp +80000030: 0051a2b3 slt t0,gp,t0 +80000034: 0061a333 slt t1,gp,t1 +80000038: 0071a3b3 slt t2,gp,t2 +8000003c: 0081a433 slt s0,gp,s0 +80000040: 00312023 sw gp,0(sp) +80000044: 00412223 sw tp,4(sp) +80000048: 00512423 sw t0,8(sp) +8000004c: 00612623 sw t1,12(sp) +80000050: 00712823 sw t2,16(sp) +80000054: 00812a23 sw s0,20(sp) +80000058: 00001097 auipc ra,0x1 +8000005c: fac08093 addi ra,ra,-84 # 80001004 +80000060: 00001117 auipc sp,0x1 +80000064: fd810113 addi sp,sp,-40 # 80001038 +80000068: 0000a403 lw s0,0(ra) +8000006c: 00100493 li s1,1 +80000070: 80000537 lui a0,0x80000 +80000074: fff50513 addi a0,a0,-1 # 7fffffff <_end+0xffffef1f> +80000078: fff00593 li a1,-1 +8000007c: 00000613 li a2,0 +80000080: 800006b7 lui a3,0x80000 +80000084: 009424b3 slt s1,s0,s1 +80000088: 00a42533 slt a0,s0,a0 +8000008c: 00b425b3 slt a1,s0,a1 +80000090: 00c42633 slt a2,s0,a2 +80000094: 00d426b3 slt a3,s0,a3 +80000098: 00812023 sw s0,0(sp) +8000009c: 00912223 sw s1,4(sp) +800000a0: 00a12423 sw a0,8(sp) +800000a4: 00b12623 sw a1,12(sp) +800000a8: 00c12823 sw a2,16(sp) +800000ac: 00d12a23 sw a3,20(sp) +800000b0: 00001097 auipc ra,0x1 +800000b4: f5808093 addi ra,ra,-168 # 80001008 +800000b8: 00001117 auipc sp,0x1 +800000bc: f9810113 addi sp,sp,-104 # 80001050 +800000c0: 0000a683 lw a3,0(ra) +800000c4: 00100713 li a4,1 +800000c8: 800007b7 lui a5,0x80000 +800000cc: fff78793 addi a5,a5,-1 # 7fffffff <_end+0xffffef1f> +800000d0: fff00813 li a6,-1 +800000d4: 00000893 li a7,0 +800000d8: 80000937 lui s2,0x80000 +800000dc: 00e6a733 slt a4,a3,a4 +800000e0: 00f6a7b3 slt a5,a3,a5 +800000e4: 0106a833 slt a6,a3,a6 +800000e8: 0116a8b3 slt a7,a3,a7 +800000ec: 0126a933 slt s2,a3,s2 +800000f0: 00d12023 sw a3,0(sp) +800000f4: 00e12223 sw a4,4(sp) +800000f8: 00f12423 sw a5,8(sp) +800000fc: 01012623 sw a6,12(sp) +80000100: 01112823 sw a7,16(sp) +80000104: 01212a23 sw s2,20(sp) +80000108: 00001097 auipc ra,0x1 +8000010c: f0408093 addi ra,ra,-252 # 8000100c +80000110: 00001117 auipc sp,0x1 +80000114: f5810113 addi sp,sp,-168 # 80001068 +80000118: 0000a903 lw s2,0(ra) +8000011c: 00100993 li s3,1 +80000120: 80000a37 lui s4,0x80000 +80000124: fffa0a13 addi s4,s4,-1 # 7fffffff <_end+0xffffef1f> +80000128: fff00a93 li s5,-1 +8000012c: 00000b13 li s6,0 +80000130: 80000bb7 lui s7,0x80000 +80000134: 013929b3 slt s3,s2,s3 +80000138: 01492a33 slt s4,s2,s4 +8000013c: 01592ab3 slt s5,s2,s5 +80000140: 01692b33 slt s6,s2,s6 +80000144: 01792bb3 slt s7,s2,s7 +80000148: 01212023 sw s2,0(sp) +8000014c: 01312223 sw s3,4(sp) +80000150: 01412423 sw s4,8(sp) +80000154: 01512623 sw s5,12(sp) +80000158: 01612823 sw s6,16(sp) +8000015c: 01712a23 sw s7,20(sp) +80000160: 00001097 auipc ra,0x1 +80000164: eb008093 addi ra,ra,-336 # 80001010 +80000168: 00001117 auipc sp,0x1 +8000016c: f1810113 addi sp,sp,-232 # 80001080 +80000170: 0000ab83 lw s7,0(ra) +80000174: 00100c13 li s8,1 +80000178: 80000cb7 lui s9,0x80000 +8000017c: fffc8c93 addi s9,s9,-1 # 7fffffff <_end+0xffffef1f> +80000180: fff00d13 li s10,-1 +80000184: 00000d93 li s11,0 +80000188: 80000e37 lui t3,0x80000 +8000018c: 018bac33 slt s8,s7,s8 +80000190: 019bacb3 slt s9,s7,s9 +80000194: 01abad33 slt s10,s7,s10 +80000198: 01bbadb3 slt s11,s7,s11 +8000019c: 01cbae33 slt t3,s7,t3 +800001a0: 01712023 sw s7,0(sp) +800001a4: 01812223 sw s8,4(sp) +800001a8: 01912423 sw s9,8(sp) +800001ac: 01a12623 sw s10,12(sp) +800001b0: 01b12823 sw s11,16(sp) +800001b4: 01c12a23 sw t3,20(sp) +800001b8: 00001d17 auipc s10,0x1 +800001bc: e5cd0d13 addi s10,s10,-420 # 80001014 +800001c0: 00001d97 auipc s11,0x1 +800001c4: ed8d8d93 addi s11,s11,-296 # 80001098 +800001c8: 000d2083 lw ra,0(s10) +800001cc: 00100113 li sp,1 +800001d0: 0020a033 slt zero,ra,sp +800001d4: 000da023 sw zero,0(s11) +800001d8: 001da223 sw ra,4(s11) +800001dc: 002da423 sw sp,8(s11) +800001e0: 00001f97 auipc t6,0x1 +800001e4: ec4f8f93 addi t6,t6,-316 # 800010a4 +800001e8: 00100093 li ra,1 +800001ec: 7ff00113 li sp,2047 +800001f0: fff00193 li gp,-1 +800001f4: 00000213 li tp,0 +800001f8: 80000293 li t0,-2048 +800001fc: 00102333 sgtz t1,ra +80000200: 002023b3 sgtz t2,sp +80000204: 00302433 sgtz s0,gp +80000208: 004024b3 sgtz s1,tp +8000020c: 00502533 sgtz a0,t0 +80000210: 0000a5b3 sltz a1,ra +80000214: 00012633 sltz a2,sp +80000218: 0001a6b3 sltz a3,gp +8000021c: 00022733 sltz a4,tp +80000220: 0002a7b3 sltz a5,t0 +80000224: 006fa023 sw t1,0(t6) +80000228: 007fa223 sw t2,4(t6) +8000022c: 008fa423 sw s0,8(t6) +80000230: 009fa623 sw s1,12(t6) +80000234: 00afa823 sw a0,16(t6) +80000238: 00bfaa23 sw a1,20(t6) +8000023c: 00cfac23 sw a2,24(t6) +80000240: 00dfae23 sw a3,28(t6) +80000244: 02efa023 sw a4,32(t6) +80000248: 02ffa223 sw a5,36(t6) +8000024c: 00001f97 auipc t6,0x1 +80000250: e80f8f93 addi t6,t6,-384 # 800010cc +80000254: 00100193 li gp,1 +80000258: 003020b3 sgtz ra,gp +8000025c: 0030a133 slt sp,ra,gp +80000260: 00312e33 slt t3,sp,gp +80000264: 003e2eb3 slt t4,t3,gp +80000268: 003eaf33 slt t5,t4,gp +8000026c: 001fa023 sw ra,0(t6) +80000270: 002fa223 sw sp,4(t6) +80000274: 01cfa423 sw t3,8(t6) +80000278: 01dfa623 sw t4,12(t6) +8000027c: 01efa823 sw t5,16(t6) +80000280: 00001517 auipc a0,0x1 +80000284: da050513 addi a0,a0,-608 # 80001020 +80000288: 00001597 auipc a1,0x1 +8000028c: e5858593 addi a1,a1,-424 # 800010e0 <_end> +80000290: f0100637 lui a2,0xf0100 +80000294: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +80000298 : +80000298: 02b50663 beq a0,a1,800002c4 +8000029c: 00c52683 lw a3,12(a0) +800002a0: 00d62023 sw a3,0(a2) +800002a4: 00852683 lw a3,8(a0) +800002a8: 00d62023 sw a3,0(a2) +800002ac: 00452683 lw a3,4(a0) +800002b0: 00d62023 sw a3,0(a2) +800002b4: 00052683 lw a3,0(a0) +800002b8: 00d62023 sw a3,0(a2) +800002bc: 01050513 addi a0,a0,16 +800002c0: fd9ff06f j 80000298 + +800002c4 : +800002c4: f0100537 lui a0,0xf0100 +800002c8: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +800002cc: 00052023 sw zero,0(a0) +800002d0: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff + +80001068 : +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff + +80001098 : +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff + +800010a4 : +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff +800010c8: ffff 0xffff +800010ca: ffff 0xffff + +800010cc : +800010cc: ffff 0xffff +800010ce: ffff 0xffff +800010d0: ffff 0xffff +800010d2: ffff 0xffff +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-SLTI-01.elf.objdump b/src/test/resources/asm/I-SLTI-01.elf.objdump new file mode 100644 index 0000000..433f418 --- /dev/null +++ b/src/test/resources/asm/I-SLTI-01.elf.objdump @@ -0,0 +1,277 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SLTI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 0011a213 slti tp,gp,1 +80000018: 7ff1a293 slti t0,gp,2047 +8000001c: fff1a313 slti t1,gp,-1 +80000020: 0001a393 slti t2,gp,0 +80000024: 8001a413 slti s0,gp,-2048 +80000028: 00312023 sw gp,0(sp) +8000002c: 00412223 sw tp,4(sp) +80000030: 00512423 sw t0,8(sp) +80000034: 00612623 sw t1,12(sp) +80000038: 00712823 sw t2,16(sp) +8000003c: 00812a23 sw s0,20(sp) +80000040: 00001097 auipc ra,0x1 +80000044: fc408093 addi ra,ra,-60 # 80001004 +80000048: 00001117 auipc sp,0x1 +8000004c: ff010113 addi sp,sp,-16 # 80001038 +80000050: 0000a403 lw s0,0(ra) +80000054: 00142493 slti s1,s0,1 +80000058: 7ff42513 slti a0,s0,2047 +8000005c: fff42593 slti a1,s0,-1 +80000060: 00042613 slti a2,s0,0 +80000064: 80042693 slti a3,s0,-2048 +80000068: 00812023 sw s0,0(sp) +8000006c: 00912223 sw s1,4(sp) +80000070: 00a12423 sw a0,8(sp) +80000074: 00b12623 sw a1,12(sp) +80000078: 00c12823 sw a2,16(sp) +8000007c: 00d12a23 sw a3,20(sp) +80000080: 00001097 auipc ra,0x1 +80000084: f8808093 addi ra,ra,-120 # 80001008 +80000088: 00001117 auipc sp,0x1 +8000008c: fc810113 addi sp,sp,-56 # 80001050 +80000090: 0000a683 lw a3,0(ra) +80000094: 0016a713 slti a4,a3,1 +80000098: 7ff6a793 slti a5,a3,2047 +8000009c: fff6a813 slti a6,a3,-1 +800000a0: 0006a893 slti a7,a3,0 +800000a4: 8006a913 slti s2,a3,-2048 +800000a8: 00d12023 sw a3,0(sp) +800000ac: 00e12223 sw a4,4(sp) +800000b0: 00f12423 sw a5,8(sp) +800000b4: 01012623 sw a6,12(sp) +800000b8: 01112823 sw a7,16(sp) +800000bc: 01212a23 sw s2,20(sp) +800000c0: 00001097 auipc ra,0x1 +800000c4: f4c08093 addi ra,ra,-180 # 8000100c +800000c8: 00001117 auipc sp,0x1 +800000cc: fa010113 addi sp,sp,-96 # 80001068 +800000d0: 0000a903 lw s2,0(ra) +800000d4: 00192993 slti s3,s2,1 +800000d8: 7ff92a13 slti s4,s2,2047 +800000dc: fff92a93 slti s5,s2,-1 +800000e0: 00092b13 slti s6,s2,0 +800000e4: 80092b93 slti s7,s2,-2048 +800000e8: 01212023 sw s2,0(sp) +800000ec: 01312223 sw s3,4(sp) +800000f0: 01412423 sw s4,8(sp) +800000f4: 01512623 sw s5,12(sp) +800000f8: 01612823 sw s6,16(sp) +800000fc: 01712a23 sw s7,20(sp) +80000100: 00001097 auipc ra,0x1 +80000104: f1008093 addi ra,ra,-240 # 80001010 +80000108: 00001117 auipc sp,0x1 +8000010c: f7810113 addi sp,sp,-136 # 80001080 +80000110: 0000ab83 lw s7,0(ra) +80000114: 001bac13 slti s8,s7,1 +80000118: 7ffbac93 slti s9,s7,2047 +8000011c: fffbad13 slti s10,s7,-1 +80000120: 000bad93 slti s11,s7,0 +80000124: 800bae13 slti t3,s7,-2048 +80000128: 01712023 sw s7,0(sp) +8000012c: 01812223 sw s8,4(sp) +80000130: 01912423 sw s9,8(sp) +80000134: 01a12623 sw s10,12(sp) +80000138: 01b12823 sw s11,16(sp) +8000013c: 01c12a23 sw t3,20(sp) +80000140: 00001d17 auipc s10,0x1 +80000144: ed4d0d13 addi s10,s10,-300 # 80001014 +80000148: 00001d97 auipc s11,0x1 +8000014c: f50d8d93 addi s11,s11,-176 # 80001098 +80000150: 000d2083 lw ra,0(s10) +80000154: 0010a013 slti zero,ra,1 +80000158: 001da023 sw ra,0(s11) +8000015c: 000da223 sw zero,4(s11) +80000160: 00001f97 auipc t6,0x1 +80000164: f40f8f93 addi t6,t6,-192 # 800010a0 +80000168: 00102093 slti ra,zero,1 +8000016c: 7ff02113 slti sp,zero,2047 +80000170: fff02193 slti gp,zero,-1 +80000174: 00002213 slti tp,zero,0 +80000178: 80002293 slti t0,zero,-2048 +8000017c: 000fa023 sw zero,0(t6) +80000180: 001fa223 sw ra,4(t6) +80000184: 002fa423 sw sp,8(t6) +80000188: 003fa623 sw gp,12(t6) +8000018c: 004fa823 sw tp,16(t6) +80000190: 005faa23 sw t0,20(t6) +80000194: 00001f97 auipc t6,0x1 +80000198: f24f8f93 addi t6,t6,-220 # 800010b8 +8000019c: 00102093 slti ra,zero,1 +800001a0: 0010a113 slti sp,ra,1 +800001a4: 00112e13 slti t3,sp,1 +800001a8: 001e2e93 slti t4,t3,1 +800001ac: 001eaf13 slti t5,t4,1 +800001b0: 000fa023 sw zero,0(t6) +800001b4: 001fa223 sw ra,4(t6) +800001b8: 002fa423 sw sp,8(t6) +800001bc: 01cfa623 sw t3,12(t6) +800001c0: 01dfa823 sw t4,16(t6) +800001c4: 01efaa23 sw t5,20(t6) +800001c8: 00001517 auipc a0,0x1 +800001cc: e5850513 addi a0,a0,-424 # 80001020 +800001d0: 00001597 auipc a1,0x1 +800001d4: f0058593 addi a1,a1,-256 # 800010d0 <_end> +800001d8: f0100637 lui a2,0xf0100 +800001dc: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001e0 : +800001e0: 02b50663 beq a0,a1,8000020c +800001e4: 00c52683 lw a3,12(a0) +800001e8: 00d62023 sw a3,0(a2) +800001ec: 00852683 lw a3,8(a0) +800001f0: 00d62023 sw a3,0(a2) +800001f4: 00452683 lw a3,4(a0) +800001f8: 00d62023 sw a3,0(a2) +800001fc: 00052683 lw a3,0(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 01050513 addi a0,a0,16 +80000208: fd9ff06f j 800001e0 + +8000020c : +8000020c: f0100537 lui a0,0xf0100 +80000210: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +80000214: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff + +80001068 : +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff + +80001098 : +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff + +800010b8 : +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff +800010c8: ffff 0xffff +800010ca: ffff 0xffff +800010cc: ffff 0xffff +800010ce: ffff 0xffff diff --git a/src/test/resources/asm/I-SLTIU-01.elf.objdump b/src/test/resources/asm/I-SLTIU-01.elf.objdump new file mode 100644 index 0000000..32fc6f7 --- /dev/null +++ b/src/test/resources/asm/I-SLTIU-01.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SLTIU-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 0011b213 seqz tp,gp +80000018: 7ff1b293 sltiu t0,gp,2047 +8000001c: fff1b313 sltiu t1,gp,-1 +80000020: 0001b393 sltiu t2,gp,0 +80000024: 8001b413 sltiu s0,gp,-2048 +80000028: 00312023 sw gp,0(sp) +8000002c: 00412223 sw tp,4(sp) +80000030: 00512423 sw t0,8(sp) +80000034: 00612623 sw t1,12(sp) +80000038: 00712823 sw t2,16(sp) +8000003c: 00812a23 sw s0,20(sp) +80000040: 00001097 auipc ra,0x1 +80000044: fc408093 addi ra,ra,-60 # 80001004 +80000048: 00001117 auipc sp,0x1 +8000004c: ff010113 addi sp,sp,-16 # 80001038 +80000050: 0000a403 lw s0,0(ra) +80000054: 00143493 seqz s1,s0 +80000058: 7ff43513 sltiu a0,s0,2047 +8000005c: fff43593 sltiu a1,s0,-1 +80000060: 00043613 sltiu a2,s0,0 +80000064: 80043693 sltiu a3,s0,-2048 +80000068: 00812023 sw s0,0(sp) +8000006c: 00912223 sw s1,4(sp) +80000070: 00a12423 sw a0,8(sp) +80000074: 00b12623 sw a1,12(sp) +80000078: 00c12823 sw a2,16(sp) +8000007c: 00d12a23 sw a3,20(sp) +80000080: 00001097 auipc ra,0x1 +80000084: f8808093 addi ra,ra,-120 # 80001008 +80000088: 00001117 auipc sp,0x1 +8000008c: fc810113 addi sp,sp,-56 # 80001050 +80000090: 0000a683 lw a3,0(ra) +80000094: 0016b713 seqz a4,a3 +80000098: 7ff6b793 sltiu a5,a3,2047 +8000009c: fff6b813 sltiu a6,a3,-1 +800000a0: 0006b893 sltiu a7,a3,0 +800000a4: 8006b913 sltiu s2,a3,-2048 +800000a8: 00d12023 sw a3,0(sp) +800000ac: 00e12223 sw a4,4(sp) +800000b0: 00f12423 sw a5,8(sp) +800000b4: 01012623 sw a6,12(sp) +800000b8: 01112823 sw a7,16(sp) +800000bc: 01212a23 sw s2,20(sp) +800000c0: 00001097 auipc ra,0x1 +800000c4: f4c08093 addi ra,ra,-180 # 8000100c +800000c8: 00001117 auipc sp,0x1 +800000cc: fa010113 addi sp,sp,-96 # 80001068 +800000d0: 0000a903 lw s2,0(ra) +800000d4: 00193993 seqz s3,s2 +800000d8: 7ff93a13 sltiu s4,s2,2047 +800000dc: fff93a93 sltiu s5,s2,-1 +800000e0: 00093b13 sltiu s6,s2,0 +800000e4: 80093b93 sltiu s7,s2,-2048 +800000e8: 01212023 sw s2,0(sp) +800000ec: 01312223 sw s3,4(sp) +800000f0: 01412423 sw s4,8(sp) +800000f4: 01512623 sw s5,12(sp) +800000f8: 01612823 sw s6,16(sp) +800000fc: 01712a23 sw s7,20(sp) +80000100: 00001097 auipc ra,0x1 +80000104: f1008093 addi ra,ra,-240 # 80001010 +80000108: 00001117 auipc sp,0x1 +8000010c: f7810113 addi sp,sp,-136 # 80001080 +80000110: 0000ab83 lw s7,0(ra) +80000114: 001bbc13 seqz s8,s7 +80000118: 7ffbbc93 sltiu s9,s7,2047 +8000011c: fffbbd13 sltiu s10,s7,-1 +80000120: 000bbd93 sltiu s11,s7,0 +80000124: 800bbe13 sltiu t3,s7,-2048 +80000128: 01712023 sw s7,0(sp) +8000012c: 01812223 sw s8,4(sp) +80000130: 01912423 sw s9,8(sp) +80000134: 01a12623 sw s10,12(sp) +80000138: 01b12823 sw s11,16(sp) +8000013c: 01c12a23 sw t3,20(sp) +80000140: 00001d17 auipc s10,0x1 +80000144: ed4d0d13 addi s10,s10,-300 # 80001014 +80000148: 00001d97 auipc s11,0x1 +8000014c: f50d8d93 addi s11,s11,-176 # 80001098 +80000150: 000d2083 lw ra,0(s10) +80000154: fff0b013 sltiu zero,ra,-1 +80000158: 001da023 sw ra,0(s11) +8000015c: 000da223 sw zero,4(s11) +80000160: 00001f97 auipc t6,0x1 +80000164: f40f8f93 addi t6,t6,-192 # 800010a0 +80000168: 00103093 seqz ra,zero +8000016c: 7ff03113 sltiu sp,zero,2047 +80000170: fff03193 sltiu gp,zero,-1 +80000174: 00003213 sltiu tp,zero,0 +80000178: 80003293 sltiu t0,zero,-2048 +8000017c: 000fa023 sw zero,0(t6) +80000180: 001fa223 sw ra,4(t6) +80000184: 002fa423 sw sp,8(t6) +80000188: 003fa623 sw gp,12(t6) +8000018c: 004fa823 sw tp,16(t6) +80000190: 005faa23 sw t0,20(t6) +80000194: 00001f97 auipc t6,0x1 +80000198: f24f8f93 addi t6,t6,-220 # 800010b8 +8000019c: 00103093 seqz ra,zero +800001a0: 0010b113 seqz sp,ra +800001a4: 00113e13 seqz t3,sp +800001a8: 001e3e93 seqz t4,t3 +800001ac: 001ebf13 seqz t5,t4 +800001b0: 000fa023 sw zero,0(t6) +800001b4: 001fa223 sw ra,4(t6) +800001b8: 002fa423 sw sp,8(t6) +800001bc: 01cfa623 sw t3,12(t6) +800001c0: 01dfa823 sw t4,16(t6) +800001c4: 01efaa23 sw t5,20(t6) +800001c8: 00001517 auipc a0,0x1 +800001cc: e5850513 addi a0,a0,-424 # 80001020 +800001d0: 00001597 auipc a1,0x1 +800001d4: f0058593 addi a1,a1,-256 # 800010d0 <_end> +800001d8: f0100637 lui a2,0xf0100 +800001dc: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001e0 : +800001e0: 02b50663 beq a0,a1,8000020c +800001e4: 00c52683 lw a3,12(a0) +800001e8: 00d62023 sw a3,0(a2) +800001ec: 00852683 lw a3,8(a0) +800001f0: 00d62023 sw a3,0(a2) +800001f4: 00452683 lw a3,4(a0) +800001f8: 00d62023 sw a3,0(a2) +800001fc: 00052683 lw a3,0(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 01050513 addi a0,a0,16 +80000208: fd9ff06f j 800001e0 + +8000020c : +8000020c: f0100537 lui a0,0xf0100 +80000210: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +80000214: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: 0001 nop + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff + +80001068 : +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff + +80001098 : +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff + +800010b8 : +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff +800010c8: ffff 0xffff +800010ca: ffff 0xffff +800010cc: ffff 0xffff +800010ce: ffff 0xffff diff --git a/src/test/resources/asm/I-SLTU-01.elf.objdump b/src/test/resources/asm/I-SLTU-01.elf.objdump new file mode 100644 index 0000000..0362f0b --- /dev/null +++ b/src/test/resources/asm/I-SLTU-01.elf.objdump @@ -0,0 +1,331 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SLTU-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00100213 li tp,1 +80000018: 800002b7 lui t0,0x80000 +8000001c: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffef1f> +80000020: fff00313 li t1,-1 +80000024: 00000393 li t2,0 +80000028: 80000437 lui s0,0x80000 +8000002c: 0041b233 sltu tp,gp,tp +80000030: 0051b2b3 sltu t0,gp,t0 +80000034: 0061b333 sltu t1,gp,t1 +80000038: 0071b3b3 sltu t2,gp,t2 +8000003c: 0081b433 sltu s0,gp,s0 +80000040: 00312023 sw gp,0(sp) +80000044: 00412223 sw tp,4(sp) +80000048: 00512423 sw t0,8(sp) +8000004c: 00612623 sw t1,12(sp) +80000050: 00712823 sw t2,16(sp) +80000054: 00812a23 sw s0,20(sp) +80000058: 00001097 auipc ra,0x1 +8000005c: fac08093 addi ra,ra,-84 # 80001004 +80000060: 00001117 auipc sp,0x1 +80000064: fd810113 addi sp,sp,-40 # 80001038 +80000068: 0000a403 lw s0,0(ra) +8000006c: 00100493 li s1,1 +80000070: 80000537 lui a0,0x80000 +80000074: fff50513 addi a0,a0,-1 # 7fffffff <_end+0xffffef1f> +80000078: fff00593 li a1,-1 +8000007c: 00000613 li a2,0 +80000080: 800006b7 lui a3,0x80000 +80000084: 009434b3 sltu s1,s0,s1 +80000088: 00a43533 sltu a0,s0,a0 +8000008c: 00b435b3 sltu a1,s0,a1 +80000090: 00c43633 sltu a2,s0,a2 +80000094: 00d436b3 sltu a3,s0,a3 +80000098: 00812023 sw s0,0(sp) +8000009c: 00912223 sw s1,4(sp) +800000a0: 00a12423 sw a0,8(sp) +800000a4: 00b12623 sw a1,12(sp) +800000a8: 00c12823 sw a2,16(sp) +800000ac: 00d12a23 sw a3,20(sp) +800000b0: 00001097 auipc ra,0x1 +800000b4: f5808093 addi ra,ra,-168 # 80001008 +800000b8: 00001117 auipc sp,0x1 +800000bc: f9810113 addi sp,sp,-104 # 80001050 +800000c0: 0000a683 lw a3,0(ra) +800000c4: 00100713 li a4,1 +800000c8: 800007b7 lui a5,0x80000 +800000cc: fff78793 addi a5,a5,-1 # 7fffffff <_end+0xffffef1f> +800000d0: fff00813 li a6,-1 +800000d4: 00000893 li a7,0 +800000d8: 80000937 lui s2,0x80000 +800000dc: 00e6b733 sltu a4,a3,a4 +800000e0: 00f6b7b3 sltu a5,a3,a5 +800000e4: 0106b833 sltu a6,a3,a6 +800000e8: 0116b8b3 sltu a7,a3,a7 +800000ec: 0126b933 sltu s2,a3,s2 +800000f0: 00d12023 sw a3,0(sp) +800000f4: 00e12223 sw a4,4(sp) +800000f8: 00f12423 sw a5,8(sp) +800000fc: 01012623 sw a6,12(sp) +80000100: 01112823 sw a7,16(sp) +80000104: 01212a23 sw s2,20(sp) +80000108: 00001097 auipc ra,0x1 +8000010c: f0408093 addi ra,ra,-252 # 8000100c +80000110: 00001117 auipc sp,0x1 +80000114: f5810113 addi sp,sp,-168 # 80001068 +80000118: 0000a903 lw s2,0(ra) +8000011c: 00100993 li s3,1 +80000120: 80000a37 lui s4,0x80000 +80000124: fffa0a13 addi s4,s4,-1 # 7fffffff <_end+0xffffef1f> +80000128: fff00a93 li s5,-1 +8000012c: 00000b13 li s6,0 +80000130: 80000bb7 lui s7,0x80000 +80000134: 013939b3 sltu s3,s2,s3 +80000138: 01493a33 sltu s4,s2,s4 +8000013c: 01593ab3 sltu s5,s2,s5 +80000140: 01693b33 sltu s6,s2,s6 +80000144: 01793bb3 sltu s7,s2,s7 +80000148: 01212023 sw s2,0(sp) +8000014c: 01312223 sw s3,4(sp) +80000150: 01412423 sw s4,8(sp) +80000154: 01512623 sw s5,12(sp) +80000158: 01612823 sw s6,16(sp) +8000015c: 01712a23 sw s7,20(sp) +80000160: 00001097 auipc ra,0x1 +80000164: eb008093 addi ra,ra,-336 # 80001010 +80000168: 00001117 auipc sp,0x1 +8000016c: f1810113 addi sp,sp,-232 # 80001080 +80000170: 0000ab83 lw s7,0(ra) +80000174: 00100c13 li s8,1 +80000178: 80000cb7 lui s9,0x80000 +8000017c: fffc8c93 addi s9,s9,-1 # 7fffffff <_end+0xffffef1f> +80000180: fff00d13 li s10,-1 +80000184: 00000d93 li s11,0 +80000188: 80000e37 lui t3,0x80000 +8000018c: 018bbc33 sltu s8,s7,s8 +80000190: 019bbcb3 sltu s9,s7,s9 +80000194: 01abbd33 sltu s10,s7,s10 +80000198: 01bbbdb3 sltu s11,s7,s11 +8000019c: 01cbbe33 sltu t3,s7,t3 +800001a0: 01712023 sw s7,0(sp) +800001a4: 01812223 sw s8,4(sp) +800001a8: 01912423 sw s9,8(sp) +800001ac: 01a12623 sw s10,12(sp) +800001b0: 01b12823 sw s11,16(sp) +800001b4: 01c12a23 sw t3,20(sp) +800001b8: 00001d17 auipc s10,0x1 +800001bc: e5cd0d13 addi s10,s10,-420 # 80001014 +800001c0: 00001d97 auipc s11,0x1 +800001c4: ed8d8d93 addi s11,s11,-296 # 80001098 +800001c8: 000d2083 lw ra,0(s10) +800001cc: fff00113 li sp,-1 +800001d0: 0020b033 sltu zero,ra,sp +800001d4: 000da023 sw zero,0(s11) +800001d8: 001da223 sw ra,4(s11) +800001dc: 002da423 sw sp,8(s11) +800001e0: 00001f97 auipc t6,0x1 +800001e4: ec4f8f93 addi t6,t6,-316 # 800010a4 +800001e8: 00100093 li ra,1 +800001ec: 7ff00113 li sp,2047 +800001f0: fff00193 li gp,-1 +800001f4: 00000213 li tp,0 +800001f8: 80000293 li t0,-2048 +800001fc: 00103333 snez t1,ra +80000200: 002033b3 snez t2,sp +80000204: 00303433 snez s0,gp +80000208: 004034b3 snez s1,tp +8000020c: 00503533 snez a0,t0 +80000210: 0000b5b3 sltu a1,ra,zero +80000214: 00013633 sltu a2,sp,zero +80000218: 0001b6b3 sltu a3,gp,zero +8000021c: 00023733 sltu a4,tp,zero +80000220: 0002b7b3 sltu a5,t0,zero +80000224: 006fa023 sw t1,0(t6) +80000228: 007fa223 sw t2,4(t6) +8000022c: 008fa423 sw s0,8(t6) +80000230: 009fa623 sw s1,12(t6) +80000234: 00afa823 sw a0,16(t6) +80000238: 00bfaa23 sw a1,20(t6) +8000023c: 00cfac23 sw a2,24(t6) +80000240: 00dfae23 sw a3,28(t6) +80000244: 02efa023 sw a4,32(t6) +80000248: 02ffa223 sw a5,36(t6) +8000024c: 00001f97 auipc t6,0x1 +80000250: e80f8f93 addi t6,t6,-384 # 800010cc +80000254: 00100193 li gp,1 +80000258: 003030b3 snez ra,gp +8000025c: 0030b133 sltu sp,ra,gp +80000260: 00313e33 sltu t3,sp,gp +80000264: 003e3eb3 sltu t4,t3,gp +80000268: 003ebf33 sltu t5,t4,gp +8000026c: 001fa023 sw ra,0(t6) +80000270: 002fa223 sw sp,4(t6) +80000274: 01cfa423 sw t3,8(t6) +80000278: 01dfa623 sw t4,12(t6) +8000027c: 01efa823 sw t5,16(t6) +80000280: 00001517 auipc a0,0x1 +80000284: da050513 addi a0,a0,-608 # 80001020 +80000288: 00001597 auipc a1,0x1 +8000028c: e5858593 addi a1,a1,-424 # 800010e0 <_end> +80000290: f0100637 lui a2,0xf0100 +80000294: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +80000298 : +80000298: 02b50663 beq a0,a1,800002c4 +8000029c: 00c52683 lw a3,12(a0) +800002a0: 00d62023 sw a3,0(a2) +800002a4: 00852683 lw a3,8(a0) +800002a8: 00d62023 sw a3,0(a2) +800002ac: 00452683 lw a3,4(a0) +800002b0: 00d62023 sw a3,0(a2) +800002b4: 00052683 lw a3,0(a0) +800002b8: 00d62023 sw a3,0(a2) +800002bc: 01050513 addi a0,a0,16 +800002c0: fd9ff06f j 80000298 + +800002c4 : +800002c4: f0100537 lui a0,0xf0100 +800002c8: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +800002cc: 00052023 sw zero,0(a0) +800002d0: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: 0001 nop + ... + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff + +80001068 : +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff + +80001098 : +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff + +800010a4 : +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff +800010c8: ffff 0xffff +800010ca: ffff 0xffff + +800010cc : +800010cc: ffff 0xffff +800010ce: ffff 0xffff +800010d0: ffff 0xffff +800010d2: ffff 0xffff +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-SRA-01.elf.objdump b/src/test/resources/asm/I-SRA-01.elf.objdump new file mode 100644 index 0000000..906c3ae --- /dev/null +++ b/src/test/resources/asm/I-SRA-01.elf.objdump @@ -0,0 +1,340 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SRA-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00100213 li tp,1 +80000018: 00f00293 li t0,15 +8000001c: 01f00313 li t1,31 +80000020: 00000393 li t2,0 +80000024: 01000413 li s0,16 +80000028: 4041d233 sra tp,gp,tp +8000002c: 4051d2b3 sra t0,gp,t0 +80000030: 4061d333 sra t1,gp,t1 +80000034: 4071d3b3 sra t2,gp,t2 +80000038: 4081d433 sra s0,gp,s0 +8000003c: 00312023 sw gp,0(sp) +80000040: 00412223 sw tp,4(sp) +80000044: 00512423 sw t0,8(sp) +80000048: 00612623 sw t1,12(sp) +8000004c: 00712823 sw t2,16(sp) +80000050: 00812a23 sw s0,20(sp) +80000054: 00001097 auipc ra,0x1 +80000058: fb008093 addi ra,ra,-80 # 80001004 +8000005c: 00001117 auipc sp,0x1 +80000060: fec10113 addi sp,sp,-20 # 80001048 +80000064: 0000a403 lw s0,0(ra) +80000068: 00100493 li s1,1 +8000006c: 00f00513 li a0,15 +80000070: 01f00593 li a1,31 +80000074: 00000613 li a2,0 +80000078: 01000693 li a3,16 +8000007c: 409454b3 sra s1,s0,s1 +80000080: 40a45533 sra a0,s0,a0 +80000084: 40b455b3 sra a1,s0,a1 +80000088: 40c45633 sra a2,s0,a2 +8000008c: 40d456b3 sra a3,s0,a3 +80000090: 00812023 sw s0,0(sp) +80000094: 00912223 sw s1,4(sp) +80000098: 00a12423 sw a0,8(sp) +8000009c: 00b12623 sw a1,12(sp) +800000a0: 00c12823 sw a2,16(sp) +800000a4: 00d12a23 sw a3,20(sp) +800000a8: 00001097 auipc ra,0x1 +800000ac: f6008093 addi ra,ra,-160 # 80001008 +800000b0: 00001117 auipc sp,0x1 +800000b4: fb010113 addi sp,sp,-80 # 80001060 +800000b8: 0000a683 lw a3,0(ra) +800000bc: 00100713 li a4,1 +800000c0: 00f00793 li a5,15 +800000c4: 01f00813 li a6,31 +800000c8: 00000893 li a7,0 +800000cc: 01000913 li s2,16 +800000d0: 40e6d733 sra a4,a3,a4 +800000d4: 40f6d7b3 sra a5,a3,a5 +800000d8: 4106d833 sra a6,a3,a6 +800000dc: 4116d8b3 sra a7,a3,a7 +800000e0: 4126d933 sra s2,a3,s2 +800000e4: 00d12023 sw a3,0(sp) +800000e8: 00e12223 sw a4,4(sp) +800000ec: 00f12423 sw a5,8(sp) +800000f0: 01012623 sw a6,12(sp) +800000f4: 01112823 sw a7,16(sp) +800000f8: 01212a23 sw s2,20(sp) +800000fc: 00001617 auipc a2,0x1 +80000100: f1060613 addi a2,a2,-240 # 8000100c +80000104: 00001697 auipc a3,0x1 +80000108: f7468693 addi a3,a3,-140 # 80001078 +8000010c: 00062903 lw s2,0(a2) +80000110: 00100993 li s3,1 +80000114: 00f00a13 li s4,15 +80000118: 01f00a93 li s5,31 +8000011c: 00000b13 li s6,0 +80000120: 01000b93 li s7,16 +80000124: 413959b3 sra s3,s2,s3 +80000128: 41495a33 sra s4,s2,s4 +8000012c: 41595ab3 sra s5,s2,s5 +80000130: 41695b33 sra s6,s2,s6 +80000134: 41795bb3 sra s7,s2,s7 +80000138: 0126a023 sw s2,0(a3) +8000013c: 0136a223 sw s3,4(a3) +80000140: 0146a423 sw s4,8(a3) +80000144: 0156a623 sw s5,12(a3) +80000148: 0166a823 sw s6,16(a3) +8000014c: 0176aa23 sw s7,20(a3) +80000150: 00001617 auipc a2,0x1 +80000154: ec060613 addi a2,a2,-320 # 80001010 +80000158: 00001697 auipc a3,0x1 +8000015c: f3868693 addi a3,a3,-200 # 80001090 +80000160: 00062b83 lw s7,0(a2) +80000164: 00100c13 li s8,1 +80000168: 00f00c93 li s9,15 +8000016c: 01f00d13 li s10,31 +80000170: 00000d93 li s11,0 +80000174: 01000e13 li t3,16 +80000178: 418bdc33 sra s8,s7,s8 +8000017c: 419bdcb3 sra s9,s7,s9 +80000180: 41abdd33 sra s10,s7,s10 +80000184: 41bbddb3 sra s11,s7,s11 +80000188: 41cbde33 sra t3,s7,t3 +8000018c: 0176a023 sw s7,0(a3) +80000190: 0186a223 sw s8,4(a3) +80000194: 0196a423 sw s9,8(a3) +80000198: 01a6a623 sw s10,12(a3) +8000019c: 01b6a823 sw s11,16(a3) +800001a0: 01c6aa23 sw t3,20(a3) +800001a4: 00001c97 auipc s9,0x1 +800001a8: e70c8c93 addi s9,s9,-400 # 80001014 +800001ac: 00001d17 auipc s10,0x1 +800001b0: efcd0d13 addi s10,s10,-260 # 800010a8 +800001b4: 000cae03 lw t3,0(s9) +800001b8: 00100d93 li s11,1 +800001bc: 41be5eb3 sra t4,t3,s11 +800001c0: 41bedf33 sra t5,t4,s11 +800001c4: 41bf5fb3 sra t6,t5,s11 +800001c8: 41bfd0b3 sra ra,t6,s11 +800001cc: 41b0d133 sra sp,ra,s11 +800001d0: 41b151b3 sra gp,sp,s11 +800001d4: 01cd2023 sw t3,0(s10) +800001d8: 01dd2223 sw t4,4(s10) +800001dc: 01ed2423 sw t5,8(s10) +800001e0: 01fd2623 sw t6,12(s10) +800001e4: 001d2823 sw ra,16(s10) +800001e8: 002d2a23 sw sp,20(s10) +800001ec: 003d2c23 sw gp,24(s10) +800001f0: 00001097 auipc ra,0x1 +800001f4: e2808093 addi ra,ra,-472 # 80001018 +800001f8: 00001117 auipc sp,0x1 +800001fc: ecc10113 addi sp,sp,-308 # 800010c4 +80000200: 0000a283 lw t0,0(ra) +80000204: 00100d93 li s11,1 +80000208: 41b2d033 sra zero,t0,s11 +8000020c: 00012023 sw zero,0(sp) +80000210: 00001097 auipc ra,0x1 +80000214: e0c08093 addi ra,ra,-500 # 8000101c +80000218: 00001117 auipc sp,0x1 +8000021c: eb010113 addi sp,sp,-336 # 800010c8 +80000220: 0000a283 lw t0,0(ra) +80000224: 00100d93 li s11,1 +80000228: 41b2d033 sra zero,t0,s11 +8000022c: 41b052b3 sra t0,zero,s11 +80000230: 00012023 sw zero,0(sp) +80000234: 00512223 sw t0,4(sp) +80000238: 00001097 auipc ra,0x1 +8000023c: de808093 addi ra,ra,-536 # 80001020 +80000240: 00001117 auipc sp,0x1 +80000244: e9010113 addi sp,sp,-368 # 800010d0 +80000248: 0000a183 lw gp,0(ra) +8000024c: 10000237 lui tp,0x10000 +80000250: fe020213 addi tp,tp,-32 # fffffe0 <_start-0x70000020> +80000254: 100002b7 lui t0,0x10000 +80000258: fe128293 addi t0,t0,-31 # fffffe1 <_start-0x7000001f> +8000025c: 10000337 lui t1,0x10000 +80000260: fef30313 addi t1,t1,-17 # fffffef <_start-0x70000011> +80000264: 100003b7 lui t2,0x10000 +80000268: fff38393 addi t2,t2,-1 # fffffff <_start-0x70000001> +8000026c: 4041d233 sra tp,gp,tp +80000270: 4051d2b3 sra t0,gp,t0 +80000274: 4061d333 sra t1,gp,t1 +80000278: 4071d3b3 sra t2,gp,t2 +8000027c: 00412023 sw tp,0(sp) +80000280: 00512223 sw t0,4(sp) +80000284: 00612423 sw t1,8(sp) +80000288: 00712623 sw t2,12(sp) +8000028c: 00001517 auipc a0,0x1 +80000290: da450513 addi a0,a0,-604 # 80001030 +80000294: 00001597 auipc a1,0x1 +80000298: e4c58593 addi a1,a1,-436 # 800010e0 <_end> +8000029c: f0100637 lui a2,0xf0100 +800002a0: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +800002a4 : +800002a4: 02b50663 beq a0,a1,800002d0 +800002a8: 00c52683 lw a3,12(a0) +800002ac: 00d62023 sw a3,0(a2) +800002b0: 00852683 lw a3,8(a0) +800002b4: 00d62023 sw a3,0(a2) +800002b8: 00452683 lw a3,4(a0) +800002bc: 00d62023 sw a3,0(a2) +800002c0: 00052683 lw a3,0(a0) +800002c4: 00d62023 sw a3,0(a2) +800002c8: 01050513 addi a0,a0,16 +800002cc: fd9ff06f j 800002a4 + +800002d0 : +800002d0: f0100537 lui a0,0xf0100 +800002d4: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +800002d8: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ef10 fsw fa2,24(a4) +80001016: abcd j 80001608 <_end+0x528> + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 4321 li t1,8 +80001022: 8765 srai a4,a4,0x19 + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff + +800010c4 : +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff +800010cc: ffff 0xffff +800010ce: ffff 0xffff + +800010d0 : +800010d0: ffff 0xffff +800010d2: ffff 0xffff +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-SRAI-01.elf.objdump b/src/test/resources/asm/I-SRAI-01.elf.objdump new file mode 100644 index 0000000..f8f9031 --- /dev/null +++ b/src/test/resources/asm/I-SRAI-01.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SRAI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 4011d213 srai tp,gp,0x1 +80000018: 40f1d293 srai t0,gp,0xf +8000001c: 41f1d313 srai t1,gp,0x1f +80000020: 4001d393 srai t2,gp,0x0 +80000024: 4101d413 srai s0,gp,0x10 +80000028: 00312023 sw gp,0(sp) +8000002c: 00412223 sw tp,4(sp) +80000030: 00512423 sw t0,8(sp) +80000034: 00612623 sw t1,12(sp) +80000038: 00712823 sw t2,16(sp) +8000003c: 00812a23 sw s0,20(sp) +80000040: 00001097 auipc ra,0x1 +80000044: fc408093 addi ra,ra,-60 # 80001004 +80000048: 00001117 auipc sp,0x1 +8000004c: ff010113 addi sp,sp,-16 # 80001038 +80000050: 0000a403 lw s0,0(ra) +80000054: 40145493 srai s1,s0,0x1 +80000058: 40f45513 srai a0,s0,0xf +8000005c: 41f45593 srai a1,s0,0x1f +80000060: 40045613 srai a2,s0,0x0 +80000064: 41045693 srai a3,s0,0x10 +80000068: 00812023 sw s0,0(sp) +8000006c: 00912223 sw s1,4(sp) +80000070: 00a12423 sw a0,8(sp) +80000074: 00b12623 sw a1,12(sp) +80000078: 00c12823 sw a2,16(sp) +8000007c: 00d12a23 sw a3,20(sp) +80000080: 00001097 auipc ra,0x1 +80000084: f8808093 addi ra,ra,-120 # 80001008 +80000088: 00001117 auipc sp,0x1 +8000008c: fc810113 addi sp,sp,-56 # 80001050 +80000090: 0000a683 lw a3,0(ra) +80000094: 4016d713 srai a4,a3,0x1 +80000098: 40f6d793 srai a5,a3,0xf +8000009c: 41f6d813 srai a6,a3,0x1f +800000a0: 4006d893 srai a7,a3,0x0 +800000a4: 4106d913 srai s2,a3,0x10 +800000a8: 00d12023 sw a3,0(sp) +800000ac: 00e12223 sw a4,4(sp) +800000b0: 00f12423 sw a5,8(sp) +800000b4: 01012623 sw a6,12(sp) +800000b8: 01112823 sw a7,16(sp) +800000bc: 01212a23 sw s2,20(sp) +800000c0: 00001617 auipc a2,0x1 +800000c4: f4c60613 addi a2,a2,-180 # 8000100c +800000c8: 00001697 auipc a3,0x1 +800000cc: fa068693 addi a3,a3,-96 # 80001068 +800000d0: 00062903 lw s2,0(a2) +800000d4: 40195993 srai s3,s2,0x1 +800000d8: 40f95a13 srai s4,s2,0xf +800000dc: 41f95a93 srai s5,s2,0x1f +800000e0: 40095b13 srai s6,s2,0x0 +800000e4: 41095b93 srai s7,s2,0x10 +800000e8: 0126a023 sw s2,0(a3) +800000ec: 0136a223 sw s3,4(a3) +800000f0: 0146a423 sw s4,8(a3) +800000f4: 0156a623 sw s5,12(a3) +800000f8: 0166a823 sw s6,16(a3) +800000fc: 0176aa23 sw s7,20(a3) +80000100: 00001617 auipc a2,0x1 +80000104: f1060613 addi a2,a2,-240 # 80001010 +80000108: 00001697 auipc a3,0x1 +8000010c: f7868693 addi a3,a3,-136 # 80001080 +80000110: 00062b83 lw s7,0(a2) +80000114: 401bdc13 srai s8,s7,0x1 +80000118: 40fbdc93 srai s9,s7,0xf +8000011c: 41fbdd13 srai s10,s7,0x1f +80000120: 400bdd93 srai s11,s7,0x0 +80000124: 410bde13 srai t3,s7,0x10 +80000128: 0176a023 sw s7,0(a3) +8000012c: 0186a223 sw s8,4(a3) +80000130: 0196a423 sw s9,8(a3) +80000134: 01a6a623 sw s10,12(a3) +80000138: 01b6a823 sw s11,16(a3) +8000013c: 01c6aa23 sw t3,20(a3) +80000140: 00001d17 auipc s10,0x1 +80000144: ed4d0d13 addi s10,s10,-300 # 80001014 +80000148: 00001d97 auipc s11,0x1 +8000014c: f50d8d93 addi s11,s11,-176 # 80001098 +80000150: 000d2e03 lw t3,0(s10) +80000154: 401e5e93 srai t4,t3,0x1 +80000158: 401edf13 srai t5,t4,0x1 +8000015c: 401f5f93 srai t6,t5,0x1 +80000160: 401fd093 srai ra,t6,0x1 +80000164: 4010d113 srai sp,ra,0x1 +80000168: 40115193 srai gp,sp,0x1 +8000016c: 01cda023 sw t3,0(s11) +80000170: 01dda223 sw t4,4(s11) +80000174: 01eda423 sw t5,8(s11) +80000178: 01fda623 sw t6,12(s11) +8000017c: 001da823 sw ra,16(s11) +80000180: 002daa23 sw sp,20(s11) +80000184: 003dac23 sw gp,24(s11) +80000188: 00001097 auipc ra,0x1 +8000018c: e9008093 addi ra,ra,-368 # 80001018 +80000190: 00001117 auipc sp,0x1 +80000194: f2410113 addi sp,sp,-220 # 800010b4 +80000198: 0000a283 lw t0,0(ra) +8000019c: 4012d013 srai zero,t0,0x1 +800001a0: 00012023 sw zero,0(sp) +800001a4: 00001097 auipc ra,0x1 +800001a8: e7808093 addi ra,ra,-392 # 8000101c +800001ac: 00001117 auipc sp,0x1 +800001b0: f0c10113 addi sp,sp,-244 # 800010b8 +800001b4: 0000a283 lw t0,0(ra) +800001b8: 4012d013 srai zero,t0,0x1 +800001bc: 40105293 srai t0,zero,0x1 +800001c0: 00012023 sw zero,0(sp) +800001c4: 00512223 sw t0,4(sp) +800001c8: 00001517 auipc a0,0x1 +800001cc: e5850513 addi a0,a0,-424 # 80001020 +800001d0: 00001597 auipc a1,0x1 +800001d4: ef058593 addi a1,a1,-272 # 800010c0 <_end> +800001d8: f0100637 lui a2,0xf0100 +800001dc: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee6c> + +800001e0 : +800001e0: 02b50663 beq a0,a1,8000020c +800001e4: 00c52683 lw a3,12(a0) +800001e8: 00d62023 sw a3,0(a2) +800001ec: 00852683 lw a3,8(a0) +800001f0: 00d62023 sw a3,0(a2) +800001f4: 00452683 lw a3,4(a0) +800001f8: 00d62023 sw a3,0(a2) +800001fc: 00052683 lw a3,0(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 01050513 addi a0,a0,16 +80000208: fd9ff06f j 800001e0 + +8000020c : +8000020c: f0100537 lui a0,0xf0100 +80000210: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee60> +80000214: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ef10 fsw fa2,24(a4) +80001016: abcd j 80001608 <_end+0x548> + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff + +80001068 : +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff + +80001098 : +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff + +800010b8 : +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff diff --git a/src/test/resources/asm/I-SRL-01.elf.objdump b/src/test/resources/asm/I-SRL-01.elf.objdump new file mode 100644 index 0000000..6115ebb --- /dev/null +++ b/src/test/resources/asm/I-SRL-01.elf.objdump @@ -0,0 +1,340 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SRL-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00100213 li tp,1 +80000018: 00f00293 li t0,15 +8000001c: 01f00313 li t1,31 +80000020: 00000393 li t2,0 +80000024: 01000413 li s0,16 +80000028: 0041d233 srl tp,gp,tp +8000002c: 0051d2b3 srl t0,gp,t0 +80000030: 0061d333 srl t1,gp,t1 +80000034: 0071d3b3 srl t2,gp,t2 +80000038: 0081d433 srl s0,gp,s0 +8000003c: 00312023 sw gp,0(sp) +80000040: 00412223 sw tp,4(sp) +80000044: 00512423 sw t0,8(sp) +80000048: 00612623 sw t1,12(sp) +8000004c: 00712823 sw t2,16(sp) +80000050: 00812a23 sw s0,20(sp) +80000054: 00001097 auipc ra,0x1 +80000058: fb008093 addi ra,ra,-80 # 80001004 +8000005c: 00001117 auipc sp,0x1 +80000060: fec10113 addi sp,sp,-20 # 80001048 +80000064: 0000a403 lw s0,0(ra) +80000068: 00100493 li s1,1 +8000006c: 00f00513 li a0,15 +80000070: 01f00593 li a1,31 +80000074: 00000613 li a2,0 +80000078: 01000693 li a3,16 +8000007c: 009454b3 srl s1,s0,s1 +80000080: 00a45533 srl a0,s0,a0 +80000084: 00b455b3 srl a1,s0,a1 +80000088: 00c45633 srl a2,s0,a2 +8000008c: 00d456b3 srl a3,s0,a3 +80000090: 00812023 sw s0,0(sp) +80000094: 00912223 sw s1,4(sp) +80000098: 00a12423 sw a0,8(sp) +8000009c: 00b12623 sw a1,12(sp) +800000a0: 00c12823 sw a2,16(sp) +800000a4: 00d12a23 sw a3,20(sp) +800000a8: 00001097 auipc ra,0x1 +800000ac: f6008093 addi ra,ra,-160 # 80001008 +800000b0: 00001117 auipc sp,0x1 +800000b4: fb010113 addi sp,sp,-80 # 80001060 +800000b8: 0000a683 lw a3,0(ra) +800000bc: 00100713 li a4,1 +800000c0: 00f00793 li a5,15 +800000c4: 01f00813 li a6,31 +800000c8: 00000893 li a7,0 +800000cc: 01000913 li s2,16 +800000d0: 00e6d733 srl a4,a3,a4 +800000d4: 00f6d7b3 srl a5,a3,a5 +800000d8: 0106d833 srl a6,a3,a6 +800000dc: 0116d8b3 srl a7,a3,a7 +800000e0: 0126d933 srl s2,a3,s2 +800000e4: 00d12023 sw a3,0(sp) +800000e8: 00e12223 sw a4,4(sp) +800000ec: 00f12423 sw a5,8(sp) +800000f0: 01012623 sw a6,12(sp) +800000f4: 01112823 sw a7,16(sp) +800000f8: 01212a23 sw s2,20(sp) +800000fc: 00001617 auipc a2,0x1 +80000100: f1060613 addi a2,a2,-240 # 8000100c +80000104: 00001697 auipc a3,0x1 +80000108: f7468693 addi a3,a3,-140 # 80001078 +8000010c: 00062903 lw s2,0(a2) +80000110: 00100993 li s3,1 +80000114: 00f00a13 li s4,15 +80000118: 01f00a93 li s5,31 +8000011c: 00000b13 li s6,0 +80000120: 01000b93 li s7,16 +80000124: 013959b3 srl s3,s2,s3 +80000128: 01495a33 srl s4,s2,s4 +8000012c: 01595ab3 srl s5,s2,s5 +80000130: 01695b33 srl s6,s2,s6 +80000134: 01795bb3 srl s7,s2,s7 +80000138: 0126a023 sw s2,0(a3) +8000013c: 0136a223 sw s3,4(a3) +80000140: 0146a423 sw s4,8(a3) +80000144: 0156a623 sw s5,12(a3) +80000148: 0166a823 sw s6,16(a3) +8000014c: 0176aa23 sw s7,20(a3) +80000150: 00001617 auipc a2,0x1 +80000154: ec060613 addi a2,a2,-320 # 80001010 +80000158: 00001697 auipc a3,0x1 +8000015c: f3868693 addi a3,a3,-200 # 80001090 +80000160: 00062b83 lw s7,0(a2) +80000164: 00100c13 li s8,1 +80000168: 00f00c93 li s9,15 +8000016c: 01f00d13 li s10,31 +80000170: 00000d93 li s11,0 +80000174: 01000e13 li t3,16 +80000178: 018bdc33 srl s8,s7,s8 +8000017c: 019bdcb3 srl s9,s7,s9 +80000180: 01abdd33 srl s10,s7,s10 +80000184: 01bbddb3 srl s11,s7,s11 +80000188: 01cbde33 srl t3,s7,t3 +8000018c: 0176a023 sw s7,0(a3) +80000190: 0186a223 sw s8,4(a3) +80000194: 0196a423 sw s9,8(a3) +80000198: 01a6a623 sw s10,12(a3) +8000019c: 01b6a823 sw s11,16(a3) +800001a0: 01c6aa23 sw t3,20(a3) +800001a4: 00001c97 auipc s9,0x1 +800001a8: e70c8c93 addi s9,s9,-400 # 80001014 +800001ac: 00001d17 auipc s10,0x1 +800001b0: efcd0d13 addi s10,s10,-260 # 800010a8 +800001b4: 000cae03 lw t3,0(s9) +800001b8: 00100d93 li s11,1 +800001bc: 01be5eb3 srl t4,t3,s11 +800001c0: 01bedf33 srl t5,t4,s11 +800001c4: 01bf5fb3 srl t6,t5,s11 +800001c8: 01bfd0b3 srl ra,t6,s11 +800001cc: 01b0d133 srl sp,ra,s11 +800001d0: 01b151b3 srl gp,sp,s11 +800001d4: 01cd2023 sw t3,0(s10) +800001d8: 01dd2223 sw t4,4(s10) +800001dc: 01ed2423 sw t5,8(s10) +800001e0: 01fd2623 sw t6,12(s10) +800001e4: 001d2823 sw ra,16(s10) +800001e8: 002d2a23 sw sp,20(s10) +800001ec: 003d2c23 sw gp,24(s10) +800001f0: 00001097 auipc ra,0x1 +800001f4: e2808093 addi ra,ra,-472 # 80001018 +800001f8: 00001117 auipc sp,0x1 +800001fc: ecc10113 addi sp,sp,-308 # 800010c4 +80000200: 0000a283 lw t0,0(ra) +80000204: 00100d93 li s11,1 +80000208: 01b2d033 srl zero,t0,s11 +8000020c: 00012023 sw zero,0(sp) +80000210: 00001097 auipc ra,0x1 +80000214: e0c08093 addi ra,ra,-500 # 8000101c +80000218: 00001117 auipc sp,0x1 +8000021c: eb010113 addi sp,sp,-336 # 800010c8 +80000220: 0000a283 lw t0,0(ra) +80000224: 00100d93 li s11,1 +80000228: 01b2d033 srl zero,t0,s11 +8000022c: 01b052b3 srl t0,zero,s11 +80000230: 00012023 sw zero,0(sp) +80000234: 00512223 sw t0,4(sp) +80000238: 00001097 auipc ra,0x1 +8000023c: de808093 addi ra,ra,-536 # 80001020 +80000240: 00001117 auipc sp,0x1 +80000244: e9010113 addi sp,sp,-368 # 800010d0 +80000248: 0000a183 lw gp,0(ra) +8000024c: 10000237 lui tp,0x10000 +80000250: fe020213 addi tp,tp,-32 # fffffe0 <_start-0x70000020> +80000254: 100002b7 lui t0,0x10000 +80000258: fe128293 addi t0,t0,-31 # fffffe1 <_start-0x7000001f> +8000025c: 10000337 lui t1,0x10000 +80000260: fef30313 addi t1,t1,-17 # fffffef <_start-0x70000011> +80000264: 100003b7 lui t2,0x10000 +80000268: fff38393 addi t2,t2,-1 # fffffff <_start-0x70000001> +8000026c: 0041d233 srl tp,gp,tp +80000270: 0051d2b3 srl t0,gp,t0 +80000274: 0061d333 srl t1,gp,t1 +80000278: 0071d3b3 srl t2,gp,t2 +8000027c: 00412023 sw tp,0(sp) +80000280: 00512223 sw t0,4(sp) +80000284: 00612423 sw t1,8(sp) +80000288: 00712623 sw t2,12(sp) +8000028c: 00001517 auipc a0,0x1 +80000290: da450513 addi a0,a0,-604 # 80001030 +80000294: 00001597 auipc a1,0x1 +80000298: e4c58593 addi a1,a1,-436 # 800010e0 <_end> +8000029c: f0100637 lui a2,0xf0100 +800002a0: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +800002a4 : +800002a4: 02b50663 beq a0,a1,800002d0 +800002a8: 00c52683 lw a3,12(a0) +800002ac: 00d62023 sw a3,0(a2) +800002b0: 00852683 lw a3,8(a0) +800002b4: 00d62023 sw a3,0(a2) +800002b8: 00452683 lw a3,4(a0) +800002bc: 00d62023 sw a3,0(a2) +800002c0: 00052683 lw a3,0(a0) +800002c4: 00d62023 sw a3,0(a2) +800002c8: 01050513 addi a0,a0,16 +800002cc: fd9ff06f j 800002a4 + +800002d0 : +800002d0: f0100537 lui a0,0xf0100 +800002d4: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +800002d8: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ef10 fsw fa2,24(a4) +80001016: abcd j 80001608 <_end+0x528> + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 4321 li t1,8 +80001022: 8765 srai a4,a4,0x19 + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff + +800010c4 : +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff +800010cc: ffff 0xffff +800010ce: ffff 0xffff + +800010d0 : +800010d0: ffff 0xffff +800010d2: ffff 0xffff +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-SRLI-01.elf.objdump b/src/test/resources/asm/I-SRLI-01.elf.objdump new file mode 100644 index 0000000..d277adc --- /dev/null +++ b/src/test/resources/asm/I-SRLI-01.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SRLI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 01810113 addi sp,sp,24 # 80001020 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 0011d213 srli tp,gp,0x1 +80000018: 00f1d293 srli t0,gp,0xf +8000001c: 01f1d313 srli t1,gp,0x1f +80000020: 0001d393 srli t2,gp,0x0 +80000024: 0101d413 srli s0,gp,0x10 +80000028: 00312023 sw gp,0(sp) +8000002c: 00412223 sw tp,4(sp) +80000030: 00512423 sw t0,8(sp) +80000034: 00612623 sw t1,12(sp) +80000038: 00712823 sw t2,16(sp) +8000003c: 00812a23 sw s0,20(sp) +80000040: 00001097 auipc ra,0x1 +80000044: fc408093 addi ra,ra,-60 # 80001004 +80000048: 00001117 auipc sp,0x1 +8000004c: ff010113 addi sp,sp,-16 # 80001038 +80000050: 0000a403 lw s0,0(ra) +80000054: 00145493 srli s1,s0,0x1 +80000058: 00f45513 srli a0,s0,0xf +8000005c: 01f45593 srli a1,s0,0x1f +80000060: 00045613 srli a2,s0,0x0 +80000064: 01045693 srli a3,s0,0x10 +80000068: 00812023 sw s0,0(sp) +8000006c: 00912223 sw s1,4(sp) +80000070: 00a12423 sw a0,8(sp) +80000074: 00b12623 sw a1,12(sp) +80000078: 00c12823 sw a2,16(sp) +8000007c: 00d12a23 sw a3,20(sp) +80000080: 00001097 auipc ra,0x1 +80000084: f8808093 addi ra,ra,-120 # 80001008 +80000088: 00001117 auipc sp,0x1 +8000008c: fc810113 addi sp,sp,-56 # 80001050 +80000090: 0000a683 lw a3,0(ra) +80000094: 0016d713 srli a4,a3,0x1 +80000098: 00f6d793 srli a5,a3,0xf +8000009c: 01f6d813 srli a6,a3,0x1f +800000a0: 0006d893 srli a7,a3,0x0 +800000a4: 0106d913 srli s2,a3,0x10 +800000a8: 00d12023 sw a3,0(sp) +800000ac: 00e12223 sw a4,4(sp) +800000b0: 00f12423 sw a5,8(sp) +800000b4: 01012623 sw a6,12(sp) +800000b8: 01112823 sw a7,16(sp) +800000bc: 01212a23 sw s2,20(sp) +800000c0: 00001617 auipc a2,0x1 +800000c4: f4c60613 addi a2,a2,-180 # 8000100c +800000c8: 00001697 auipc a3,0x1 +800000cc: fa068693 addi a3,a3,-96 # 80001068 +800000d0: 00062903 lw s2,0(a2) +800000d4: 00195993 srli s3,s2,0x1 +800000d8: 00f95a13 srli s4,s2,0xf +800000dc: 01f95a93 srli s5,s2,0x1f +800000e0: 00095b13 srli s6,s2,0x0 +800000e4: 01095b93 srli s7,s2,0x10 +800000e8: 0126a023 sw s2,0(a3) +800000ec: 0136a223 sw s3,4(a3) +800000f0: 0146a423 sw s4,8(a3) +800000f4: 0156a623 sw s5,12(a3) +800000f8: 0166a823 sw s6,16(a3) +800000fc: 0176aa23 sw s7,20(a3) +80000100: 00001617 auipc a2,0x1 +80000104: f1060613 addi a2,a2,-240 # 80001010 +80000108: 00001697 auipc a3,0x1 +8000010c: f7868693 addi a3,a3,-136 # 80001080 +80000110: 00062b83 lw s7,0(a2) +80000114: 001bdc13 srli s8,s7,0x1 +80000118: 00fbdc93 srli s9,s7,0xf +8000011c: 01fbdd13 srli s10,s7,0x1f +80000120: 000bdd93 srli s11,s7,0x0 +80000124: 010bde13 srli t3,s7,0x10 +80000128: 0176a023 sw s7,0(a3) +8000012c: 0186a223 sw s8,4(a3) +80000130: 0196a423 sw s9,8(a3) +80000134: 01a6a623 sw s10,12(a3) +80000138: 01b6a823 sw s11,16(a3) +8000013c: 01c6aa23 sw t3,20(a3) +80000140: 00001d17 auipc s10,0x1 +80000144: ed4d0d13 addi s10,s10,-300 # 80001014 +80000148: 00001d97 auipc s11,0x1 +8000014c: f50d8d93 addi s11,s11,-176 # 80001098 +80000150: 000d2e03 lw t3,0(s10) +80000154: 001e5e93 srli t4,t3,0x1 +80000158: 001edf13 srli t5,t4,0x1 +8000015c: 001f5f93 srli t6,t5,0x1 +80000160: 001fd093 srli ra,t6,0x1 +80000164: 0010d113 srli sp,ra,0x1 +80000168: 00115193 srli gp,sp,0x1 +8000016c: 01cda023 sw t3,0(s11) +80000170: 01dda223 sw t4,4(s11) +80000174: 01eda423 sw t5,8(s11) +80000178: 01fda623 sw t6,12(s11) +8000017c: 001da823 sw ra,16(s11) +80000180: 002daa23 sw sp,20(s11) +80000184: 003dac23 sw gp,24(s11) +80000188: 00001097 auipc ra,0x1 +8000018c: e9008093 addi ra,ra,-368 # 80001018 +80000190: 00001117 auipc sp,0x1 +80000194: f2410113 addi sp,sp,-220 # 800010b4 +80000198: 0000a283 lw t0,0(ra) +8000019c: 0012d013 srli zero,t0,0x1 +800001a0: 00012023 sw zero,0(sp) +800001a4: 00001097 auipc ra,0x1 +800001a8: e7808093 addi ra,ra,-392 # 8000101c +800001ac: 00001117 auipc sp,0x1 +800001b0: f0c10113 addi sp,sp,-244 # 800010b8 +800001b4: 0000a283 lw t0,0(ra) +800001b8: 0012d013 srli zero,t0,0x1 +800001bc: 00105293 srli t0,zero,0x1 +800001c0: 00012023 sw zero,0(sp) +800001c4: 00512223 sw t0,4(sp) +800001c8: 00001517 auipc a0,0x1 +800001cc: e5850513 addi a0,a0,-424 # 80001020 +800001d0: 00001597 auipc a1,0x1 +800001d4: ef058593 addi a1,a1,-272 # 800010c0 <_end> +800001d8: f0100637 lui a2,0xf0100 +800001dc: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee6c> + +800001e0 : +800001e0: 02b50663 beq a0,a1,8000020c +800001e4: 00c52683 lw a3,12(a0) +800001e8: 00d62023 sw a3,0(a2) +800001ec: 00852683 lw a3,8(a0) +800001f0: 00d62023 sw a3,0(a2) +800001f4: 00452683 lw a3,4(a0) +800001f8: 00d62023 sw a3,0(a2) +800001fc: 00052683 lw a3,0(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 01050513 addi a0,a0,16 +80000208: fd9ff06f j 800001e0 + +8000020c : +8000020c: f0100537 lui a0,0xf0100 +80000210: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee60> +80000214: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ef10 fsw fa2,24(a4) +80001016: abcd j 80001608 <_end+0x548> + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff + +80001068 : +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff + +80001080 : +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff + +80001098 : +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff + +800010b8 : +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff diff --git a/src/test/resources/asm/I-SUB-01.elf.objdump b/src/test/resources/asm/I-SUB-01.elf.objdump new file mode 100644 index 0000000..d5fd16f --- /dev/null +++ b/src/test/resources/asm/I-SUB-01.elf.objdump @@ -0,0 +1,344 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SUB-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef1f> +80000028: 80000437 lui s0,0x80000 +8000002c: 40418233 sub tp,gp,tp +80000030: 405182b3 sub t0,gp,t0 +80000034: 40618333 sub t1,gp,t1 +80000038: 407183b3 sub t2,gp,t2 +8000003c: 40818433 sub s0,gp,s0 +80000040: 00312023 sw gp,0(sp) +80000044: 00412223 sw tp,4(sp) +80000048: 00512423 sw t0,8(sp) +8000004c: 00612623 sw t1,12(sp) +80000050: 00712823 sw t2,16(sp) +80000054: 00812a23 sw s0,20(sp) +80000058: 00001097 auipc ra,0x1 +8000005c: fac08093 addi ra,ra,-84 # 80001004 +80000060: 00001117 auipc sp,0x1 +80000064: fe810113 addi sp,sp,-24 # 80001048 +80000068: 0000a403 lw s0,0(ra) +8000006c: 00000493 li s1,0 +80000070: 00100513 li a0,1 +80000074: fff00593 li a1,-1 +80000078: 80000637 lui a2,0x80000 +8000007c: fff60613 addi a2,a2,-1 # 7fffffff <_end+0xffffef1f> +80000080: 800006b7 lui a3,0x80000 +80000084: 409404b3 sub s1,s0,s1 +80000088: 40a40533 sub a0,s0,a0 +8000008c: 40b405b3 sub a1,s0,a1 +80000090: 40c40633 sub a2,s0,a2 +80000094: 40d406b3 sub a3,s0,a3 +80000098: 00812023 sw s0,0(sp) +8000009c: 00912223 sw s1,4(sp) +800000a0: 00a12423 sw a0,8(sp) +800000a4: 00b12623 sw a1,12(sp) +800000a8: 00c12823 sw a2,16(sp) +800000ac: 00d12a23 sw a3,20(sp) +800000b0: 00001097 auipc ra,0x1 +800000b4: f5808093 addi ra,ra,-168 # 80001008 +800000b8: 00001117 auipc sp,0x1 +800000bc: fa810113 addi sp,sp,-88 # 80001060 +800000c0: 0000a683 lw a3,0(ra) +800000c4: 00000713 li a4,0 +800000c8: 00100793 li a5,1 +800000cc: fff00813 li a6,-1 +800000d0: 800008b7 lui a7,0x80000 +800000d4: fff88893 addi a7,a7,-1 # 7fffffff <_end+0xffffef1f> +800000d8: 80000937 lui s2,0x80000 +800000dc: 40e68733 sub a4,a3,a4 +800000e0: 40f687b3 sub a5,a3,a5 +800000e4: 41068833 sub a6,a3,a6 +800000e8: 411688b3 sub a7,a3,a7 +800000ec: 41268933 sub s2,a3,s2 +800000f0: 00d12023 sw a3,0(sp) +800000f4: 00e12223 sw a4,4(sp) +800000f8: 00f12423 sw a5,8(sp) +800000fc: 01012623 sw a6,12(sp) +80000100: 01112823 sw a7,16(sp) +80000104: 01212a23 sw s2,20(sp) +80000108: 00001097 auipc ra,0x1 +8000010c: f0408093 addi ra,ra,-252 # 8000100c +80000110: 00001117 auipc sp,0x1 +80000114: f6810113 addi sp,sp,-152 # 80001078 +80000118: 0000a903 lw s2,0(ra) +8000011c: 00000993 li s3,0 +80000120: 00100a13 li s4,1 +80000124: fff00a93 li s5,-1 +80000128: 80000b37 lui s6,0x80000 +8000012c: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef1f> +80000130: 80000bb7 lui s7,0x80000 +80000134: 413909b3 sub s3,s2,s3 +80000138: 41490a33 sub s4,s2,s4 +8000013c: 41590ab3 sub s5,s2,s5 +80000140: 41690b33 sub s6,s2,s6 +80000144: 41790bb3 sub s7,s2,s7 +80000148: 01212023 sw s2,0(sp) +8000014c: 01312223 sw s3,4(sp) +80000150: 01412423 sw s4,8(sp) +80000154: 01512623 sw s5,12(sp) +80000158: 01612823 sw s6,16(sp) +8000015c: 01712a23 sw s7,20(sp) +80000160: 00001097 auipc ra,0x1 +80000164: eb008093 addi ra,ra,-336 # 80001010 +80000168: 00001117 auipc sp,0x1 +8000016c: f2810113 addi sp,sp,-216 # 80001090 +80000170: 0000ab83 lw s7,0(ra) +80000174: 00000c13 li s8,0 +80000178: 00100c93 li s9,1 +8000017c: fff00d13 li s10,-1 +80000180: 80000db7 lui s11,0x80000 +80000184: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef1f> +80000188: 80000e37 lui t3,0x80000 +8000018c: 418b8c33 sub s8,s7,s8 +80000190: 419b8cb3 sub s9,s7,s9 +80000194: 41ab8d33 sub s10,s7,s10 +80000198: 41bb8db3 sub s11,s7,s11 +8000019c: 41cb8e33 sub t3,s7,t3 +800001a0: 01712023 sw s7,0(sp) +800001a4: 01812223 sw s8,4(sp) +800001a8: 01912423 sw s9,8(sp) +800001ac: 01a12623 sw s10,12(sp) +800001b0: 01b12823 sw s11,16(sp) +800001b4: 01c12a23 sw t3,20(sp) +800001b8: 00001c97 auipc s9,0x1 +800001bc: e5cc8c93 addi s9,s9,-420 # 80001014 +800001c0: 00001d17 auipc s10,0x1 +800001c4: ee8d0d13 addi s10,s10,-280 # 800010a8 +800001c8: 000cae03 lw t3,0(s9) +800001cc: 00100d93 li s11,1 +800001d0: 41be0eb3 sub t4,t3,s11 +800001d4: 41be8f33 sub t5,t4,s11 +800001d8: 41bf0fb3 sub t6,t5,s11 +800001dc: 41bf80b3 sub ra,t6,s11 +800001e0: 41b08133 sub sp,ra,s11 +800001e4: 41b101b3 sub gp,sp,s11 +800001e8: 01bd2023 sw s11,0(s10) +800001ec: 01cd2223 sw t3,4(s10) +800001f0: 01dd2423 sw t4,8(s10) +800001f4: 01ed2623 sw t5,12(s10) +800001f8: 01fd2823 sw t6,16(s10) +800001fc: 001d2a23 sw ra,20(s10) +80000200: 002d2c23 sw sp,24(s10) +80000204: 003d2e23 sw gp,28(s10) +80000208: 00001097 auipc ra,0x1 +8000020c: e1008093 addi ra,ra,-496 # 80001018 +80000210: 00001117 auipc sp,0x1 +80000214: eb810113 addi sp,sp,-328 # 800010c8 +80000218: 0000ae03 lw t3,0(ra) +8000021c: f7ff9db7 lui s11,0xf7ff9 +80000220: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +80000224: 41be0033 sub zero,t3,s11 +80000228: 00012023 sw zero,0(sp) +8000022c: 00001097 auipc ra,0x1 +80000230: df008093 addi ra,ra,-528 # 8000101c +80000234: 00001117 auipc sp,0x1 +80000238: e9810113 addi sp,sp,-360 # 800010cc +8000023c: 0000ae03 lw t3,0(ra) +80000240: f7ff9db7 lui s11,0xf7ff9 +80000244: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +80000248: 41be0033 sub zero,t3,s11 +8000024c: 400002b3 neg t0,zero +80000250: 00012023 sw zero,0(sp) +80000254: 00512223 sw t0,4(sp) +80000258: 00001097 auipc ra,0x1 +8000025c: dc808093 addi ra,ra,-568 # 80001020 +80000260: 00001117 auipc sp,0x1 +80000264: e7410113 addi sp,sp,-396 # 800010d4 +80000268: 0000a183 lw gp,0(ra) +8000026c: 40018233 sub tp,gp,zero +80000270: 400202b3 sub t0,tp,zero +80000274: 40500333 neg t1,t0 +80000278: 40030733 sub a4,t1,zero +8000027c: 400707b3 sub a5,a4,zero +80000280: 40078833 sub a6,a5,zero +80000284: 41000cb3 neg s9,a6 +80000288: 41900d33 neg s10,s9 +8000028c: 400d0db3 sub s11,s10,zero +80000290: 00412023 sw tp,0(sp) +80000294: 01a12223 sw s10,4(sp) +80000298: 01b12423 sw s11,8(sp) +8000029c: 00001517 auipc a0,0x1 +800002a0: d9450513 addi a0,a0,-620 # 80001030 +800002a4: 00001597 auipc a1,0x1 +800002a8: e3c58593 addi a1,a1,-452 # 800010e0 <_end> +800002ac: f0100637 lui a2,0xf0100 +800002b0: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +800002b4 : +800002b4: 02b50663 beq a0,a1,800002e0 +800002b8: 00c52683 lw a3,12(a0) +800002bc: 00d62023 sw a3,0(a2) +800002c0: 00852683 lw a3,8(a0) +800002c4: 00d62023 sw a3,0(a2) +800002c8: 00452683 lw a3,4(a0) +800002cc: 00d62023 sw a3,0(a2) +800002d0: 00052683 lw a3,0(a0) +800002d4: 00d62023 sw a3,0(a2) +800002d8: 01050513 addi a0,a0,16 +800002dc: fd9ff06f j 800002b4 + +800002e0 : +800002e0: f0100537 lui a0,0xf0100 +800002e4: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +800002e8: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: abcd j 80001606 <_end+0x526> + ... + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 5814 lw a3,48(s0) +80001022: 3692 fld fa3,288(sp) + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff + +800010cc : +800010cc: ffff 0xffff +800010ce: ffff 0xffff +800010d0: ffff 0xffff +800010d2: ffff 0xffff + +800010d4 : +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-SW-01.elf.objdump b/src/test/resources/asm/I-SW-01.elf.objdump new file mode 100644 index 0000000..83179d7 --- /dev/null +++ b/src/test/resources/asm/I-SW-01.elf.objdump @@ -0,0 +1,182 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-SW-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 01008093 addi ra,ra,16 # 80001010 +80000008: 11f1f137 lui sp,0x11f1f +8000000c: 22210113 addi sp,sp,546 # 11f1f222 <_start-0x6e0e0dde> +80000010: 0020a023 sw sp,0(ra) +80000014: 00001297 auipc t0,0x1 +80000018: 00128293 addi t0,t0,1 # 80001015 +8000001c: f3334cb7 lui s9,0xf3334 +80000020: 4f4c8c93 addi s9,s9,1268 # f33344f4 <_end+0x733334a4> +80000024: ff92afa3 sw s9,-1(t0) +80000028: 00001417 auipc s0,0x1 +8000002c: fef40413 addi s0,s0,-17 # 80001017 +80000030: 55f5ffb7 lui t6,0x55f5f +80000034: 666f8f93 addi t6,t6,1638 # 55f5f666 <_start-0x2a0a099a> +80000038: 01f420a3 sw t6,1(s0) +8000003c: 00001597 auipc a1,0x1 +80000040: 7e058593 addi a1,a1,2016 # 8000181c <_end+0x7cc> +80000044: f7779637 lui a2,0xf7779 +80000048: 8f860613 addi a2,a2,-1800 # f77788f8 <_end+0x777778a8> +8000004c: 80c5a023 sw a2,-2048(a1) +80000050: 00000717 auipc a4,0x0 +80000054: 7d170713 addi a4,a4,2001 # 80000821 +80000058: 990917b7 lui a5,0x99091 +8000005c: aaa78793 addi a5,a5,-1366 # 99090aaa <_end+0x1908fa5a> +80000060: 7ef72fa3 sw a5,2047(a4) +80000064: 00001897 auipc a7,0x1 +80000068: fc488893 addi a7,a7,-60 # 80001028 +8000006c: 0bbbd937 lui s2,0xbbbd +80000070: c0c90913 addi s2,s2,-1012 # bbbcc0c <_start-0x744433f4> +80000074: dd0d19b7 lui s3,0xdd0d1 +80000078: eee98993 addi s3,s3,-274 # dd0d0eee <_end+0x5d0cfe9e> +8000007c: 0fff0a37 lui s4,0xfff0 +80000080: 0f0a0a13 addi s4,s4,240 # fff00f0 <_start-0x7000ff10> +80000084: ff28ae23 sw s2,-4(a7) +80000088: 0138a023 sw s3,0(a7) +8000008c: 0148a223 sw s4,4(a7) +80000090: 00001b17 auipc s6,0x1 +80000094: fa0b0b13 addi s6,s6,-96 # 80001030 +80000098: 12345037 lui zero,0x12345 +8000009c: 67800013 li zero,1656 +800000a0: 000b2023 sw zero,0(s6) +800000a4: 00001a97 auipc s5,0x1 +800000a8: f5ca8a93 addi s5,s5,-164 # 80001000 +800000ac: 112239b7 lui s3,0x11223 +800000b0: 34498993 addi s3,s3,836 # 11223344 <_start-0x6eddccbc> +800000b4: 000aab83 lw s7,0(s5) +800000b8: 013ba023 sw s3,0(s7) +800000bc: 00001b97 auipc s7,0x1 +800000c0: f48b8b93 addi s7,s7,-184 # 80001004 +800000c4: 00001c17 auipc s8,0x1 +800000c8: f74c0c13 addi s8,s8,-140 # 80001038 +800000cc: 000bac83 lw s9,0(s7) +800000d0: 019c2023 sw s9,0(s8) +800000d4: 00001d17 auipc s10,0x1 +800000d8: f68d0d13 addi s10,s10,-152 # 8000103c +800000dc: 76543cb7 lui s9,0x76543 +800000e0: 210c8c93 addi s9,s9,528 # 76543210 <_start-0x9abcdf0> +800000e4: 019d2023 sw s9,0(s10) +800000e8: 00000c93 li s9,0 +800000ec: 00001e17 auipc t3,0x1 +800000f0: f54e0e13 addi t3,t3,-172 # 80001040 +800000f4: 89abddb7 lui s11,0x89abd +800000f8: defd8d93 addi s11,s11,-529 # 89abcdef <_end+0x9abbd9f> +800000fc: 01be2023 sw s11,0(t3) +80000100: ffce0e13 addi t3,t3,-4 +80000104: 00001e97 auipc t4,0x1 +80000108: f40e8e93 addi t4,t4,-192 # 80001044 +8000010c: 14726db7 lui s11,0x14726 +80000110: 836d8d93 addi s11,s11,-1994 # 14725836 <_start-0x6b8da7ca> +80000114: 01bea023 sw s11,0(t4) +80000118: 000eaf03 lw t5,0(t4) +8000011c: 01eea223 sw t5,4(t4) +80000120: 00001097 auipc ra,0x1 +80000124: f2c08093 addi ra,ra,-212 # 8000104c +80000128: 96385137 lui sp,0x96385 +8000012c: 20110113 addi sp,sp,513 # 96385201 <_end+0x163841b1> +80000130: 258151b7 lui gp,0x25815 +80000134: 96318193 addi gp,gp,-1693 # 25814963 <_start-0x5a7eb69d> +80000138: 0020a023 sw sp,0(ra) +8000013c: 0030a023 sw gp,0(ra) +80000140: 00001517 auipc a0,0x1 +80000144: ed050513 addi a0,a0,-304 # 80001010 +80000148: 00001597 auipc a1,0x1 +8000014c: f0858593 addi a1,a1,-248 # 80001050 <_end> +80000150: f0100637 lui a2,0xf0100 +80000154: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feedc> + +80000158 : +80000158: 02b50663 beq a0,a1,80000184 +8000015c: 00c52683 lw a3,12(a0) +80000160: 00d62023 sw a3,0(a2) +80000164: 00852683 lw a3,8(a0) +80000168: 00d62023 sw a3,0(a2) +8000016c: 00452683 lw a3,4(a0) +80000170: 00d62023 sw a3,0(a2) +80000174: 00052683 lw a3,0(a0) +80000178: 00d62023 sw a3,0(a2) +8000017c: 01050513 addi a0,a0,16 +80000180: fd9ff06f j 80000158 + +80000184 : +80000184: f0100537 lui a0,0xf0100 +80000188: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feed0> +8000018c: 00052023 sw zero,0(a0) +80000190: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 1034 addi a3,sp,40 +80001002: 8000 0x8000 + +80001004 : +80001004: def0 sw a2,124(a3) +80001006: 9abc 0x9abc + ... + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff + +80001018 : +80001018: ffff 0xffff +8000101a: ffff 0xffff + +8000101c : +8000101c: ffff 0xffff +8000101e: ffff 0xffff + +80001020 : +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff + +80001034 : +80001034: ffff 0xffff +80001036: ffff 0xffff + +80001038 : +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff + +80001040 : +80001040: ffff 0xffff +80001042: ffff 0xffff + +80001044 : +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff + +8000104c : +8000104c: ffff 0xffff +8000104e: ffff 0xffff diff --git a/src/test/resources/asm/I-XOR-01.elf.objdump b/src/test/resources/asm/I-XOR-01.elf.objdump new file mode 100644 index 0000000..aa98446 --- /dev/null +++ b/src/test/resources/asm/I-XOR-01.elf.objdump @@ -0,0 +1,350 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-XOR-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 00000213 li tp,0 +80000018: 00100293 li t0,1 +8000001c: fff00313 li t1,-1 +80000020: 800003b7 lui t2,0x80000 +80000024: fff38393 addi t2,t2,-1 # 7fffffff <_end+0xffffef1f> +80000028: 80000437 lui s0,0x80000 +8000002c: 0041c233 xor tp,gp,tp +80000030: 0051c2b3 xor t0,gp,t0 +80000034: 0061c333 xor t1,gp,t1 +80000038: 0071c3b3 xor t2,gp,t2 +8000003c: 0081c433 xor s0,gp,s0 +80000040: 00312023 sw gp,0(sp) +80000044: 00412223 sw tp,4(sp) +80000048: 00512423 sw t0,8(sp) +8000004c: 00612623 sw t1,12(sp) +80000050: 00712823 sw t2,16(sp) +80000054: 00812a23 sw s0,20(sp) +80000058: 00001097 auipc ra,0x1 +8000005c: fac08093 addi ra,ra,-84 # 80001004 +80000060: 00001117 auipc sp,0x1 +80000064: fe810113 addi sp,sp,-24 # 80001048 +80000068: 0000a403 lw s0,0(ra) +8000006c: 00000493 li s1,0 +80000070: 00100513 li a0,1 +80000074: fff00593 li a1,-1 +80000078: 80000637 lui a2,0x80000 +8000007c: fff60613 addi a2,a2,-1 # 7fffffff <_end+0xffffef1f> +80000080: 800006b7 lui a3,0x80000 +80000084: 009444b3 xor s1,s0,s1 +80000088: 00a44533 xor a0,s0,a0 +8000008c: 00b445b3 xor a1,s0,a1 +80000090: 00c44633 xor a2,s0,a2 +80000094: 00d446b3 xor a3,s0,a3 +80000098: 00812023 sw s0,0(sp) +8000009c: 00912223 sw s1,4(sp) +800000a0: 00a12423 sw a0,8(sp) +800000a4: 00b12623 sw a1,12(sp) +800000a8: 00c12823 sw a2,16(sp) +800000ac: 00d12a23 sw a3,20(sp) +800000b0: 00001097 auipc ra,0x1 +800000b4: f5808093 addi ra,ra,-168 # 80001008 +800000b8: 00001117 auipc sp,0x1 +800000bc: fa810113 addi sp,sp,-88 # 80001060 +800000c0: 0000a683 lw a3,0(ra) +800000c4: 00000713 li a4,0 +800000c8: 00100793 li a5,1 +800000cc: fff00813 li a6,-1 +800000d0: 800008b7 lui a7,0x80000 +800000d4: fff88893 addi a7,a7,-1 # 7fffffff <_end+0xffffef1f> +800000d8: 80000937 lui s2,0x80000 +800000dc: 00e6c733 xor a4,a3,a4 +800000e0: 00f6c7b3 xor a5,a3,a5 +800000e4: 0106c833 xor a6,a3,a6 +800000e8: 0116c8b3 xor a7,a3,a7 +800000ec: 0126c933 xor s2,a3,s2 +800000f0: 00d12023 sw a3,0(sp) +800000f4: 00e12223 sw a4,4(sp) +800000f8: 00f12423 sw a5,8(sp) +800000fc: 01012623 sw a6,12(sp) +80000100: 01112823 sw a7,16(sp) +80000104: 01212a23 sw s2,20(sp) +80000108: 00001097 auipc ra,0x1 +8000010c: f0408093 addi ra,ra,-252 # 8000100c +80000110: 00001117 auipc sp,0x1 +80000114: f6810113 addi sp,sp,-152 # 80001078 +80000118: 0000a903 lw s2,0(ra) +8000011c: 00000993 li s3,0 +80000120: 00100a13 li s4,1 +80000124: fff00a93 li s5,-1 +80000128: 80000b37 lui s6,0x80000 +8000012c: fffb0b13 addi s6,s6,-1 # 7fffffff <_end+0xffffef1f> +80000130: 80000bb7 lui s7,0x80000 +80000134: 013949b3 xor s3,s2,s3 +80000138: 01494a33 xor s4,s2,s4 +8000013c: 01594ab3 xor s5,s2,s5 +80000140: 01694b33 xor s6,s2,s6 +80000144: 01794bb3 xor s7,s2,s7 +80000148: 01212023 sw s2,0(sp) +8000014c: 01312223 sw s3,4(sp) +80000150: 01412423 sw s4,8(sp) +80000154: 01512623 sw s5,12(sp) +80000158: 01612823 sw s6,16(sp) +8000015c: 01712a23 sw s7,20(sp) +80000160: 00001097 auipc ra,0x1 +80000164: eb008093 addi ra,ra,-336 # 80001010 +80000168: 00001117 auipc sp,0x1 +8000016c: f2810113 addi sp,sp,-216 # 80001090 +80000170: 0000ab83 lw s7,0(ra) +80000174: 00000c13 li s8,0 +80000178: 00100c93 li s9,1 +8000017c: fff00d13 li s10,-1 +80000180: 80000db7 lui s11,0x80000 +80000184: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef1f> +80000188: 80000e37 lui t3,0x80000 +8000018c: 018bcc33 xor s8,s7,s8 +80000190: 019bccb3 xor s9,s7,s9 +80000194: 01abcd33 xor s10,s7,s10 +80000198: 01bbcdb3 xor s11,s7,s11 +8000019c: 01cbce33 xor t3,s7,t3 +800001a0: 01712023 sw s7,0(sp) +800001a4: 01812223 sw s8,4(sp) +800001a8: 01912423 sw s9,8(sp) +800001ac: 01a12623 sw s10,12(sp) +800001b0: 01b12823 sw s11,16(sp) +800001b4: 01c12a23 sw t3,20(sp) +800001b8: 00001c97 auipc s9,0x1 +800001bc: e5cc8c93 addi s9,s9,-420 # 80001014 +800001c0: 00001d17 auipc s10,0x1 +800001c4: ee8d0d13 addi s10,s10,-280 # 800010a8 +800001c8: 000cae03 lw t3,0(s9) +800001cc: 07f00213 li tp,127 +800001d0: 03f00293 li t0,63 +800001d4: 01f00313 li t1,31 +800001d8: 00f00393 li t2,15 +800001dc: 00700413 li s0,7 +800001e0: 00300493 li s1,3 +800001e4: 004e4eb3 xor t4,t3,tp +800001e8: 005ecf33 xor t5,t4,t0 +800001ec: 006f4fb3 xor t6,t5,t1 +800001f0: 007fc0b3 xor ra,t6,t2 +800001f4: 0080c133 xor sp,ra,s0 +800001f8: 009141b3 xor gp,sp,s1 +800001fc: 004d2023 sw tp,0(s10) +80000200: 01cd2223 sw t3,4(s10) +80000204: 01dd2423 sw t4,8(s10) +80000208: 01ed2623 sw t5,12(s10) +8000020c: 01fd2823 sw t6,16(s10) +80000210: 001d2a23 sw ra,20(s10) +80000214: 002d2c23 sw sp,24(s10) +80000218: 003d2e23 sw gp,28(s10) +8000021c: 00001097 auipc ra,0x1 +80000220: dfc08093 addi ra,ra,-516 # 80001018 +80000224: 00001117 auipc sp,0x1 +80000228: ea410113 addi sp,sp,-348 # 800010c8 +8000022c: 0000ae03 lw t3,0(ra) +80000230: f7ff9db7 lui s11,0xf7ff9 +80000234: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +80000238: 01be4033 xor zero,t3,s11 +8000023c: 00012023 sw zero,0(sp) +80000240: 00001097 auipc ra,0x1 +80000244: ddc08093 addi ra,ra,-548 # 8000101c +80000248: 00001117 auipc sp,0x1 +8000024c: e8410113 addi sp,sp,-380 # 800010cc +80000250: 0000ae03 lw t3,0(ra) +80000254: f7ff9db7 lui s11,0xf7ff9 +80000258: 818d8d93 addi s11,s11,-2024 # f7ff8818 <_end+0x77ff7738> +8000025c: 01be4033 xor zero,t3,s11 +80000260: 000042b3 xor t0,zero,zero +80000264: 00012023 sw zero,0(sp) +80000268: 00512223 sw t0,4(sp) +8000026c: 00001097 auipc ra,0x1 +80000270: db408093 addi ra,ra,-588 # 80001020 +80000274: 00001117 auipc sp,0x1 +80000278: e6010113 addi sp,sp,-416 # 800010d4 +8000027c: 0000a183 lw gp,0(ra) +80000280: 0001c233 xor tp,gp,zero +80000284: 000242b3 xor t0,tp,zero +80000288: 00504333 xor t1,zero,t0 +8000028c: 00034733 xor a4,t1,zero +80000290: 000747b3 xor a5,a4,zero +80000294: 0007c833 xor a6,a5,zero +80000298: 01004cb3 xor s9,zero,a6 +8000029c: 01904d33 xor s10,zero,s9 +800002a0: 000d4db3 xor s11,s10,zero +800002a4: 00412023 sw tp,0(sp) +800002a8: 01a12223 sw s10,4(sp) +800002ac: 01b12423 sw s11,8(sp) +800002b0: 00001517 auipc a0,0x1 +800002b4: d8050513 addi a0,a0,-640 # 80001030 +800002b8: 00001597 auipc a1,0x1 +800002bc: e2858593 addi a1,a1,-472 # 800010e0 <_end> +800002c0: f0100637 lui a2,0xf0100 +800002c4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +800002c8 : +800002c8: 02b50663 beq a0,a1,800002f4 +800002cc: 00c52683 lw a3,12(a0) +800002d0: 00d62023 sw a3,0(a2) +800002d4: 00852683 lw a3,8(a0) +800002d8: 00d62023 sw a3,0(a2) +800002dc: 00452683 lw a3,4(a0) +800002e0: 00d62023 sw a3,0(a2) +800002e4: 00052683 lw a3,0(a0) +800002e8: 00d62023 sw a3,0(a2) +800002ec: 01050513 addi a0,a0,16 +800002f0: fd9ff06f j 800002c8 + +800002f4 : +800002f4: f0100537 lui a0,0xf0100 +800002f8: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +800002fc: 00052023 sw zero,0(a0) +80000300: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ffff 0xffff +80001016: abcd j 80001608 <_end+0x528> + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 5814 lw a3,48(s0) +80001022: 3692 fld fa3,288(sp) + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff + +800010cc : +800010cc: ffff 0xffff +800010ce: ffff 0xffff +800010d0: ffff 0xffff +800010d2: ffff 0xffff + +800010d4 : +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/asm/I-XORI-01.elf.objdump b/src/test/resources/asm/I-XORI-01.elf.objdump new file mode 100644 index 0000000..f969f99 --- /dev/null +++ b/src/test/resources/asm/I-XORI-01.elf.objdump @@ -0,0 +1,310 @@ + +/home/spinalvm/hdl/riscv-compliance/work//I-XORI-01.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001097 auipc ra,0x1 +80000004: 00008093 mv ra,ra +80000008: 00001117 auipc sp,0x1 +8000000c: 02810113 addi sp,sp,40 # 80001030 +80000010: 0000a183 lw gp,0(ra) # 80001000 +80000014: 0011c213 xori tp,gp,1 +80000018: 7ff1c293 xori t0,gp,2047 +8000001c: fff1c313 not t1,gp +80000020: 0001c393 xori t2,gp,0 +80000024: 8001c413 xori s0,gp,-2048 +80000028: 00312023 sw gp,0(sp) +8000002c: 00412223 sw tp,4(sp) +80000030: 00512423 sw t0,8(sp) +80000034: 00612623 sw t1,12(sp) +80000038: 00712823 sw t2,16(sp) +8000003c: 00812a23 sw s0,20(sp) +80000040: 00001097 auipc ra,0x1 +80000044: fc408093 addi ra,ra,-60 # 80001004 +80000048: 00001117 auipc sp,0x1 +8000004c: 00010113 mv sp,sp +80000050: 0000a403 lw s0,0(ra) +80000054: 00144493 xori s1,s0,1 +80000058: 7ff44513 xori a0,s0,2047 +8000005c: fff44593 not a1,s0 +80000060: 00044613 xori a2,s0,0 +80000064: 80044693 xori a3,s0,-2048 +80000068: 00812023 sw s0,0(sp) # 80001048 +8000006c: 00912223 sw s1,4(sp) +80000070: 00a12423 sw a0,8(sp) +80000074: 00b12623 sw a1,12(sp) +80000078: 00c12823 sw a2,16(sp) +8000007c: 00d12a23 sw a3,20(sp) +80000080: 00001097 auipc ra,0x1 +80000084: f8808093 addi ra,ra,-120 # 80001008 +80000088: 00001117 auipc sp,0x1 +8000008c: fd810113 addi sp,sp,-40 # 80001060 +80000090: 0000a683 lw a3,0(ra) +80000094: 0016c713 xori a4,a3,1 +80000098: 7ff6c793 xori a5,a3,2047 +8000009c: fff6c813 not a6,a3 +800000a0: 0006c893 xori a7,a3,0 +800000a4: 8006c913 xori s2,a3,-2048 +800000a8: 00d12023 sw a3,0(sp) +800000ac: 00e12223 sw a4,4(sp) +800000b0: 00f12423 sw a5,8(sp) +800000b4: 01012623 sw a6,12(sp) +800000b8: 01112823 sw a7,16(sp) +800000bc: 01212a23 sw s2,20(sp) +800000c0: 00001097 auipc ra,0x1 +800000c4: f4c08093 addi ra,ra,-180 # 8000100c +800000c8: 00001117 auipc sp,0x1 +800000cc: fb010113 addi sp,sp,-80 # 80001078 +800000d0: 0000a903 lw s2,0(ra) +800000d4: 00194993 xori s3,s2,1 +800000d8: 7ff94a13 xori s4,s2,2047 +800000dc: fff94a93 not s5,s2 +800000e0: 00094b13 xori s6,s2,0 +800000e4: 80094b93 xori s7,s2,-2048 +800000e8: 01212023 sw s2,0(sp) +800000ec: 01312223 sw s3,4(sp) +800000f0: 01412423 sw s4,8(sp) +800000f4: 01512623 sw s5,12(sp) +800000f8: 01612823 sw s6,16(sp) +800000fc: 01712a23 sw s7,20(sp) +80000100: 00001097 auipc ra,0x1 +80000104: f1008093 addi ra,ra,-240 # 80001010 +80000108: 00001117 auipc sp,0x1 +8000010c: f8810113 addi sp,sp,-120 # 80001090 +80000110: 0000ab83 lw s7,0(ra) +80000114: 001bcc13 xori s8,s7,1 +80000118: 7ffbcc93 xori s9,s7,2047 +8000011c: fffbcd13 not s10,s7 +80000120: 000bcd93 xori s11,s7,0 +80000124: 800bce13 xori t3,s7,-2048 +80000128: 01712023 sw s7,0(sp) +8000012c: 01812223 sw s8,4(sp) +80000130: 01912423 sw s9,8(sp) +80000134: 01a12623 sw s10,12(sp) +80000138: 01b12823 sw s11,16(sp) +8000013c: 01c12a23 sw t3,20(sp) +80000140: 00001d17 auipc s10,0x1 +80000144: ed4d0d13 addi s10,s10,-300 # 80001014 +80000148: 00001d97 auipc s11,0x1 +8000014c: f60d8d93 addi s11,s11,-160 # 800010a8 +80000150: 000d2e03 lw t3,0(s10) +80000154: 07fe4e93 xori t4,t3,127 +80000158: 03fecf13 xori t5,t4,63 +8000015c: 01ff4f93 xori t6,t5,31 +80000160: 00ffc093 xori ra,t6,15 +80000164: 0070c113 xori sp,ra,7 +80000168: 00314193 xori gp,sp,3 +8000016c: 01cda023 sw t3,0(s11) +80000170: 01dda223 sw t4,4(s11) +80000174: 01eda423 sw t5,8(s11) +80000178: 01fda623 sw t6,12(s11) +8000017c: 001da823 sw ra,16(s11) +80000180: 002daa23 sw sp,20(s11) +80000184: 003dac23 sw gp,24(s11) +80000188: 00001097 auipc ra,0x1 +8000018c: e9008093 addi ra,ra,-368 # 80001018 +80000190: 00001117 auipc sp,0x1 +80000194: f3410113 addi sp,sp,-204 # 800010c4 +80000198: 0000a283 lw t0,0(ra) +8000019c: 0012c013 xori zero,t0,1 +800001a0: 00012023 sw zero,0(sp) +800001a4: 00001097 auipc ra,0x1 +800001a8: e7808093 addi ra,ra,-392 # 8000101c +800001ac: 00001117 auipc sp,0x1 +800001b0: f1c10113 addi sp,sp,-228 # 800010c8 +800001b4: 0000a283 lw t0,0(ra) +800001b8: 0012c013 xori zero,t0,1 +800001bc: 00104293 xori t0,zero,1 +800001c0: 00012023 sw zero,0(sp) +800001c4: 00512223 sw t0,4(sp) +800001c8: 00001097 auipc ra,0x1 +800001cc: e5808093 addi ra,ra,-424 # 80001020 +800001d0: 00001117 auipc sp,0x1 +800001d4: f0010113 addi sp,sp,-256 # 800010d0 +800001d8: 0000a183 lw gp,0(ra) +800001dc: 0001c213 xori tp,gp,0 +800001e0: 00024293 xori t0,tp,0 +800001e4: 0002c313 xori t1,t0,0 +800001e8: 00034713 xori a4,t1,0 +800001ec: 00074793 xori a5,a4,0 +800001f0: 0007c813 xori a6,a5,0 +800001f4: 00084c93 xori s9,a6,0 +800001f8: 000ccd13 xori s10,s9,0 +800001fc: 000d4d93 xori s11,s10,0 +80000200: 00312023 sw gp,0(sp) +80000204: 00412223 sw tp,4(sp) +80000208: 01a12423 sw s10,8(sp) +8000020c: 01b12623 sw s11,12(sp) +80000210: 00001517 auipc a0,0x1 +80000214: e2050513 addi a0,a0,-480 # 80001030 +80000218: 00001597 auipc a1,0x1 +8000021c: ec858593 addi a1,a1,-312 # 800010e0 <_end> +80000220: f0100637 lui a2,0xf0100 +80000224: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee4c> + +80000228 : +80000228: 02b50663 beq a0,a1,80000254 +8000022c: 00c52683 lw a3,12(a0) +80000230: 00d62023 sw a3,0(a2) +80000234: 00852683 lw a3,8(a0) +80000238: 00d62023 sw a3,0(a2) +8000023c: 00452683 lw a3,4(a0) +80000240: 00d62023 sw a3,0(a2) +80000244: 00052683 lw a3,0(a0) +80000248: 00d62023 sw a3,0(a2) +8000024c: 01050513 addi a0,a0,16 +80000250: fd9ff06f j 80000228 + +80000254 : +80000254: f0100537 lui a0,0xf0100 +80000258: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee40> +8000025c: 00052023 sw zero,0(a0) +80000260: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: 0000 unimp + ... + +80001004 : +80001004: 0001 nop + ... + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: 7fff 0x7fff + +80001010 : +80001010: 0000 unimp +80001012: 8000 0x8000 + +80001014 : +80001014: ffff 0xffff +80001016: abcd j 80001608 <_end+0x528> + +80001018 : +80001018: 5678 lw a4,108(a2) +8000101a: 1234 addi a3,sp,296 + +8000101c : +8000101c: ba98 fsd fa4,48(a3) +8000101e: fedc fsw fa5,60(a3) + +80001020 : +80001020: 5814 lw a3,48(s0) +80001022: 3692 fld fa3,288(sp) + ... + +80001030 : +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff + +80001048 : +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff + +80001060 : +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff + +80001090 : +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff + +800010a8 : +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff + +800010c4 : +800010c4: ffff 0xffff +800010c6: ffff 0xffff + +800010c8 : +800010c8: ffff 0xffff +800010ca: ffff 0xffff +800010cc: ffff 0xffff +800010ce: ffff 0xffff + +800010d0 : +800010d0: ffff 0xffff +800010d2: ffff 0xffff +800010d4: ffff 0xffff +800010d6: ffff 0xffff +800010d8: ffff 0xffff +800010da: ffff 0xffff +800010dc: ffff 0xffff +800010de: ffff 0xffff diff --git a/src/test/resources/hex/I-ADD-01.elf.hex b/src/test/resources/hex/I-ADD-01.elf.hex new file mode 100644 index 0000000..038e1f0 --- /dev/null +++ b/src/test/resources/hex/I-ADD-01.elf.hex @@ -0,0 +1,65 @@ +:0200000480007A +:100000009710000093800000171100001301810277 +:1000100083A1000013020000930210001303F0FFFD +:10002000B70300809383F3FF3704008033824100DD +:10003000B382510033836100B38371003384810044 +:100040002320310023224100232451002326610074 +:1000500023287100232A8100971000009380C0FAA2 +:1000600017110000130181FE03A400009304000097 +:10007000130510009305F0FF370600801306F6FF06 +:10008000B7060080B30494003305A400B305B400A0 +:100090003306C400B306D40023208100232291003C +:1000A0002324A1002326B1002328C100232AD10044 +:1000B00097100000938080F517110000130181FA5A +:1000C00083A6000013070000930710001308F0FF39 +:1000D000B70800809388F8FF370900803387E6006F +:1000E000B387F60033880601B388160133892601E9 +:1000F0002320D1002322E1002324F1002326010143 +:1001000023281101232A210197100000938040F039 +:1001100017110000130181F603A9000093090000E4 +:10012000130A1000930AF0FF370B0080130BFBFF3C +:10013000B70B0080B3093901330A4901B30A5901E9 +:10014000330B6901B30B79012320210123223101F3 +:10015000232441012326510123286101232A71010F +:1001600097100000938000EB17110000130181F23B +:1001700083AB0000130C0000930C1000130DF0FF74 +:10018000B70D0080938DFDFF370E0080338C8B01FF +:10019000B38C9B01338DAB01B38DBB01338ECB018F +:1001A0002320710123228101232491012326A1010F +:1001B0002328B101232AC101971C0000938CCCE5B0 +:1001C000171D0000130D8DEE03AE0C00930D1000F3 +:1001D000B30EBE01338FBE01B30FBF01B380BF01A9 +:1001E0003381B001B301B1012320BD012322CD0130 +:1001F0002324DD012326ED012328FD01232A1D00F0 +:10020000232C2D00232E3D0097100000938000E149 +:1002100017110000130181EB03AE0000B79DFFF73B +:10022000938D8D813300BE012320010097100000C3 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a/src/test/resources/ref/I-RF_x0-01.reference_output b/src/test/resources/ref/I-RF_x0-01.reference_output new file mode 100644 index 0000000..a0b36af --- /dev/null +++ b/src/test/resources/ref/I-RF_x0-01.reference_output @@ -0,0 +1,3 @@ +00000000000000000000000000000000 +00000000000000000000000000000000 +00000000000000000000000000000000 diff --git a/src/test/resources/ref/I-SB-01.reference_output b/src/test/resources/ref/I-SB-01.reference_output new file mode 100644 index 0000000..288281f --- /dev/null +++ b/src/test/resources/ref/I-SB-01.reference_output @@ -0,0 +1,4 @@ +000000f800000066000000f4aaaabb22 +0fff00f0dd0d0eee0bbbcc0c000000aa +00000010000000f00000004487654300 +000000630000003600000036000000ef diff --git a/src/test/resources/ref/I-SH-01.reference_output b/src/test/resources/ref/I-SH-01.reference_output new file mode 100644 index 0000000..8f22e2d --- /dev/null +++ b/src/test/resources/ref/I-SH-01.reference_output @@ -0,0 +1,4 @@ +000088f80000f666000044f4aaaaf222 +0fff00f0dd0d0eee0bbbcc0c00000aaa +000032100000def00000334487650000 +0000496300005836000058360000cdef diff --git a/src/test/resources/ref/I-SLL-01.reference_output b/src/test/resources/ref/I-SLL-01.reference_output new file mode 100644 index 0000000..18bb825 --- /dev/null +++ b/src/test/resources/ref/I-SLL-01.reference_output @@ -0,0 +1,11 @@ +00000000000000000000000000000000 +00000002000000010000000000000000 +00010000000000018000000000008000 +80000000ffff8000fffffffeffffffff +fffffffe7fffffffffff0000ffffffff +ffff00007fffffff80000000ffff8000 +00000000000000000000000080000000 +579bde20abcdef100000000080000000 +79bde200bcdef1005e6f7880af37bc40 +000000000000000000000000f37bc400 +80000000a19080000eca864287654321 diff --git a/src/test/resources/ref/I-SLLI-01.reference_output b/src/test/resources/ref/I-SLLI-01.reference_output new file mode 100644 index 0000000..25818ac --- /dev/null +++ b/src/test/resources/ref/I-SLLI-01.reference_output @@ -0,0 +1,10 @@ +00000000000000000000000000000000 +00000002000000010000000000000000 +00010000000000018000000000008000 +80000000ffff8000fffffffeffffffff +fffffffe7fffffffffff0000ffffffff +ffff00007fffffff80000000ffff8000 +00000000000000000000000080000000 +579bde20abcdef100000000080000000 +79bde200bcdef1005e6f7880af37bc40 +000000000000000000000000f37bc400 diff --git a/src/test/resources/ref/I-SLT-01.reference_output b/src/test/resources/ref/I-SLT-01.reference_output new file mode 100644 index 0000000..ffc1108 --- /dev/null +++ b/src/test/resources/ref/I-SLT-01.reference_output @@ -0,0 +1,12 @@ +00000000000000010000000100000000 +00000000000000010000000000000000 +00000000000000000000000000000001 +000000000000000100000001ffffffff +000000007fffffff0000000000000001 +00000000000000000000000000000000 +00000001000000010000000180000000 +ffffffff000000000000000000000001 +00000000000000010000000100000001 +00000000000000000000000000000000 +00000001000000010000000000000001 +00000001000000000000000100000000 diff --git a/src/test/resources/ref/I-SLTI-01.reference_output b/src/test/resources/ref/I-SLTI-01.reference_output new file mode 100644 index 0000000..ab1cdda --- /dev/null +++ b/src/test/resources/ref/I-SLTI-01.reference_output @@ -0,0 +1,11 @@ +00000000000000010000000100000000 +00000000000000010000000000000000 +00000000000000000000000000000001 +000000000000000100000001ffffffff +000000007fffffff0000000000000001 +00000000000000000000000000000000 +00000001000000010000000180000000 +00000000ffffffff0000000100000001 +00000000000000010000000100000000 +00000001000000000000000000000000 +00000001000000000000000100000000 diff --git a/src/test/resources/ref/I-SLTIU-01.reference_output b/src/test/resources/ref/I-SLTIU-01.reference_output new file mode 100644 index 0000000..fae3854 --- /dev/null +++ b/src/test/resources/ref/I-SLTIU-01.reference_output @@ -0,0 +1,11 @@ +00000001000000010000000100000000 +00000000000000010000000100000000 +00000001000000000000000100000001 +000000000000000000000000ffffffff +000000007fffffff0000000000000000 +00000001000000000000000100000000 +00000001000000000000000080000000 +00000000000000010000000100000000 +00000001000000010000000100000000 +00000001000000000000000100000000 +00000001000000000000000100000000 diff --git a/src/test/resources/ref/I-SLTU-01.reference_output b/src/test/resources/ref/I-SLTU-01.reference_output new file mode 100644 index 0000000..aa67d8f --- /dev/null +++ b/src/test/resources/ref/I-SLTU-01.reference_output @@ -0,0 +1,12 @@ +00000001000000010000000100000000 +00000000000000010000000100000000 +00000001000000000000000100000001 +000000000000000000000000ffffffff +000000007fffffff0000000000000000 +00000001000000000000000100000000 +00000001000000000000000080000000 +00000001000000000000000000000000 +000000010000000100000001ffffffff +00000000000000000000000100000000 +00000001000000000000000000000000 +00000001000000000000000100000000 diff --git a/src/test/resources/ref/I-SRA-01.reference_output b/src/test/resources/ref/I-SRA-01.reference_output new file mode 100644 index 0000000..5338082 --- /dev/null +++ b/src/test/resources/ref/I-SRA-01.reference_output @@ -0,0 +1,11 @@ +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +ffffffffffffffffffffffffffffffff +3fffffff7fffffffffffffffffffffff +00007fff7fffffff000000000000ffff +ffffffffffff0000c000000080000000 +d5e6f788abcdef10ffff800080000000 +fd5e6f78fabcdef1f579bde2eaf37bc4 +000000000000000000000000feaf37bc +ffffffffffff0ecac3b2a19087654321 diff --git a/src/test/resources/ref/I-SRAI-01.reference_output b/src/test/resources/ref/I-SRAI-01.reference_output new file mode 100644 index 0000000..adbf5bf --- /dev/null +++ b/src/test/resources/ref/I-SRAI-01.reference_output @@ -0,0 +1,10 @@ +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +ffffffffffffffffffffffffffffffff +3fffffff7fffffffffffffffffffffff +00007fff7fffffff000000000000ffff +ffffffffffff0000c000000080000000 +d5e6f788abcdef10ffff800080000000 +fd5e6f78fabcdef1f579bde2eaf37bc4 +000000000000000000000000feaf37bc diff --git a/src/test/resources/ref/I-SRL-01.reference_output b/src/test/resources/ref/I-SRL-01.reference_output new file mode 100644 index 0000000..baa9cdf --- /dev/null +++ b/src/test/resources/ref/I-SRL-01.reference_output @@ -0,0 +1,11 @@ +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +000000010001ffff7fffffffffffffff +3fffffff7fffffff0000ffffffffffff +00007fff7fffffff000000000000ffff +00000001000100004000000080000000 +55e6f788abcdef100000800080000000 +055e6f780abcdef11579bde22af37bc4 +00000000000000000000000002af37bc +0000000100010eca43b2a19087654321 diff --git a/src/test/resources/ref/I-SRLI-01.reference_output b/src/test/resources/ref/I-SRLI-01.reference_output new file mode 100644 index 0000000..8cf21d8 --- /dev/null +++ b/src/test/resources/ref/I-SRLI-01.reference_output @@ -0,0 +1,10 @@ +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +000000010001ffff7fffffffffffffff +3fffffff7fffffff0000ffffffffffff +00007fff7fffffff000000000000ffff +00000001000100004000000080000000 +55e6f788abcdef100000800080000000 +055e6f780abcdef11579bde22af37bc4 +00000000000000000000000002af37bc diff --git a/src/test/resources/ref/I-SUB-01.reference_output b/src/test/resources/ref/I-SUB-01.reference_output new file mode 100644 index 0000000..9bd5c2f --- /dev/null +++ b/src/test/resources/ref/I-SUB-01.reference_output @@ -0,0 +1,11 @@ +00000001ffffffff0000000000000000 +00000001000000018000000080000001 +80000001800000020000000200000000 +00000000fffffffeffffffffffffffff +7fffffff7fffffff7fffffff80000000 +ffffffff00000000800000007ffffffe +800000017fffffff8000000080000000 +0000abcd000000010000000000000001 +0000abc90000abca0000abcb0000abcc +00000000000000000000abc70000abc8 +c96da7ecc96da7ec3692581400000000 diff --git a/src/test/resources/ref/I-SW-01.reference_output b/src/test/resources/ref/I-SW-01.reference_output new file mode 100644 index 0000000..7ff05bd --- /dev/null +++ b/src/test/resources/ref/I-SW-01.reference_output @@ -0,0 +1,4 @@ +f77788f855f5f666f33344f411f1f222 +0fff00f0dd0d0eee0bbbcc0c99090aaa +765432109abcdef01122334400000000 +25814963147258361472583689abcdef diff --git a/src/test/resources/ref/I-XOR-01.reference_output b/src/test/resources/ref/I-XOR-01.reference_output new file mode 100644 index 0000000..514db10 --- /dev/null +++ b/src/test/resources/ref/I-XOR-01.reference_output @@ -0,0 +1,11 @@ +ffffffff000000010000000000000000 +0000000100000001800000007fffffff +800000017ffffffefffffffe00000000 +00000000fffffffeffffffffffffffff +7fffffff7fffffff7fffffff80000000 +ffffffff00000000800000007ffffffe +7fffffff800000018000000080000000 +abcdffff0000007f00000000ffffffff +abcdffafabcdffa0abcdffbfabcdff80 +0000000000000000abcdffababcdffa8 +36925814369258143692581400000000 diff --git a/src/test/resources/ref/I-XORI-01.reference_output b/src/test/resources/ref/I-XORI-01.reference_output new file mode 100644 index 0000000..dd8c914 --- /dev/null +++ b/src/test/resources/ref/I-XORI-01.reference_output @@ -0,0 +1,11 @@ +ffffffff000007ff0000000100000000 +0000000000000001fffff80000000000 +fffff80100000001fffffffe000007fe +00000000fffff800fffffffeffffffff +7ffffffe7fffffff000007ffffffffff +800007ff7fffffff800000007ffff800 +7fffffff800007ff8000000180000000 +abcdff80abcdffff7ffff80080000000 +abcdffa8abcdffafabcdffa0abcdffbf +000000010000000000000000abcdffab +36925814369258143692581436925814 diff --git a/src/test/scala/vexriscv/experimental/GenMicro.scala b/src/test/scala/vexriscv/experimental/GenMicro.scala index e5a9eaf..c98aac0 100644 --- a/src/test/scala/vexriscv/experimental/GenMicro.scala +++ b/src/test/scala/vexriscv/experimental/GenMicro.scala @@ -14,10 +14,10 @@ object GenMicro extends App{ def cpu() = { val removeOneFetchStage = true val writeBackOpt = true - val onlyLoadWords = true + val onlyLoadWords = false val rspHoldValue = true val earlyBranch = false - val noShifter = true + val noShifter = false val pessimisticHazard = true new VexRiscv( config = VexRiscvConfig( From c26b7e15cf216052e6d31fd4a83d687a4c65a346 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 11 Oct 2018 17:56:49 +0200 Subject: [PATCH 27/56] BranchPlugin exceptions are now risc-v compliance alligned --- .gitignore | 1 + src/main/scala/vexriscv/TestsWorkspace.scala | 2 +- .../scala/vexriscv/plugin/BranchPlugin.scala | 37 ++++++++++++------- src/test/cpp/regression/I-ADD-01.out32 | 11 ------ src/test/cpp/regression/I-ADDI-01.out32 | 11 ------ src/test/cpp/regression/I-AND-01.out32 | 11 ------ src/test/cpp/regression/I-ANDI-01.out32 | 11 ------ src/test/cpp/regression/I-AUIPC-01.out32 | 4 -- src/test/cpp/regression/I-BEQ-01.out32 | 10 ----- src/test/cpp/regression/I-BGE-01.out32 | 10 ----- src/test/cpp/regression/I-BGEU-01.out32 | 10 ----- src/test/cpp/regression/I-BLT-01.out32 | 10 ----- src/test/cpp/regression/I-BLTU-01.out32 | 10 ----- src/test/cpp/regression/I-BNE-01.out32 | 10 ----- src/test/cpp/regression/I-CSRRC-01.out32 | 6 --- src/test/cpp/regression/I-CSRRCI-01.out32 | 4 -- src/test/cpp/regression/I-CSRRS-01.out32 | 6 --- src/test/cpp/regression/I-CSRRSI-01.out32 | 4 -- src/test/cpp/regression/I-CSRRW-01.out32 | 4 -- src/test/cpp/regression/I-CSRRWI-01.out32 | 2 - .../cpp/regression/I-DELAY_SLOTS-01.out32 | 2 - src/test/cpp/regression/I-EBREAK-01.out32 | 1 - src/test/cpp/regression/I-ECALL-01.out32 | 1 - src/test/cpp/regression/I-ENDIANESS-01.out32 | 2 - src/test/cpp/regression/I-FENCE.I-01.out32 | 1 - src/test/cpp/regression/I-IO.out32 | 11 ------ src/test/cpp/regression/I-JAL-01.out32 | 5 --- src/test/cpp/regression/I-JALR-01.out32 | 6 --- src/test/cpp/regression/I-LB-01.out32 | 9 ----- src/test/cpp/regression/I-LBU-01.out32 | 9 ----- src/test/cpp/regression/I-LH-01.out32 | 5 --- src/test/cpp/regression/I-LHU-01.out32 | 5 --- src/test/cpp/regression/I-LUI-01.out32 | 4 -- src/test/cpp/regression/I-LW-01.out32 | 3 -- .../cpp/regression/I-MISALIGN_JMP-01.out32 | 0 .../cpp/regression/I-MISALIGN_LDST-01.out32 | 11 ------ src/test/cpp/regression/I-NOP-01.out32 | 8 ---- src/test/cpp/regression/I-OR-01.out32 | 11 ------ src/test/cpp/regression/I-ORI-01.out32 | 11 ------ src/test/cpp/regression/I-RF_size-01.out32 | 9 ----- src/test/cpp/regression/I-RF_width-01.out32 | 8 ---- src/test/cpp/regression/I-RF_x0-01.out32 | 3 -- src/test/cpp/regression/I-SB-01.out32 | 4 -- src/test/cpp/regression/I-SH-01.out32 | 4 -- src/test/cpp/regression/I-SLL-01.out32 | 11 ------ src/test/cpp/regression/I-SLLI-01.out32 | 10 ----- src/test/cpp/regression/I-SLT-01.out32 | 12 ------ src/test/cpp/regression/I-SLTI-01.out32 | 11 ------ src/test/cpp/regression/I-SLTIU-01.out32 | 11 ------ src/test/cpp/regression/I-SLTU-01.out32 | 12 ------ src/test/cpp/regression/I-SRA-01.out32 | 11 ------ src/test/cpp/regression/I-SRAI-01.out32 | 10 ----- src/test/cpp/regression/I-SRL-01.out32 | 11 ------ src/test/cpp/regression/I-SRLI-01.out32 | 10 ----- src/test/cpp/regression/I-SUB-01.out32 | 11 ------ src/test/cpp/regression/I-SW-01.out32 | 4 -- src/test/cpp/regression/I-XOR-01.out32 | 11 ------ src/test/cpp/regression/I-XORI-01.out32 | 11 ------ src/test/cpp/regression/main.cpp | 2 +- 59 files changed, 26 insertions(+), 429 deletions(-) delete mode 100644 src/test/cpp/regression/I-ADD-01.out32 delete mode 100644 src/test/cpp/regression/I-ADDI-01.out32 delete mode 100644 src/test/cpp/regression/I-AND-01.out32 delete mode 100644 src/test/cpp/regression/I-ANDI-01.out32 delete mode 100644 src/test/cpp/regression/I-AUIPC-01.out32 delete mode 100644 src/test/cpp/regression/I-BEQ-01.out32 delete mode 100644 src/test/cpp/regression/I-BGE-01.out32 delete mode 100644 src/test/cpp/regression/I-BGEU-01.out32 delete mode 100644 src/test/cpp/regression/I-BLT-01.out32 delete mode 100644 src/test/cpp/regression/I-BLTU-01.out32 delete mode 100644 src/test/cpp/regression/I-BNE-01.out32 delete mode 100644 src/test/cpp/regression/I-CSRRC-01.out32 delete mode 100644 src/test/cpp/regression/I-CSRRCI-01.out32 delete mode 100644 src/test/cpp/regression/I-CSRRS-01.out32 delete mode 100644 src/test/cpp/regression/I-CSRRSI-01.out32 delete mode 100644 src/test/cpp/regression/I-CSRRW-01.out32 delete mode 100644 src/test/cpp/regression/I-CSRRWI-01.out32 delete mode 100644 src/test/cpp/regression/I-DELAY_SLOTS-01.out32 delete mode 100644 src/test/cpp/regression/I-EBREAK-01.out32 delete mode 100644 src/test/cpp/regression/I-ECALL-01.out32 delete mode 100644 src/test/cpp/regression/I-ENDIANESS-01.out32 delete mode 100644 src/test/cpp/regression/I-FENCE.I-01.out32 delete mode 100644 src/test/cpp/regression/I-IO.out32 delete mode 100644 src/test/cpp/regression/I-JAL-01.out32 delete mode 100644 src/test/cpp/regression/I-JALR-01.out32 delete mode 100644 src/test/cpp/regression/I-LB-01.out32 delete mode 100644 src/test/cpp/regression/I-LBU-01.out32 delete mode 100644 src/test/cpp/regression/I-LH-01.out32 delete mode 100644 src/test/cpp/regression/I-LHU-01.out32 delete mode 100644 src/test/cpp/regression/I-LUI-01.out32 delete mode 100644 src/test/cpp/regression/I-LW-01.out32 delete mode 100644 src/test/cpp/regression/I-MISALIGN_JMP-01.out32 delete mode 100644 src/test/cpp/regression/I-MISALIGN_LDST-01.out32 delete mode 100644 src/test/cpp/regression/I-NOP-01.out32 delete mode 100644 src/test/cpp/regression/I-OR-01.out32 delete mode 100644 src/test/cpp/regression/I-ORI-01.out32 delete mode 100644 src/test/cpp/regression/I-RF_size-01.out32 delete mode 100644 src/test/cpp/regression/I-RF_width-01.out32 delete mode 100644 src/test/cpp/regression/I-RF_x0-01.out32 delete mode 100644 src/test/cpp/regression/I-SB-01.out32 delete mode 100644 src/test/cpp/regression/I-SH-01.out32 delete mode 100644 src/test/cpp/regression/I-SLL-01.out32 delete mode 100644 src/test/cpp/regression/I-SLLI-01.out32 delete mode 100644 src/test/cpp/regression/I-SLT-01.out32 delete mode 100644 src/test/cpp/regression/I-SLTI-01.out32 delete mode 100644 src/test/cpp/regression/I-SLTIU-01.out32 delete mode 100644 src/test/cpp/regression/I-SLTU-01.out32 delete mode 100644 src/test/cpp/regression/I-SRA-01.out32 delete mode 100644 src/test/cpp/regression/I-SRAI-01.out32 delete mode 100644 src/test/cpp/regression/I-SRL-01.out32 delete mode 100644 src/test/cpp/regression/I-SRLI-01.out32 delete mode 100644 src/test/cpp/regression/I-SUB-01.out32 delete mode 100644 src/test/cpp/regression/I-SW-01.out32 delete mode 100644 src/test/cpp/regression/I-XOR-01.out32 delete mode 100644 src/test/cpp/regression/I-XORI-01.out32 diff --git a/.gitignore b/.gitignore index 3c575c5..eaab2e7 100644 --- a/.gitignore +++ b/.gitignore @@ -46,3 +46,4 @@ obj_dir simWorkspace/ tmp/ /archive.tar.gz +*.out32 \ No newline at end of file diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index c5f0265..70645ab 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -35,7 +35,7 @@ object TestsWorkspace { resetVector = 0x80000000l, cmdForkOnSecondStage = false, cmdForkPersistence = false, - prediction = NONE, + prediction = STATIC, historyRamSizeLog2 = 10, catchAccessFault = true, compressedGen = false, diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index 2ce64a1..b92d3b4 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -110,14 +110,14 @@ class BranchPlugin(earlyBranch : Boolean, decoderService.addDefault(BRANCH_CTRL, BranchCtrlEnum.INC) val rvc = pipeline(RVC_GEN) decoderService.add(List( - JAL(rvc) -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JAL, ALU_CTRL -> AluCtrlEnum.ADD_SUB)), - JALR -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JALR, ALU_CTRL -> AluCtrlEnum.ADD_SUB, RS1_USE -> True)), - BEQ(rvc) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B)), - BNE(rvc) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B)), - BLT(rvc) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> False)), - BGE(rvc) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> False)), - BLTU(rvc) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> True)), - BGEU(rvc) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> True)) + JAL(true) -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JAL, ALU_CTRL -> AluCtrlEnum.ADD_SUB)), + JALR -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JALR, ALU_CTRL -> AluCtrlEnum.ADD_SUB, RS1_USE -> True)), + BEQ(true) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B)), + BNE(true) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B)), + BLT(true) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> False)), + BGE(true) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> False)), + BLTU(true) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> True)), + BGEU(true) -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> True)) )) if(fenceiGenAsAJump) { @@ -200,7 +200,7 @@ class BranchPlugin(earlyBranch : Boolean, } if(catchAddressMisaligned) { - branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && (if(pipeline(RVC_GEN)) jumpInterface.payload(0 downto 0) =/= 0 else jumpInterface.payload(1 downto 0) =/= 0) + branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && (jumpInterface.payload((if(pipeline(RVC_GEN)) 0 else 1) downto 0) =/= 0) branchExceptionPort.code := 0 branchExceptionPort.badAddr := jumpInterface.payload } @@ -217,7 +217,7 @@ class BranchPlugin(earlyBranch : Boolean, decode plug new Area { import decode._ - insert(PREDICTION_HAD_BRANCHED) := decodePrediction.cmd.hadBranch + insert(PREDICTION_HAD_BRANCHED) := (if(fenceiGenAsAJump) decodePrediction.cmd.hadBranch && !decode.input(IS_FENCEI) else decodePrediction.cmd.hadBranch) } //Do real branch calculation @@ -239,10 +239,16 @@ class BranchPlugin(earlyBranch : Boolean, ) ) - insert(BRANCH_DO) := input(PREDICTION_HAD_BRANCHED) =/= input(BRANCH_COND_RESULT) + val imm = IMM(input(INSTRUCTION)) + val missAlignedTarget = if(pipeline(RVC_GEN)) False else (input(BRANCH_COND_RESULT) && input(BRANCH_CTRL).mux( + BranchCtrlEnum.JALR -> (imm.i_sext(1) ^ input(RS1)(1)), + BranchCtrlEnum.JAL -> imm.j_sext(1), + default -> imm.b_sext(1) + )) + + insert(BRANCH_DO) := input(PREDICTION_HAD_BRANCHED) =/= input(BRANCH_COND_RESULT) || missAlignedTarget //Calculation of the branch target / correction - val imm = IMM(input(INSTRUCTION)) val branch_src1,branch_src2 = UInt(32 bits) switch(input(BRANCH_CTRL)){ is(BranchCtrlEnum.JALR){ @@ -251,7 +257,10 @@ class BranchPlugin(earlyBranch : Boolean, } default{ branch_src1 := input(PC) - branch_src2 := (input(PREDICTION_HAD_BRANCHED) ? (if(pipeline(RVC_GEN)) Mux(input(IS_RVC), B(2), B(4)) else B(4)).resized | imm.b_sext).asUInt + branch_src2 := ((input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt + when(input(PREDICTION_HAD_BRANCHED) && ! missAlignedTarget){ + branch_src2 := (if(pipeline(RVC_GEN)) Mux(input(IS_RVC), B(2), B(4)) else B(4)).asUInt.resized + } } } val branchAdder = branch_src1 + branch_src2 @@ -271,7 +280,7 @@ class BranchPlugin(earlyBranch : Boolean, } if(catchAddressMisaligned) { - val unalignedJump = input(BRANCH_DO) && (if(pipeline(RVC_GEN)) input(BRANCH_CALC)(0 downto 0) =/= 0 else input(BRANCH_CALC)(1 downto 0) =/= 0) + val unalignedJump = input(BRANCH_DO) && (input(BRANCH_CALC)((if(pipeline(RVC_GEN)) 0 else 1) downto 0) =/= 0) branchExceptionPort.valid := arbitration.isValid && unalignedJump branchExceptionPort.code := 0 branchExceptionPort.badAddr := input(BRANCH_CALC) //pipeline.stages(pipeline.indexOf(branchStage)-1).input diff --git a/src/test/cpp/regression/I-ADD-01.out32 b/src/test/cpp/regression/I-ADD-01.out32 deleted file mode 100644 index 2a85b7a..0000000 --- a/src/test/cpp/regression/I-ADD-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -ffffffff000000010000000000000000 -0000000100000001800000007fffffff -80000001800000000000000000000002 -fffffffe00000000ffffffffffffffff -7fffffff7fffffff7fffffff7ffffffe -fffffffffffffffe7ffffffe80000000 -7fffffff800000018000000080000000 -0000abcd0000000100000000ffffffff -0000abd10000abd00000abcf0000abce -00000000000000000000abd30000abd2 -36925814369258143692581400000000 diff --git a/src/test/cpp/regression/I-ADDI-01.out32 b/src/test/cpp/regression/I-ADDI-01.out32 deleted file mode 100644 index d8a4aa9..0000000 --- a/src/test/cpp/regression/I-ADDI-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -ffffffff000007ff0000000100000000 -0000000200000001fffff80000000000 -fffff801000000010000000000000800 -fffffffe000007fe00000000ffffffff -800000007ffffffffffff7ffffffffff -7ffff7ff7fffffff7ffffffe800007fe -7fffffff800007ff8000000180000000 -0000abce0000abcd7ffff80080000000 -0000abd20000abd10000abd00000abcf -0000000100000000000000000000abd3 -36925814369258143692581436925814 diff --git a/src/test/cpp/regression/I-AND-01.out32 b/src/test/cpp/regression/I-AND-01.out32 deleted file mode 100644 index 36062e1..0000000 --- a/src/test/cpp/regression/I-AND-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -00000000000000000000000000000000 -00000000000000010000000000000000 -00000000000000010000000100000001 -ffffffff0000000100000000ffffffff -000000007fffffff800000007fffffff -000000007fffffff7fffffff00000001 -80000000000000000000000080000000 -abcdffff0000007f8000000000000000 -0000000f0000001f0000003f0000007f -00000000000000000000000300000007 -36925814369258143692581400000000 diff --git a/src/test/cpp/regression/I-ANDI-01.out32 b/src/test/cpp/regression/I-ANDI-01.out32 deleted file mode 100644 index 678ea1b..0000000 --- a/src/test/cpp/regression/I-ANDI-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -00000000000000000000000000000000 -00000001000000010000000000000000 -00000000000000000000000100000001 -ffffffff000007ff00000001ffffffff -000000017ffffffffffff80000000000 -7ffff800000000007fffffff000007ff -80000000000000000000000080000000 -0000007fabcdffff8000000000000000 -000000070000000f0000001f0000003f -00000000000000000000000000000003 -36925814369258143692581436925814 diff --git a/src/test/cpp/regression/I-AUIPC-01.out32 b/src/test/cpp/regression/I-AUIPC-01.out32 deleted file mode 100644 index aed7e49..0000000 --- a/src/test/cpp/regression/I-AUIPC-01.out32 +++ /dev/null @@ -1,4 +0,0 @@ -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 diff --git a/src/test/cpp/regression/I-BEQ-01.out32 b/src/test/cpp/regression/I-BEQ-01.out32 deleted file mode 100644 index 55bcb00..0000000 --- a/src/test/cpp/regression/I-BEQ-01.out32 +++ /dev/null @@ -1,10 +0,0 @@ -ffffffff000000010000000000000000 -000000010000001e800000007fffffff -7fffffffffffffff0000000100000000 -00000000ffffffff0000001d80000000 -800000007fffffffffffffff00000001 -00000001000000007fffffff0000001b -00000017800000007fffffffffffffff -ffffffff000000010000000080000000 -000003de0000000f800000007fffffff -0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-BGE-01.out32 b/src/test/cpp/regression/I-BGE-01.out32 deleted file mode 100644 index 4d90737..0000000 --- a/src/test/cpp/regression/I-BGE-01.out32 +++ /dev/null @@ -1,10 +0,0 @@ -ffffffff000000010000000000000000 -000000010000000a800000007fffffff -7fffffffffffffff0000000100000000 -00000000ffffffff0000000880000000 -800000007fffffffffffffff00000001 -00000001000000007fffffff0000000b -00000000800000007fffffffffffffff -ffffffff000000010000000080000000 -000001540000000f800000007fffffff -0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-BGEU-01.out32 b/src/test/cpp/regression/I-BGEU-01.out32 deleted file mode 100644 index ec77619..0000000 --- a/src/test/cpp/regression/I-BGEU-01.out32 +++ /dev/null @@ -1,10 +0,0 @@ -ffffffff000000010000000000000000 -000000010000001e800000007fffffff -7fffffffffffffff0000000100000000 -00000000ffffffff0000001c80000000 -800000007fffffffffffffff00000001 -00000001000000007fffffff00000000 -00000014800000007fffffffffffffff -ffffffff000000010000000080000000 -000003c000000004800000007fffffff -0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-BLT-01.out32 b/src/test/cpp/regression/I-BLT-01.out32 deleted file mode 100644 index 81618ad..0000000 --- a/src/test/cpp/regression/I-BLT-01.out32 +++ /dev/null @@ -1,10 +0,0 @@ -ffffffff000000010000000000000000 -0000000100000015800000007fffffff -7fffffffffffffff0000000100000000 -00000000ffffffff0000001780000000 -800000007fffffffffffffff00000001 -00000001000000007fffffff00000014 -0000001f800000007fffffffffffffff -ffffffff000000010000000080000000 -000002ab00000010800000007fffffff -0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-BLTU-01.out32 b/src/test/cpp/regression/I-BLTU-01.out32 deleted file mode 100644 index d4c8e1f..0000000 --- a/src/test/cpp/regression/I-BLTU-01.out32 +++ /dev/null @@ -1,10 +0,0 @@ -ffffffff000000010000000000000000 -0000000100000001800000007fffffff -7fffffffffffffff0000000100000000 -00000000ffffffff0000000380000000 -800000007fffffffffffffff00000001 -00000001000000007fffffff0000001f -0000000b800000007fffffffffffffff -ffffffff000000010000000080000000 -0000003f0000001b800000007fffffff -0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-BNE-01.out32 b/src/test/cpp/regression/I-BNE-01.out32 deleted file mode 100644 index 7816951..0000000 --- a/src/test/cpp/regression/I-BNE-01.out32 +++ /dev/null @@ -1,10 +0,0 @@ -ffffffff000000010000000000000000 -0000000100000001800000007fffffff -7fffffffffffffff0000000100000000 -00000000ffffffff0000000280000000 -800000007fffffffffffffff00000001 -00000001000000007fffffff00000004 -00000008800000007fffffffffffffff -ffffffff000000010000000080000000 -0000002100000010800000007fffffff -0fedcba9876543219abcdef000000000 diff --git a/src/test/cpp/regression/I-CSRRC-01.out32 b/src/test/cpp/regression/I-CSRRC-01.out32 deleted file mode 100644 index f72c9e7..0000000 --- a/src/test/cpp/regression/I-CSRRC-01.out32 +++ /dev/null @@ -1,6 +0,0 @@ -800f0000fffffffffffffffe00000000 -fffffffeffffffff000000007fffffff -00000000000f0000800f0000fffffffe -ffffffff00000000ffffffffedcba987 -0000000042726e6f00000000ffffffff -49c1a90369c7ad8bfffffffff7ff8818 diff --git a/src/test/cpp/regression/I-CSRRCI-01.out32 b/src/test/cpp/regression/I-CSRRCI-01.out32 deleted file mode 100644 index 9b6918d..0000000 --- a/src/test/cpp/regression/I-CSRRCI-01.out32 +++ /dev/null @@ -1,4 +0,0 @@ -ffffffe0fffffffffffffffe00000000 -fffffffffffffffffffffff0ffffffef -ffffffe0ffffffe0fffffffefffffffe -3216549000000000ffffffffffffffe0 diff --git a/src/test/cpp/regression/I-CSRRS-01.out32 b/src/test/cpp/regression/I-CSRRS-01.out32 deleted file mode 100644 index 126f7b6..0000000 --- a/src/test/cpp/regression/I-CSRRS-01.out32 +++ /dev/null @@ -1,6 +0,0 @@ -7ff0ffff000000000000000100000000 -0000000100000000ffffffff80000000 -fffffffffff0ffff7ff0ffff00000001 -00000000123456780000000012345678 -0000000042726e6f0000000012345678 -b63e56fc9638527400000000f7ff8818 diff --git a/src/test/cpp/regression/I-CSRRSI-01.out32 b/src/test/cpp/regression/I-CSRRSI-01.out32 deleted file mode 100644 index 1957fea..0000000 --- a/src/test/cpp/regression/I-CSRRSI-01.out32 +++ /dev/null @@ -1,4 +0,0 @@ -0000001f000000000000000100000000 -00000000000000000000000f00000010 -0000001f0000001f0000000100000001 -321654983216549f000000000000001f diff --git a/src/test/cpp/regression/I-CSRRW-01.out32 b/src/test/cpp/regression/I-CSRRW-01.out32 deleted file mode 100644 index 937da08..0000000 --- a/src/test/cpp/regression/I-CSRRW-01.out32 +++ /dev/null @@ -1,4 +0,0 @@ -ffffffff000000000000000100000000 -9abcdef012345678800000007fffffff -00000000000000009abcdef012345678 -32165498963852741472583600000000 diff --git a/src/test/cpp/regression/I-CSRRWI-01.out32 b/src/test/cpp/regression/I-CSRRWI-01.out32 deleted file mode 100644 index ebc2adc..0000000 --- a/src/test/cpp/regression/I-CSRRWI-01.out32 +++ /dev/null @@ -1,2 +0,0 @@ -00000000000000010000000000000000 -00000000000000100000000f0000001f diff --git a/src/test/cpp/regression/I-DELAY_SLOTS-01.out32 b/src/test/cpp/regression/I-DELAY_SLOTS-01.out32 deleted file mode 100644 index 653c12d..0000000 --- a/src/test/cpp/regression/I-DELAY_SLOTS-01.out32 +++ /dev/null @@ -1,2 +0,0 @@ -44444444333333332222222211111111 -88888888777777776666666655555555 diff --git a/src/test/cpp/regression/I-EBREAK-01.out32 b/src/test/cpp/regression/I-EBREAK-01.out32 deleted file mode 100644 index b6cfdac..0000000 --- a/src/test/cpp/regression/I-EBREAK-01.out32 +++ /dev/null @@ -1 +0,0 @@ -00000000000000001111111100000003 diff --git a/src/test/cpp/regression/I-ECALL-01.out32 b/src/test/cpp/regression/I-ECALL-01.out32 deleted file mode 100644 index ee60be8..0000000 --- a/src/test/cpp/regression/I-ECALL-01.out32 +++ /dev/null @@ -1 +0,0 @@ -0000000000000000111111110000000b diff --git a/src/test/cpp/regression/I-ENDIANESS-01.out32 b/src/test/cpp/regression/I-ENDIANESS-01.out32 deleted file mode 100644 index 4d78561..0000000 --- a/src/test/cpp/regression/I-ENDIANESS-01.out32 +++ /dev/null @@ -1,2 +0,0 @@ -00000089000001230000456701234567 -00000001000000230000004500000067 diff --git a/src/test/cpp/regression/I-FENCE.I-01.out32 b/src/test/cpp/regression/I-FENCE.I-01.out32 deleted file mode 100644 index ce9b712..0000000 --- a/src/test/cpp/regression/I-FENCE.I-01.out32 +++ /dev/null @@ -1 +0,0 @@ -001101b3000000420000001200000030 diff --git a/src/test/cpp/regression/I-IO.out32 b/src/test/cpp/regression/I-IO.out32 deleted file mode 100644 index 2a85b7a..0000000 --- a/src/test/cpp/regression/I-IO.out32 +++ /dev/null @@ -1,11 +0,0 @@ -ffffffff000000010000000000000000 -0000000100000001800000007fffffff -80000001800000000000000000000002 -fffffffe00000000ffffffffffffffff -7fffffff7fffffff7fffffff7ffffffe -fffffffffffffffe7ffffffe80000000 -7fffffff800000018000000080000000 -0000abcd0000000100000000ffffffff -0000abd10000abd00000abcf0000abce -00000000000000000000abd30000abd2 -36925814369258143692581400000000 diff --git a/src/test/cpp/regression/I-JAL-01.out32 b/src/test/cpp/regression/I-JAL-01.out32 deleted file mode 100644 index e29875e..0000000 --- a/src/test/cpp/regression/I-JAL-01.out32 +++ /dev/null @@ -1,5 +0,0 @@ -9abcdef0000000001234567800000000 -22222222111111110fedcba987654321 -00000000555555554444444433333333 -88888888777777776666666600000000 -0000000000000000aaaaaaaa99999999 diff --git a/src/test/cpp/regression/I-JALR-01.out32 b/src/test/cpp/regression/I-JALR-01.out32 deleted file mode 100644 index ed25991..0000000 --- a/src/test/cpp/regression/I-JALR-01.out32 +++ /dev/null @@ -1,6 +0,0 @@ -9abcdef0000000001234567800000000 -22222222111111110fedcba987654321 -00000000555555554444444433333333 -88888888777777776666666600000000 -0000000000000000aaaaaaaa99999999 -44444444333333332222222211111111 diff --git a/src/test/cpp/regression/I-LB-01.out32 b/src/test/cpp/regression/I-LB-01.out32 deleted file mode 100644 index 9d33c9e..0000000 --- a/src/test/cpp/regression/I-LB-01.out32 +++ /dev/null @@ -1,9 +0,0 @@ -00000011fffffff1fffffff200000022 -fffffff30000003300000044fffffff4 -00000055fffffff5fffffff600000066 -fffffff700000077ffffff88fffffff8 -ffffff99000000090000000affffffaa -0000000bffffffbbffffffcc0000000c -ffffffdd0000000d0000000effffffee -0000000fffffffff00000000fffffff0 -ffffff9800000010fffffff000000000 diff --git a/src/test/cpp/regression/I-LBU-01.out32 b/src/test/cpp/regression/I-LBU-01.out32 deleted file mode 100644 index 8fc7501..0000000 --- a/src/test/cpp/regression/I-LBU-01.out32 +++ /dev/null @@ -1,9 +0,0 @@ -00000011000000f1000000f200000022 -000000f30000003300000044000000f4 -00000055000000f5000000f600000066 -000000f70000007700000088000000f8 -00000099000000090000000a000000aa -0000000b000000bb000000cc0000000c -000000dd0000000d0000000e000000ee -0000000f000000ff00000000000000f0 -0000009800000010000000f000000000 diff --git a/src/test/cpp/regression/I-LH-01.out32 b/src/test/cpp/regression/I-LH-01.out32 deleted file mode 100644 index 7d40f26..0000000 --- a/src/test/cpp/regression/I-LH-01.out32 +++ /dev/null @@ -1,5 +0,0 @@ -fffff333000044f4000011f1fffff222 -fffff777ffff88f8000055f5fffff666 -00000bbbffffcc0cffff990900000aaa -00000fff000000f0ffffdd0d00000eee -ffffba9800003210ffffdef000000000 diff --git a/src/test/cpp/regression/I-LHU-01.out32 b/src/test/cpp/regression/I-LHU-01.out32 deleted file mode 100644 index 0a03139..0000000 --- a/src/test/cpp/regression/I-LHU-01.out32 +++ /dev/null @@ -1,5 +0,0 @@ -0000f333000044f4000011f10000f222 -0000f777000088f8000055f50000f666 -00000bbb0000cc0c0000990900000aaa -00000fff000000f00000dd0d00000eee -0000ba98000032100000def000000000 diff --git a/src/test/cpp/regression/I-LUI-01.out32 b/src/test/cpp/regression/I-LUI-01.out32 deleted file mode 100644 index fe029d6..0000000 --- a/src/test/cpp/regression/I-LUI-01.out32 +++ /dev/null @@ -1,4 +0,0 @@ -7ffff000fffff0000000100000000000 -000000007ffff0008000000080000000 -1234567842726e6ffffff00000001000 -9abcdef01234567842726e6f9abcdef0 diff --git a/src/test/cpp/regression/I-LW-01.out32 b/src/test/cpp/regression/I-LW-01.out32 deleted file mode 100644 index 37a6a89..0000000 --- a/src/test/cpp/regression/I-LW-01.out32 +++ /dev/null @@ -1,3 +0,0 @@ -f77788f855f5f666f33344f411f1f222 -0fff00f0dd0d0eee0bbbcc0c99090aaa -fedcba98765432109abcdef000000000 diff --git a/src/test/cpp/regression/I-MISALIGN_JMP-01.out32 b/src/test/cpp/regression/I-MISALIGN_JMP-01.out32 deleted file mode 100644 index e69de29..0000000 diff --git a/src/test/cpp/regression/I-MISALIGN_LDST-01.out32 b/src/test/cpp/regression/I-MISALIGN_LDST-01.out32 deleted file mode 100644 index 1657846..0000000 --- a/src/test/cpp/regression/I-MISALIGN_LDST-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -91a1b1c191a1b1c191a1b1c191a1b1c1 -00000004000000020000000400000001 -fffff202fffff2020000000400000003 -0000f2020000f202ffffd2e2ffffd2e2 -00000004000000010000d2e20000d2e2 -00000004000000010000000400000003 -99999999000000000000000400000003 -00000006000000019999999999999999 -00000006000000030000000600000002 -99999999000099999999999999990000 -00000006000000030000000600000001 diff --git a/src/test/cpp/regression/I-NOP-01.out32 b/src/test/cpp/regression/I-NOP-01.out32 deleted file mode 100644 index 5b827c0..0000000 --- a/src/test/cpp/regression/I-NOP-01.out32 +++ /dev/null @@ -1,8 +0,0 @@ -00000004000000030000000200000000 -00000008000000070000000600000005 -0000000c0000000b0000000a00000009 -000000100000000f0000000e0000000d -00000014000000130000001200000011 -00000018000000170000001600000015 -0000001c0000001b0000001a00000019 -000000180000001f0000001e0000001d diff --git a/src/test/cpp/regression/I-OR-01.out32 b/src/test/cpp/regression/I-OR-01.out32 deleted file mode 100644 index f8724c7..0000000 --- a/src/test/cpp/regression/I-OR-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -ffffffff000000010000000000000000 -0000000100000001800000007fffffff -800000017fffffffffffffff00000001 -ffffffffffffffffffffffffffffffff -7fffffff7fffffffffffffffffffffff -ffffffff7fffffffffffffff7fffffff -ffffffff800000018000000080000000 -0000000d0000001080000000ffffffff -000000fd0000007d0000003d0000001d -0000000000000000fffff9fd000001fd -36925814369258143692581400000000 diff --git a/src/test/cpp/regression/I-ORI-01.out32 b/src/test/cpp/regression/I-ORI-01.out32 deleted file mode 100644 index f670807..0000000 --- a/src/test/cpp/regression/I-ORI-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -ffffffff000007ff0000000100000000 -0000000100000001fffff80000000000 -fffff80100000001ffffffff000007ff -ffffffffffffffffffffffffffffffff -7fffffff7fffffffffffffffffffffff -ffffffff7fffffffffffffff7fffffff -ffffffff800007ff8000000180000000 -0000001d0000000dfffff80080000000 -000001fd000000fd0000007d0000003d -000000010000000000000000fffff9fd -36925814369258143692581436925814 diff --git a/src/test/cpp/regression/I-RF_size-01.out32 b/src/test/cpp/regression/I-RF_size-01.out32 deleted file mode 100644 index 6c2de64..0000000 --- a/src/test/cpp/regression/I-RF_size-01.out32 +++ /dev/null @@ -1,9 +0,0 @@ -526973632d5620525633324900000000 -4d696c616e204e6f73746572736b7920 -286e6f73746572736b7940636f646173 -69702e636f6d292c20526164656b2048 -616a656b202868616a656b40636f6461 -7369702e636f6d292e204c6561766520 -7573206d65737361676520696620796f -7520726561642074686973203a290d0a -526973632d5620525633324900000000 diff --git a/src/test/cpp/regression/I-RF_width-01.out32 b/src/test/cpp/regression/I-RF_width-01.out32 deleted file mode 100644 index 046d639..0000000 --- a/src/test/cpp/regression/I-RF_width-01.out32 +++ /dev/null @@ -1,8 +0,0 @@ -80000000800000008000000000000000 -80000000800000008000000080000000 -80000000800000008000000080000000 -80000000800000008000000080000000 -80000000800000008000000080000000 -80000000800000008000000080000000 -80000000800000008000000080000000 -80000000800000008000000080000000 diff --git a/src/test/cpp/regression/I-RF_x0-01.out32 b/src/test/cpp/regression/I-RF_x0-01.out32 deleted file mode 100644 index a0b36af..0000000 --- a/src/test/cpp/regression/I-RF_x0-01.out32 +++ /dev/null @@ -1,3 +0,0 @@ -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 diff --git a/src/test/cpp/regression/I-SB-01.out32 b/src/test/cpp/regression/I-SB-01.out32 deleted file mode 100644 index 288281f..0000000 --- a/src/test/cpp/regression/I-SB-01.out32 +++ /dev/null @@ -1,4 +0,0 @@ -000000f800000066000000f4aaaabb22 -0fff00f0dd0d0eee0bbbcc0c000000aa -00000010000000f00000004487654300 -000000630000003600000036000000ef diff --git a/src/test/cpp/regression/I-SH-01.out32 b/src/test/cpp/regression/I-SH-01.out32 deleted file mode 100644 index 8f22e2d..0000000 --- a/src/test/cpp/regression/I-SH-01.out32 +++ /dev/null @@ -1,4 +0,0 @@ -000088f80000f666000044f4aaaaf222 -0fff00f0dd0d0eee0bbbcc0c00000aaa -000032100000def00000334487650000 -0000496300005836000058360000cdef diff --git a/src/test/cpp/regression/I-SLL-01.out32 b/src/test/cpp/regression/I-SLL-01.out32 deleted file mode 100644 index 18bb825..0000000 --- a/src/test/cpp/regression/I-SLL-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -00000000000000000000000000000000 -00000002000000010000000000000000 -00010000000000018000000000008000 -80000000ffff8000fffffffeffffffff -fffffffe7fffffffffff0000ffffffff -ffff00007fffffff80000000ffff8000 -00000000000000000000000080000000 -579bde20abcdef100000000080000000 -79bde200bcdef1005e6f7880af37bc40 -000000000000000000000000f37bc400 -80000000a19080000eca864287654321 diff --git a/src/test/cpp/regression/I-SLLI-01.out32 b/src/test/cpp/regression/I-SLLI-01.out32 deleted file mode 100644 index 25818ac..0000000 --- a/src/test/cpp/regression/I-SLLI-01.out32 +++ /dev/null @@ -1,10 +0,0 @@ -00000000000000000000000000000000 -00000002000000010000000000000000 -00010000000000018000000000008000 -80000000ffff8000fffffffeffffffff -fffffffe7fffffffffff0000ffffffff -ffff00007fffffff80000000ffff8000 -00000000000000000000000080000000 -579bde20abcdef100000000080000000 -79bde200bcdef1005e6f7880af37bc40 -000000000000000000000000f37bc400 diff --git a/src/test/cpp/regression/I-SLT-01.out32 b/src/test/cpp/regression/I-SLT-01.out32 deleted file mode 100644 index ffc1108..0000000 --- a/src/test/cpp/regression/I-SLT-01.out32 +++ /dev/null @@ -1,12 +0,0 @@ -00000000000000010000000100000000 -00000000000000010000000000000000 -00000000000000000000000000000001 -000000000000000100000001ffffffff -000000007fffffff0000000000000001 -00000000000000000000000000000000 -00000001000000010000000180000000 -ffffffff000000000000000000000001 -00000000000000010000000100000001 -00000000000000000000000000000000 -00000001000000010000000000000001 -00000001000000000000000100000000 diff --git a/src/test/cpp/regression/I-SLTI-01.out32 b/src/test/cpp/regression/I-SLTI-01.out32 deleted file mode 100644 index ab1cdda..0000000 --- a/src/test/cpp/regression/I-SLTI-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -00000000000000010000000100000000 -00000000000000010000000000000000 -00000000000000000000000000000001 -000000000000000100000001ffffffff -000000007fffffff0000000000000001 -00000000000000000000000000000000 -00000001000000010000000180000000 -00000000ffffffff0000000100000001 -00000000000000010000000100000000 -00000001000000000000000000000000 -00000001000000000000000100000000 diff --git a/src/test/cpp/regression/I-SLTIU-01.out32 b/src/test/cpp/regression/I-SLTIU-01.out32 deleted file mode 100644 index fae3854..0000000 --- a/src/test/cpp/regression/I-SLTIU-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -00000001000000010000000100000000 -00000000000000010000000100000000 -00000001000000000000000100000001 -000000000000000000000000ffffffff -000000007fffffff0000000000000000 -00000001000000000000000100000000 -00000001000000000000000080000000 -00000000000000010000000100000000 -00000001000000010000000100000000 -00000001000000000000000100000000 -00000001000000000000000100000000 diff --git a/src/test/cpp/regression/I-SLTU-01.out32 b/src/test/cpp/regression/I-SLTU-01.out32 deleted file mode 100644 index aa67d8f..0000000 --- a/src/test/cpp/regression/I-SLTU-01.out32 +++ /dev/null @@ -1,12 +0,0 @@ -00000001000000010000000100000000 -00000000000000010000000100000000 -00000001000000000000000100000001 -000000000000000000000000ffffffff -000000007fffffff0000000000000000 -00000001000000000000000100000000 -00000001000000000000000080000000 -00000001000000000000000000000000 -000000010000000100000001ffffffff -00000000000000000000000100000000 -00000001000000000000000000000000 -00000001000000000000000100000000 diff --git a/src/test/cpp/regression/I-SRA-01.out32 b/src/test/cpp/regression/I-SRA-01.out32 deleted file mode 100644 index 5338082..0000000 --- a/src/test/cpp/regression/I-SRA-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -00000000000000000000000000000000 -00000000000000010000000000000000 -00000000000000010000000000000000 -ffffffffffffffffffffffffffffffff -3fffffff7fffffffffffffffffffffff -00007fff7fffffff000000000000ffff -ffffffffffff0000c000000080000000 -d5e6f788abcdef10ffff800080000000 -fd5e6f78fabcdef1f579bde2eaf37bc4 -000000000000000000000000feaf37bc -ffffffffffff0ecac3b2a19087654321 diff --git a/src/test/cpp/regression/I-SRAI-01.out32 b/src/test/cpp/regression/I-SRAI-01.out32 deleted file mode 100644 index adbf5bf..0000000 --- a/src/test/cpp/regression/I-SRAI-01.out32 +++ /dev/null @@ -1,10 +0,0 @@ -00000000000000000000000000000000 -00000000000000010000000000000000 -00000000000000010000000000000000 -ffffffffffffffffffffffffffffffff -3fffffff7fffffffffffffffffffffff -00007fff7fffffff000000000000ffff -ffffffffffff0000c000000080000000 -d5e6f788abcdef10ffff800080000000 -fd5e6f78fabcdef1f579bde2eaf37bc4 -000000000000000000000000feaf37bc diff --git a/src/test/cpp/regression/I-SRL-01.out32 b/src/test/cpp/regression/I-SRL-01.out32 deleted file mode 100644 index baa9cdf..0000000 --- a/src/test/cpp/regression/I-SRL-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -00000000000000000000000000000000 -00000000000000010000000000000000 -00000000000000010000000000000000 -000000010001ffff7fffffffffffffff -3fffffff7fffffff0000ffffffffffff -00007fff7fffffff000000000000ffff -00000001000100004000000080000000 -55e6f788abcdef100000800080000000 -055e6f780abcdef11579bde22af37bc4 -00000000000000000000000002af37bc -0000000100010eca43b2a19087654321 diff --git a/src/test/cpp/regression/I-SRLI-01.out32 b/src/test/cpp/regression/I-SRLI-01.out32 deleted file mode 100644 index 8cf21d8..0000000 --- a/src/test/cpp/regression/I-SRLI-01.out32 +++ /dev/null @@ -1,10 +0,0 @@ -00000000000000000000000000000000 -00000000000000010000000000000000 -00000000000000010000000000000000 -000000010001ffff7fffffffffffffff -3fffffff7fffffff0000ffffffffffff -00007fff7fffffff000000000000ffff -00000001000100004000000080000000 -55e6f788abcdef100000800080000000 -055e6f780abcdef11579bde22af37bc4 -00000000000000000000000002af37bc diff --git a/src/test/cpp/regression/I-SUB-01.out32 b/src/test/cpp/regression/I-SUB-01.out32 deleted file mode 100644 index 9bd5c2f..0000000 --- a/src/test/cpp/regression/I-SUB-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -00000001ffffffff0000000000000000 -00000001000000018000000080000001 -80000001800000020000000200000000 -00000000fffffffeffffffffffffffff -7fffffff7fffffff7fffffff80000000 -ffffffff00000000800000007ffffffe -800000017fffffff8000000080000000 -0000abcd000000010000000000000001 -0000abc90000abca0000abcb0000abcc -00000000000000000000abc70000abc8 -c96da7ecc96da7ec3692581400000000 diff --git a/src/test/cpp/regression/I-SW-01.out32 b/src/test/cpp/regression/I-SW-01.out32 deleted file mode 100644 index 7ff05bd..0000000 --- a/src/test/cpp/regression/I-SW-01.out32 +++ /dev/null @@ -1,4 +0,0 @@ -f77788f855f5f666f33344f411f1f222 -0fff00f0dd0d0eee0bbbcc0c99090aaa -765432109abcdef01122334400000000 -25814963147258361472583689abcdef diff --git a/src/test/cpp/regression/I-XOR-01.out32 b/src/test/cpp/regression/I-XOR-01.out32 deleted file mode 100644 index 514db10..0000000 --- a/src/test/cpp/regression/I-XOR-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -ffffffff000000010000000000000000 -0000000100000001800000007fffffff -800000017ffffffefffffffe00000000 -00000000fffffffeffffffffffffffff -7fffffff7fffffff7fffffff80000000 -ffffffff00000000800000007ffffffe -7fffffff800000018000000080000000 -abcdffff0000007f00000000ffffffff -abcdffafabcdffa0abcdffbfabcdff80 -0000000000000000abcdffababcdffa8 -36925814369258143692581400000000 diff --git a/src/test/cpp/regression/I-XORI-01.out32 b/src/test/cpp/regression/I-XORI-01.out32 deleted file mode 100644 index dd8c914..0000000 --- a/src/test/cpp/regression/I-XORI-01.out32 +++ /dev/null @@ -1,11 +0,0 @@ -ffffffff000007ff0000000100000000 -0000000000000001fffff80000000000 -fffff80100000001fffffffe000007fe -00000000fffff800fffffffeffffffff -7ffffffe7fffffff000007ffffffffff -800007ff7fffffff800000007ffff800 -7fffffff800007ff8000000180000000 -abcdff80abcdffff7ffff80080000000 -abcdffa8abcdffafabcdffa0abcdffbf -000000010000000000000000abcdffab -36925814369258143692581436925814 diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 28dec0b..1d2e861 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -2571,7 +2571,7 @@ int main(int argc, char **argv, char **env) { #ifdef CSR #ifndef COMPRESSED uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u , - 8,6,9,6,10,4,11,4, 12,13,2, 14,2, 15,5,16,17,1 }; + 8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 }; redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).noInstructionReadCheck()->run(10e4);) #else uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u , From 8c25e73b9d9b3bcca1b151d5381088753a5a459a Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 11 Oct 2018 22:18:21 +0200 Subject: [PATCH 28/56] Fix DIV negative values divided by zero --- src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala index 71a519e..3dd668b 100644 --- a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala @@ -140,7 +140,7 @@ class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mu rs1 := twoComplement(rs1Extended, rs1NeedRevert).resized rs2 := twoComplement(execute.input(RS2), rs2NeedRevert) if(genMul) mul.counter.clear() - if(genDiv) div.needRevert := rs1NeedRevert ^ (rs2NeedRevert && !execute.input(INSTRUCTION)(13)) + if(genDiv) div.needRevert := (rs1NeedRevert ^ (rs2NeedRevert && !execute.input(INSTRUCTION)(13))) && !(execute.input(RS2) === 0 && execute.input(IS_RS2_SIGNED) && !execute.input(INSTRUCTION)(13)) if(genDiv) div.counter.clear() } } From 594f7a8bf22dcab4c228a963b997eb62fa89ba35 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 11 Oct 2018 22:19:17 +0200 Subject: [PATCH 29/56] Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test --- src/test/cpp/regression/main.cpp | 126 ++++- src/test/cpp/regression/makefile | 11 + src/test/resources/asm/C.ADD.elf.objdump | 334 +++++++++++++ src/test/resources/asm/C.ADDI.elf.objdump | 304 ++++++++++++ src/test/resources/asm/C.ADDI16SP.elf.objdump | 194 ++++++++ src/test/resources/asm/C.ADDI4SPN.elf.objdump | 194 ++++++++ src/test/resources/asm/C.AND.elf.objdump | 334 +++++++++++++ src/test/resources/asm/C.ANDI.elf.objdump | 304 ++++++++++++ src/test/resources/asm/C.BEQZ.elf.objdump | 215 ++++++++ src/test/resources/asm/C.BNEZ.elf.objdump | 205 ++++++++ src/test/resources/asm/C.J.elf.objdump | 211 ++++++++ src/test/resources/asm/C.JAL.elf.objdump | 211 ++++++++ src/test/resources/asm/C.JALR.elf.objdump | 220 +++++++++ src/test/resources/asm/C.JR.elf.objdump | 220 +++++++++ src/test/resources/asm/C.LI.elf.objdump | 304 ++++++++++++ src/test/resources/asm/C.LUI.elf.objdump | 304 ++++++++++++ src/test/resources/asm/C.LW.elf.objdump | 263 ++++++++++ src/test/resources/asm/C.LWSP.elf.objdump | 262 ++++++++++ src/test/resources/asm/C.MV.elf.objdump | 334 +++++++++++++ src/test/resources/asm/C.OR.elf.objdump | 334 +++++++++++++ src/test/resources/asm/C.SLLI.elf.objdump | 304 ++++++++++++ src/test/resources/asm/C.SRAI.elf.objdump | 304 ++++++++++++ src/test/resources/asm/C.SRLI.elf.objdump | 304 ++++++++++++ src/test/resources/asm/C.SUB.elf.objdump | 334 +++++++++++++ src/test/resources/asm/C.SW.elf.objdump | 281 +++++++++++ src/test/resources/asm/C.SWSP.elf.objdump | 280 +++++++++++ src/test/resources/asm/C.XOR.elf.objdump | 334 +++++++++++++ src/test/resources/asm/DIV.elf.objdump | 276 +++++++++++ src/test/resources/asm/DIVU.elf.objdump | 276 +++++++++++ src/test/resources/asm/DIVW.elf.objdump | 460 ++++++++++++++++++ src/test/resources/asm/MUL.elf.objdump | 276 +++++++++++ src/test/resources/asm/MULH.elf.objdump | 276 +++++++++++ src/test/resources/asm/MULHSU.elf.objdump | 276 +++++++++++ src/test/resources/asm/MULHU.elf.objdump | 276 +++++++++++ src/test/resources/asm/MULW.elf.objdump | 460 ++++++++++++++++++ src/test/resources/asm/REM.elf.objdump | 276 +++++++++++ src/test/resources/asm/REMU.elf.objdump | 276 +++++++++++ src/test/resources/asm/REMUW.elf.objdump | 460 ++++++++++++++++++ src/test/resources/asm/REMW.elf.objdump | 460 ++++++++++++++++++ src/test/resources/hex/C.ADD.elf.hex | 50 ++ src/test/resources/hex/C.ADDI.elf.hex | 45 ++ src/test/resources/hex/C.ADDI16SP.elf.hex | 29 ++ src/test/resources/hex/C.ADDI4SPN.elf.hex | 29 ++ src/test/resources/hex/C.AND.elf.hex | 50 ++ src/test/resources/hex/C.ANDI.elf.hex | 45 ++ src/test/resources/hex/C.BEQZ.elf.hex | 33 ++ src/test/resources/hex/C.BNEZ.elf.hex | 30 ++ src/test/resources/hex/C.J.elf.hex | 32 ++ src/test/resources/hex/C.JAL.elf.hex | 32 ++ src/test/resources/hex/C.JALR.elf.hex | 35 ++ src/test/resources/hex/C.JR.elf.hex | 35 ++ src/test/resources/hex/C.LI.elf.hex | 45 ++ src/test/resources/hex/C.LUI.elf.hex | 45 ++ src/test/resources/hex/C.LW.elf.hex | 39 ++ src/test/resources/hex/C.LWSP.elf.hex | 40 ++ src/test/resources/hex/C.MV.elf.hex | 50 ++ src/test/resources/hex/C.OR.elf.hex | 50 ++ src/test/resources/hex/C.SLLI.elf.hex | 45 ++ src/test/resources/hex/C.SRAI.elf.hex | 45 ++ src/test/resources/hex/C.SRLI.elf.hex | 45 ++ src/test/resources/hex/C.SUB.elf.hex | 50 ++ src/test/resources/hex/C.SW.elf.hex | 41 ++ src/test/resources/hex/C.SWSP.elf.hex | 41 ++ src/test/resources/hex/C.XOR.elf.hex | 50 ++ src/test/resources/hex/DIV.elf.hex | 52 ++ src/test/resources/hex/DIVU.elf.hex | 52 ++ src/test/resources/hex/MUL.elf.hex | 52 ++ src/test/resources/hex/MULH.elf.hex | 52 ++ src/test/resources/hex/MULHSU.elf.hex | 52 ++ src/test/resources/hex/MULHU.elf.hex | 52 ++ src/test/resources/hex/REM.elf.hex | 52 ++ src/test/resources/hex/REMU.elf.hex | 52 ++ src/test/resources/ref/C.ADD.reference_output | 7 + .../resources/ref/C.ADDI.reference_output | 7 + .../resources/ref/C.ADDI16SP.reference_output | 2 + .../resources/ref/C.ADDI4SPN.reference_output | 2 + src/test/resources/ref/C.AND.reference_output | 7 + .../resources/ref/C.ANDI.reference_output | 7 + .../resources/ref/C.BEQZ.reference_output | 2 + .../resources/ref/C.BNEZ.reference_output | 2 + src/test/resources/ref/C.J.reference_output | 2 + src/test/resources/ref/C.JAL.reference_output | 2 + .../resources/ref/C.JALR.reference_output | 2 + src/test/resources/ref/C.JR.reference_output | 2 + src/test/resources/ref/C.LI.reference_output | 7 + src/test/resources/ref/C.LUI.reference_output | 7 + src/test/resources/ref/C.LW.reference_output | 10 + .../resources/ref/C.LWSP.reference_output | 10 + src/test/resources/ref/C.MV.reference_output | 7 + src/test/resources/ref/C.OR.reference_output | 7 + .../resources/ref/C.SLLI.reference_output | 7 + .../resources/ref/C.SRAI.reference_output | 7 + .../resources/ref/C.SRLI.reference_output | 7 + src/test/resources/ref/C.SUB.reference_output | 7 + src/test/resources/ref/C.SW.reference_output | 10 + .../resources/ref/C.SWSP.reference_output | 10 + src/test/resources/ref/C.XOR.reference_output | 7 + src/test/resources/ref/DIV.reference_output | 13 + src/test/resources/ref/DIVU.reference_output | 13 + .../resources/ref/I-ADD-01.reference_output | 22 +- .../resources/ref/I-ADDI-01.reference_output | 22 +- .../resources/ref/I-AND-01.reference_output | 22 +- .../resources/ref/I-ANDI-01.reference_output | 22 +- .../resources/ref/I-AUIPC-01.reference_output | 8 +- .../resources/ref/I-BEQ-01.reference_output | 20 +- .../resources/ref/I-BGE-01.reference_output | 20 +- .../resources/ref/I-BGEU-01.reference_output | 20 +- .../resources/ref/I-BLT-01.reference_output | 20 +- .../resources/ref/I-BLTU-01.reference_output | 20 +- .../resources/ref/I-BNE-01.reference_output | 20 +- .../resources/ref/I-CSRRC-01.reference_output | 12 +- .../ref/I-CSRRCI-01.reference_output | 8 +- .../resources/ref/I-CSRRS-01.reference_output | 12 +- .../ref/I-CSRRSI-01.reference_output | 8 +- .../resources/ref/I-CSRRW-01.reference_output | 8 +- .../ref/I-CSRRWI-01.reference_output | 4 +- .../ref/I-DELAY_SLOTS-01.reference_output | 4 +- .../ref/I-EBREAK-01.reference_output | 2 +- .../resources/ref/I-ECALL-01.reference_output | 2 +- .../ref/I-ENDIANESS-01.reference_output | 4 +- .../ref/I-FENCE.I-01.reference_output | 2 +- src/test/resources/ref/I-IO.reference_output | 22 +- .../resources/ref/I-JAL-01.reference_output | 10 +- .../resources/ref/I-JALR-01.reference_output | 12 +- .../resources/ref/I-LB-01.reference_output | 18 +- .../resources/ref/I-LBU-01.reference_output | 18 +- .../resources/ref/I-LH-01.reference_output | 10 +- .../resources/ref/I-LHU-01.reference_output | 10 +- .../resources/ref/I-LUI-01.reference_output | 8 +- .../resources/ref/I-LW-01.reference_output | 6 +- .../ref/I-MISALIGN_JMP-01.reference_output | 18 +- .../ref/I-MISALIGN_LDST-01.reference_output | 22 +- .../resources/ref/I-NOP-01.reference_output | 16 +- .../resources/ref/I-OR-01.reference_output | 22 +- .../resources/ref/I-ORI-01.reference_output | 22 +- .../ref/I-RF_size-01.reference_output | 18 +- .../ref/I-RF_width-01.reference_output | 16 +- .../resources/ref/I-RF_x0-01.reference_output | 6 +- .../resources/ref/I-SB-01.reference_output | 8 +- .../resources/ref/I-SH-01.reference_output | 8 +- .../resources/ref/I-SLL-01.reference_output | 22 +- .../resources/ref/I-SLLI-01.reference_output | 20 +- .../resources/ref/I-SLT-01.reference_output | 24 +- .../resources/ref/I-SLTI-01.reference_output | 22 +- .../resources/ref/I-SLTIU-01.reference_output | 22 +- .../resources/ref/I-SLTU-01.reference_output | 24 +- .../resources/ref/I-SRA-01.reference_output | 22 +- .../resources/ref/I-SRAI-01.reference_output | 20 +- .../resources/ref/I-SRL-01.reference_output | 22 +- .../resources/ref/I-SRLI-01.reference_output | 20 +- .../resources/ref/I-SUB-01.reference_output | 22 +- .../resources/ref/I-SW-01.reference_output | 8 +- .../resources/ref/I-XOR-01.reference_output | 22 +- .../resources/ref/I-XORI-01.reference_output | 22 +- src/test/resources/ref/MUL.reference_output | 13 + src/test/resources/ref/MULH.reference_output | 13 + .../resources/ref/MULHSU.reference_output | 13 + src/test/resources/ref/MULHU.reference_output | 13 + src/test/resources/ref/REM.reference_output | 13 + src/test/resources/ref/REMU.reference_output | 13 + 160 files changed, 13173 insertions(+), 442 deletions(-) create mode 100644 src/test/resources/asm/C.ADD.elf.objdump create mode 100644 src/test/resources/asm/C.ADDI.elf.objdump create mode 100644 src/test/resources/asm/C.ADDI16SP.elf.objdump create mode 100644 src/test/resources/asm/C.ADDI4SPN.elf.objdump create mode 100644 src/test/resources/asm/C.AND.elf.objdump create mode 100644 src/test/resources/asm/C.ANDI.elf.objdump create mode 100644 src/test/resources/asm/C.BEQZ.elf.objdump create mode 100644 src/test/resources/asm/C.BNEZ.elf.objdump create mode 100644 src/test/resources/asm/C.J.elf.objdump create mode 100644 src/test/resources/asm/C.JAL.elf.objdump create mode 100644 src/test/resources/asm/C.JALR.elf.objdump create mode 100644 src/test/resources/asm/C.JR.elf.objdump create mode 100644 src/test/resources/asm/C.LI.elf.objdump create mode 100644 src/test/resources/asm/C.LUI.elf.objdump create mode 100644 src/test/resources/asm/C.LW.elf.objdump create mode 100644 src/test/resources/asm/C.LWSP.elf.objdump create mode 100644 src/test/resources/asm/C.MV.elf.objdump create mode 100644 src/test/resources/asm/C.OR.elf.objdump create mode 100644 src/test/resources/asm/C.SLLI.elf.objdump create mode 100644 src/test/resources/asm/C.SRAI.elf.objdump create mode 100644 src/test/resources/asm/C.SRLI.elf.objdump create mode 100644 src/test/resources/asm/C.SUB.elf.objdump create mode 100644 src/test/resources/asm/C.SW.elf.objdump create mode 100644 src/test/resources/asm/C.SWSP.elf.objdump create mode 100644 src/test/resources/asm/C.XOR.elf.objdump create mode 100644 src/test/resources/asm/DIV.elf.objdump create mode 100644 src/test/resources/asm/DIVU.elf.objdump create mode 100644 src/test/resources/asm/DIVW.elf.objdump create mode 100644 src/test/resources/asm/MUL.elf.objdump create mode 100644 src/test/resources/asm/MULH.elf.objdump create mode 100644 src/test/resources/asm/MULHSU.elf.objdump create mode 100644 src/test/resources/asm/MULHU.elf.objdump create mode 100644 src/test/resources/asm/MULW.elf.objdump create mode 100644 src/test/resources/asm/REM.elf.objdump create mode 100644 src/test/resources/asm/REMU.elf.objdump create mode 100644 src/test/resources/asm/REMUW.elf.objdump create mode 100644 src/test/resources/asm/REMW.elf.objdump create mode 100644 src/test/resources/hex/C.ADD.elf.hex create mode 100644 src/test/resources/hex/C.ADDI.elf.hex create mode 100644 src/test/resources/hex/C.ADDI16SP.elf.hex create mode 100644 src/test/resources/hex/C.ADDI4SPN.elf.hex create mode 100644 src/test/resources/hex/C.AND.elf.hex create mode 100644 src/test/resources/hex/C.ANDI.elf.hex create mode 100644 src/test/resources/hex/C.BEQZ.elf.hex create mode 100644 src/test/resources/hex/C.BNEZ.elf.hex create mode 100644 src/test/resources/hex/C.J.elf.hex create mode 100644 src/test/resources/hex/C.JAL.elf.hex create mode 100644 src/test/resources/hex/C.JALR.elf.hex create mode 100644 src/test/resources/hex/C.JR.elf.hex create mode 100644 src/test/resources/hex/C.LI.elf.hex create mode 100644 src/test/resources/hex/C.LUI.elf.hex create mode 100644 src/test/resources/hex/C.LW.elf.hex create mode 100644 src/test/resources/hex/C.LWSP.elf.hex create mode 100644 src/test/resources/hex/C.MV.elf.hex create mode 100644 src/test/resources/hex/C.OR.elf.hex create mode 100644 src/test/resources/hex/C.SLLI.elf.hex create mode 100644 src/test/resources/hex/C.SRAI.elf.hex create mode 100644 src/test/resources/hex/C.SRLI.elf.hex create mode 100644 src/test/resources/hex/C.SUB.elf.hex create mode 100644 src/test/resources/hex/C.SW.elf.hex create mode 100644 src/test/resources/hex/C.SWSP.elf.hex create mode 100644 src/test/resources/hex/C.XOR.elf.hex create mode 100644 src/test/resources/hex/DIV.elf.hex create mode 100644 src/test/resources/hex/DIVU.elf.hex create mode 100644 src/test/resources/hex/MUL.elf.hex create mode 100644 src/test/resources/hex/MULH.elf.hex create mode 100644 src/test/resources/hex/MULHSU.elf.hex create mode 100644 src/test/resources/hex/MULHU.elf.hex create mode 100644 src/test/resources/hex/REM.elf.hex create mode 100644 src/test/resources/hex/REMU.elf.hex create mode 100644 src/test/resources/ref/C.ADD.reference_output create mode 100644 src/test/resources/ref/C.ADDI.reference_output create mode 100644 src/test/resources/ref/C.ADDI16SP.reference_output create mode 100644 src/test/resources/ref/C.ADDI4SPN.reference_output create mode 100644 src/test/resources/ref/C.AND.reference_output create mode 100644 src/test/resources/ref/C.ANDI.reference_output create mode 100644 src/test/resources/ref/C.BEQZ.reference_output create mode 100644 src/test/resources/ref/C.BNEZ.reference_output create mode 100644 src/test/resources/ref/C.J.reference_output create mode 100644 src/test/resources/ref/C.JAL.reference_output create mode 100644 src/test/resources/ref/C.JALR.reference_output create mode 100644 src/test/resources/ref/C.JR.reference_output create mode 100644 src/test/resources/ref/C.LI.reference_output create mode 100644 src/test/resources/ref/C.LUI.reference_output create mode 100644 src/test/resources/ref/C.LW.reference_output create mode 100644 src/test/resources/ref/C.LWSP.reference_output create mode 100644 src/test/resources/ref/C.MV.reference_output create mode 100644 src/test/resources/ref/C.OR.reference_output create mode 100644 src/test/resources/ref/C.SLLI.reference_output create mode 100644 src/test/resources/ref/C.SRAI.reference_output create mode 100644 src/test/resources/ref/C.SRLI.reference_output create mode 100644 src/test/resources/ref/C.SUB.reference_output create mode 100644 src/test/resources/ref/C.SW.reference_output create mode 100644 src/test/resources/ref/C.SWSP.reference_output create mode 100644 src/test/resources/ref/C.XOR.reference_output create mode 100644 src/test/resources/ref/DIV.reference_output create mode 100644 src/test/resources/ref/DIVU.reference_output create mode 100644 src/test/resources/ref/MUL.reference_output create mode 100644 src/test/resources/ref/MULH.reference_output create mode 100644 src/test/resources/ref/MULHSU.reference_output create mode 100644 src/test/resources/ref/MULHU.reference_output create mode 100644 src/test/resources/ref/REM.reference_output create mode 100644 src/test/resources/ref/REMU.reference_output diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 1d2e861..a5778c8 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -2094,7 +2094,7 @@ public: Workspace::dBusAccess(addr,wr,size,mask,data,error); if(wr && addr == 0xF00FFF2C){ out32 << hex << setw(8) << std::setfill('0') << *data; - if(++out32Counter % 4 == 0) out32 << "\r\n"; + if(++out32Counter % 4 == 0) out32 << "\n"; *error = 0; } } @@ -2394,14 +2394,7 @@ string freeRtosTests[] = { string riscvComplianceMain[] = { - "I-LB-01", - "I-LBU-01", - "I-LH-01", - "I-LHU-01", - "I-LW-01", - "I-SB-01", - "I-SH-01", - "I-SW-01", + "I-IO", "I-NOP-01", "I-LUI-01", "I-ADD-01", @@ -2432,26 +2425,88 @@ string riscvComplianceMain[] = { "I-BNE-01", "I-JAL-01", "I-JALR-01", + "I-DELAY_SLOTS-01", + "I-ENDIANESS-01", + "I-RF_size-01", + "I-RF_width-01", + "I-RF_x0-01", +}; + + + +string complianceTestMemory[] = { + "I-LB-01", + "I-LBU-01", + "I-LH-01", + "I-LHU-01", + "I-LW-01", + "I-SB-01", + "I-SH-01", + "I-SW-01" +}; + + +string complianceTestCsr[] = { "I-CSRRC-01", "I-CSRRCI-01", "I-CSRRS-01", "I-CSRRSI-01", "I-CSRRW-01", "I-CSRRWI-01", - "I-DELAY_SLOTS-01", - "I-EBREAK-01", - "I-ECALL-01", - "I-ENDIANESS-01", - "I-FENCE.I-01", - "I-IO", - "I-MISALIGN_JMP-01", + #ifndef COMPRESSED + "I-MISALIGN_JMP-01", //Only apply for non RVC cores + #endif "I-MISALIGN_LDST-01", - "I-RF_size-01", - "I-RF_width-01", - "I-RF_x0-01", - + "I-ECALL-01", }; + +string complianceTestMul[] = { + "MUL", + "MULH", + "MULHSU", + "MULHU", +}; + +string complianceTestDiv[] = { + "DIV", + "DIVU", + "REM", + "REMU", +}; + + +string complianceTestC[] = { + "C.ADD", + "C.ADDI16SP", + "C.ADDI4SPN", + "C.ADDI", + "C.AND", + "C.ANDI", + "C.BEQZ", + "C.BNEZ", + "C.JAL", + "C.JALR", + "C.J", + "C.JR", + "C.LI", + "C.LUI", + "C.LW", + "C.LWSP", + "C.MV", + "C.OR", + "C.SLLI", + "C.SRAI", + "C.SRLI", + "C.SUB", + "C.SW", + "C.SWSP", + "C.XOR", +}; + + + + struct timespec timer_start(){ struct timespec start_time; clock_gettime(CLOCK_REALTIME, &start_time); //CLOCK_PROCESS_CPUTIME_ID @@ -2544,7 +2599,38 @@ int main(int argc, char **argv, char **env) { for(const string &name : riscvComplianceMain){ redo(REDO, Compliance(name).run();) } + for(const string &name : complianceTestMemory){ + redo(REDO, Compliance(name).run();) + } + #ifdef COMPRESSED + for(const string &name : complianceTestC){ + redo(REDO, Compliance(name).run();) + } + #endif + + #ifdef MUL + for(const string &name : complianceTestMul){ + redo(REDO, Compliance(name).run();) + } + #endif + #ifdef DIV + for(const string &name : complianceTestDiv){ + redo(REDO, Compliance(name).run();) + } + #endif + #ifdef CSR + for(const string &name : complianceTestCsr){ + redo(REDO, Compliance(name).run();) + } + #endif + + #ifdef FENCEI + redo(REDO, Compliance("I-FENCE.I-01").run();) + #endif + #ifdef EBREAK + redo(REDO, Compliance("I-EBREAK-01").run();) + #endif for(const string &name : riscvTestMain){ redo(REDO,RiscvTest(name).run();) diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile index 03cca7d..9ed8a3c 100644 --- a/src/test/cpp/regression/makefile +++ b/src/test/cpp/regression/makefile @@ -9,6 +9,8 @@ ISA_TEST?=yes MUL?=yes DIV?=yes CSR?=yes +EBREAK?=no +FENCEI?=no MMU?=yes SEED?=no ATOMIC?=no @@ -47,6 +49,15 @@ ifeq ($(COMPRESSED),yes) ADDCFLAGS += -CFLAGS -DCOMPRESSED endif +ifeq ($(FENCEI),yes) + ADDCFLAGS += -CFLAGS -DFENCEI +endif + +ifeq ($(EBREAK),yes) + ADDCFLAGS += -CFLAGS -DEBREAK +endif + + ifeq ($(DHRYSTONE),yes) ADDCFLAGS += -CFLAGS -DDHRYSTONE endif diff --git a/src/test/resources/asm/C.ADD.elf.objdump b/src/test/resources/asm/C.ADD.elf.objdump new file mode 100644 index 0000000..32ee1ad --- /dev/null +++ b/src/test/resources/asm/C.ADD.elf.objdump @@ -0,0 +1,334 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.ADD.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4201 li tp,0 +800000f8: 4181 li gp,0 +800000fa: 9192 add gp,gp,tp +800000fc: c00e sw gp,0(sp) +800000fe: 4481 li s1,0 +80000100: 4405 li s0,1 +80000102: 9426 add s0,s0,s1 +80000104: c222 sw s0,4(sp) +80000106: 4601 li a2,0 +80000108: fff00593 li a1,-1 +8000010c: 95b2 add a1,a1,a2 +8000010e: c42e sw a1,8(sp) +80000110: 4701 li a4,0 +80000112: 000086b7 lui a3,0x8 +80000116: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +8000011a: 96ba add a3,a3,a4 +8000011c: c636 sw a3,12(sp) +8000011e: 4801 li a6,0 +80000120: 67a1 lui a5,0x8 +80000122: 97c2 add a5,a5,a6 +80000124: c83e sw a5,16(sp) +80000126: 00001117 auipc sp,0x1 +8000012a: eee10113 addi sp,sp,-274 # 80001014 +8000012e: 4905 li s2,1 +80000130: 4881 li a7,0 +80000132: 98ca add a7,a7,s2 +80000134: c046 sw a7,0(sp) +80000136: 4a05 li s4,1 +80000138: 4985 li s3,1 +8000013a: 99d2 add s3,s3,s4 +8000013c: c24e sw s3,4(sp) +8000013e: 4b05 li s6,1 +80000140: fff00a93 li s5,-1 +80000144: 9ada add s5,s5,s6 +80000146: c456 sw s5,8(sp) +80000148: 4c05 li s8,1 +8000014a: 00008bb7 lui s7,0x8 +8000014e: fffb8b93 addi s7,s7,-1 # 7fff <_start-0x7fff8001> +80000152: 9be2 add s7,s7,s8 +80000154: c65e sw s7,12(sp) +80000156: 4d05 li s10,1 +80000158: 6ca1 lui s9,0x8 +8000015a: 9cea add s9,s9,s10 +8000015c: c866 sw s9,16(sp) +8000015e: 00001117 auipc sp,0x1 +80000162: eca10113 addi sp,sp,-310 # 80001028 +80000166: fff00e13 li t3,-1 +8000016a: 4d81 li s11,0 +8000016c: 9df2 add s11,s11,t3 +8000016e: c06e sw s11,0(sp) +80000170: fff00f13 li t5,-1 +80000174: 4e85 li t4,1 +80000176: 9efa add t4,t4,t5 +80000178: c276 sw t4,4(sp) +8000017a: fff00193 li gp,-1 +8000017e: fff00f93 li t6,-1 +80000182: 9f8e add t6,t6,gp +80000184: c47e sw t6,8(sp) +80000186: fff00413 li s0,-1 +8000018a: 00008237 lui tp,0x8 +8000018e: fff20213 addi tp,tp,-1 # 7fff <_start-0x7fff8001> +80000192: 9222 add tp,tp,s0 +80000194: c612 sw tp,12(sp) +80000196: fff00593 li a1,-1 +8000019a: 64a1 lui s1,0x8 +8000019c: 94ae add s1,s1,a1 +8000019e: c826 sw s1,16(sp) +800001a0: 00001117 auipc sp,0x1 +800001a4: e9c10113 addi sp,sp,-356 # 8000103c +800001a8: 000086b7 lui a3,0x8 +800001ac: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +800001b0: 4601 li a2,0 +800001b2: 9636 add a2,a2,a3 +800001b4: c032 sw a2,0(sp) +800001b6: 000087b7 lui a5,0x8 +800001ba: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800001be: 4705 li a4,1 +800001c0: 973e add a4,a4,a5 +800001c2: c23a sw a4,4(sp) +800001c4: 000088b7 lui a7,0x8 +800001c8: fff88893 addi a7,a7,-1 # 7fff <_start-0x7fff8001> +800001cc: fff00813 li a6,-1 +800001d0: 9846 add a6,a6,a7 +800001d2: c442 sw a6,8(sp) +800001d4: 000089b7 lui s3,0x8 +800001d8: fff98993 addi s3,s3,-1 # 7fff <_start-0x7fff8001> +800001dc: 00008937 lui s2,0x8 +800001e0: fff90913 addi s2,s2,-1 # 7fff <_start-0x7fff8001> +800001e4: 994e add s2,s2,s3 +800001e6: c64a sw s2,12(sp) +800001e8: 00008ab7 lui s5,0x8 +800001ec: fffa8a93 addi s5,s5,-1 # 7fff <_start-0x7fff8001> +800001f0: 6a21 lui s4,0x8 +800001f2: 9a56 add s4,s4,s5 +800001f4: c852 sw s4,16(sp) +800001f6: 00001117 auipc sp,0x1 +800001fa: e5a10113 addi sp,sp,-422 # 80001050 +800001fe: 6ba1 lui s7,0x8 +80000200: 4b01 li s6,0 +80000202: 9b5e add s6,s6,s7 +80000204: c05a sw s6,0(sp) +80000206: 6ca1 lui s9,0x8 +80000208: 4c05 li s8,1 +8000020a: 9c66 add s8,s8,s9 +8000020c: c262 sw s8,4(sp) +8000020e: 6da1 lui s11,0x8 +80000210: fff00d13 li s10,-1 +80000214: 9d6e add s10,s10,s11 +80000216: c46a sw s10,8(sp) +80000218: 6ea1 lui t4,0x8 +8000021a: 00008e37 lui t3,0x8 +8000021e: fffe0e13 addi t3,t3,-1 # 7fff <_start-0x7fff8001> +80000222: 9e76 add t3,t3,t4 +80000224: c672 sw t3,12(sp) +80000226: 6fa1 lui t6,0x8 +80000228: 6f21 lui t5,0x8 +8000022a: 9f7e add t5,t5,t6 +8000022c: c87a sw t5,16(sp) +8000022e: 00001517 auipc a0,0x1 +80000232: dd250513 addi a0,a0,-558 # 80001000 +80000236: 00001597 auipc a1,0x1 +8000023a: e3a58593 addi a1,a1,-454 # 80001070 <_end> +8000023e: f0100637 lui a2,0xf0100 +80000242: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +80000246 : +80000246: 00b50c63 beq a0,a1,8000025e +8000024a: 4554 lw a3,12(a0) +8000024c: c214 sw a3,0(a2) +8000024e: 4514 lw a3,8(a0) +80000250: c214 sw a3,0(a2) +80000252: 4154 lw a3,4(a0) +80000254: c214 sw a3,0(a2) +80000256: 4114 lw a3,0(a0) +80000258: c214 sw a3,0(a2) +8000025a: 0541 addi a0,a0,16 +8000025c: b7ed j 80000246 + +8000025e : +8000025e: f0100537 lui a0,0xf0100 +80000262: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000266: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.ADDI.elf.objdump b/src/test/resources/asm/C.ADDI.elf.objdump new file mode 100644 index 0000000..e0e0a94 --- /dev/null +++ b/src/test/resources/asm/C.ADDI.elf.objdump @@ -0,0 +1,304 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.ADDI.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4181 li gp,0 +800000f8: 0185 addi gp,gp,1 +800000fa: c00e sw gp,0(sp) +800000fc: 4201 li tp,0 +800000fe: 0209 addi tp,tp,2 +80000100: c212 sw tp,4(sp) +80000102: 4401 li s0,0 +80000104: 043d addi s0,s0,15 +80000106: c422 sw s0,8(sp) +80000108: 4481 li s1,0 +8000010a: 04c1 addi s1,s1,16 +8000010c: c626 sw s1,12(sp) +8000010e: 4581 li a1,0 +80000110: 05fd addi a1,a1,31 +80000112: c82e sw a1,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f0010113 addi sp,sp,-256 # 80001014 +8000011c: 4605 li a2,1 +8000011e: 0605 addi a2,a2,1 +80000120: c032 sw a2,0(sp) +80000122: 4685 li a3,1 +80000124: 0689 addi a3,a3,2 +80000126: c236 sw a3,4(sp) +80000128: 4705 li a4,1 +8000012a: 073d addi a4,a4,15 +8000012c: c43a sw a4,8(sp) +8000012e: 4785 li a5,1 +80000130: 07c1 addi a5,a5,16 +80000132: c63e sw a5,12(sp) +80000134: 4805 li a6,1 +80000136: 087d addi a6,a6,31 +80000138: c842 sw a6,16(sp) +8000013a: 00001117 auipc sp,0x1 +8000013e: eee10113 addi sp,sp,-274 # 80001028 +80000142: fff00893 li a7,-1 +80000146: 0885 addi a7,a7,1 +80000148: c046 sw a7,0(sp) +8000014a: fff00913 li s2,-1 +8000014e: 0909 addi s2,s2,2 +80000150: c24a sw s2,4(sp) +80000152: fff00993 li s3,-1 +80000156: 09bd addi s3,s3,15 +80000158: c44e sw s3,8(sp) +8000015a: fff00a13 li s4,-1 +8000015e: 0a41 addi s4,s4,16 +80000160: c652 sw s4,12(sp) +80000162: fff00a93 li s5,-1 +80000166: 0afd addi s5,s5,31 +80000168: c856 sw s5,16(sp) +8000016a: 00001117 auipc sp,0x1 +8000016e: ed210113 addi sp,sp,-302 # 8000103c +80000172: 00080b37 lui s6,0x80 +80000176: fffb0b13 addi s6,s6,-1 # 7ffff <_start-0x7ff80001> +8000017a: 0b05 addi s6,s6,1 +8000017c: c05a sw s6,0(sp) +8000017e: 00080bb7 lui s7,0x80 +80000182: fffb8b93 addi s7,s7,-1 # 7ffff <_start-0x7ff80001> +80000186: 0b89 addi s7,s7,2 +80000188: c25e sw s7,4(sp) +8000018a: 00080c37 lui s8,0x80 +8000018e: fffc0c13 addi s8,s8,-1 # 7ffff <_start-0x7ff80001> +80000192: 0c3d addi s8,s8,15 +80000194: c462 sw s8,8(sp) +80000196: 00080cb7 lui s9,0x80 +8000019a: fffc8c93 addi s9,s9,-1 # 7ffff <_start-0x7ff80001> +8000019e: 0cc1 addi s9,s9,16 +800001a0: c666 sw s9,12(sp) +800001a2: 00080d37 lui s10,0x80 +800001a6: fffd0d13 addi s10,s10,-1 # 7ffff <_start-0x7ff80001> +800001aa: 0d7d addi s10,s10,31 +800001ac: c86a sw s10,16(sp) +800001ae: 00001117 auipc sp,0x1 +800001b2: ea210113 addi sp,sp,-350 # 80001050 +800001b6: 00080db7 lui s11,0x80 +800001ba: 0d85 addi s11,s11,1 +800001bc: c06e sw s11,0(sp) +800001be: 00080e37 lui t3,0x80 +800001c2: 0e09 addi t3,t3,2 +800001c4: c272 sw t3,4(sp) +800001c6: 00080eb7 lui t4,0x80 +800001ca: 0ebd addi t4,t4,15 +800001cc: c476 sw t4,8(sp) +800001ce: 00080f37 lui t5,0x80 +800001d2: 0f41 addi t5,t5,16 +800001d4: c67a sw t5,12(sp) +800001d6: 00080fb7 lui t6,0x80 +800001da: 0ffd addi t6,t6,31 +800001dc: c87e sw t6,16(sp) +800001de: 00001517 auipc a0,0x1 +800001e2: e2250513 addi a0,a0,-478 # 80001000 +800001e6: 00001597 auipc a1,0x1 +800001ea: e8a58593 addi a1,a1,-374 # 80001070 <_end> +800001ee: f0100637 lui a2,0xf0100 +800001f2: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +800001f6 : +800001f6: 00b50c63 beq a0,a1,8000020e +800001fa: 4554 lw a3,12(a0) +800001fc: c214 sw a3,0(a2) +800001fe: 4514 lw a3,8(a0) +80000200: c214 sw a3,0(a2) +80000202: 4154 lw a3,4(a0) +80000204: c214 sw a3,0(a2) +80000206: 4114 lw a3,0(a0) +80000208: c214 sw a3,0(a2) +8000020a: 0541 addi a0,a0,16 +8000020c: b7ed j 800001f6 + +8000020e : +8000020e: f0100537 lui a0,0xf0100 +80000212: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000216: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.ADDI16SP.elf.objdump b/src/test/resources/asm/C.ADDI16SP.elf.objdump new file mode 100644 index 0000000..bd3351c --- /dev/null +++ b/src/test/resources/asm/C.ADDI16SP.elf.objdump @@ -0,0 +1,194 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.ADDI16SP.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001097 auipc ra,0x1 +800000f2: f1208093 addi ra,ra,-238 # 80001000 +800000f6: 0141 addi sp,sp,16 +800000f8: 0020a023 sw sp,0(ra) +800000fc: 00001097 auipc ra,0x1 +80000100: f0808093 addi ra,ra,-248 # 80001004 +80000104: 6105 addi sp,sp,32 +80000106: 0020a023 sw sp,0(ra) +8000010a: 00001097 auipc ra,0x1 +8000010e: efe08093 addi ra,ra,-258 # 80001008 +80000112: 6121 addi sp,sp,64 +80000114: 0020a023 sw sp,0(ra) +80000118: 00001097 auipc ra,0x1 +8000011c: ef408093 addi ra,ra,-268 # 8000100c +80000120: 617d addi sp,sp,496 +80000122: 0020a023 sw sp,0(ra) +80000126: 00001097 auipc ra,0x1 +8000012a: eea08093 addi ra,ra,-278 # 80001010 +8000012e: 7101 addi sp,sp,-512 +80000130: 0020a023 sw sp,0(ra) +80000134: 00001517 auipc a0,0x1 +80000138: ecc50513 addi a0,a0,-308 # 80001000 +8000013c: 00001597 auipc a1,0x1 +80000140: ee458593 addi a1,a1,-284 # 80001020 <_end> +80000144: f0100637 lui a2,0xf0100 +80000148: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +8000014c : +8000014c: 00b50c63 beq a0,a1,80000164 +80000150: 4554 lw a3,12(a0) +80000152: c214 sw a3,0(a2) +80000154: 4514 lw a3,8(a0) +80000156: c214 sw a3,0(a2) +80000158: 4154 lw a3,4(a0) +8000015a: c214 sw a3,0(a2) +8000015c: 4114 lw a3,0(a0) +8000015e: c214 sw a3,0(a2) +80000160: 0541 addi a0,a0,16 +80000162: b7ed j 8000014c + +80000164 : +80000164: f0100537 lui a0,0xf0100 +80000168: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +8000016c: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.ADDI4SPN.elf.objdump b/src/test/resources/asm/C.ADDI4SPN.elf.objdump new file mode 100644 index 0000000..5a09876 --- /dev/null +++ b/src/test/resources/asm/C.ADDI4SPN.elf.objdump @@ -0,0 +1,194 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.ADDI4SPN.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001097 auipc ra,0x1 +800000f2: f1208093 addi ra,ra,-238 # 80001000 +800000f6: 0050 addi a2,sp,4 +800000f8: 00c0a023 sw a2,0(ra) +800000fc: 00001097 auipc ra,0x1 +80000100: f0808093 addi ra,ra,-248 # 80001004 +80000104: 0034 addi a3,sp,8 +80000106: 00d0a023 sw a3,0(ra) +8000010a: 00001097 auipc ra,0x1 +8000010e: efe08093 addi ra,ra,-258 # 80001008 +80000112: 0078 addi a4,sp,12 +80000114: 00e0a023 sw a4,0(ra) +80000118: 00001097 auipc ra,0x1 +8000011c: ef408093 addi ra,ra,-268 # 8000100c +80000120: 081c addi a5,sp,16 +80000122: 00f0a023 sw a5,0(ra) +80000126: 00001097 auipc ra,0x1 +8000012a: eea08093 addi ra,ra,-278 # 80001010 +8000012e: 1fe0 addi s0,sp,1020 +80000130: 0080a023 sw s0,0(ra) +80000134: 00001517 auipc a0,0x1 +80000138: ecc50513 addi a0,a0,-308 # 80001000 +8000013c: 00001597 auipc a1,0x1 +80000140: ee458593 addi a1,a1,-284 # 80001020 <_end> +80000144: f0100637 lui a2,0xf0100 +80000148: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +8000014c : +8000014c: 00b50c63 beq a0,a1,80000164 +80000150: 4554 lw a3,12(a0) +80000152: c214 sw a3,0(a2) +80000154: 4514 lw a3,8(a0) +80000156: c214 sw a3,0(a2) +80000158: 4154 lw a3,4(a0) +8000015a: c214 sw a3,0(a2) +8000015c: 4114 lw a3,0(a0) +8000015e: c214 sw a3,0(a2) +80000160: 0541 addi a0,a0,16 +80000162: b7ed j 8000014c + +80000164 : +80000164: f0100537 lui a0,0xf0100 +80000168: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +8000016c: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.AND.elf.objdump b/src/test/resources/asm/C.AND.elf.objdump new file mode 100644 index 0000000..d78ccb9 --- /dev/null +++ b/src/test/resources/asm/C.AND.elf.objdump @@ -0,0 +1,334 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.AND.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4581 li a1,0 +800000f8: 4481 li s1,0 +800000fa: 8ced and s1,s1,a1 +800000fc: c026 sw s1,0(sp) +800000fe: 4681 li a3,0 +80000100: 4605 li a2,1 +80000102: 8e75 and a2,a2,a3 +80000104: c232 sw a2,4(sp) +80000106: 4781 li a5,0 +80000108: fff00713 li a4,-1 +8000010c: 8f7d and a4,a4,a5 +8000010e: c43a sw a4,8(sp) +80000110: 4481 li s1,0 +80000112: 00008437 lui s0,0x8 +80000116: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> +8000011a: 8c65 and s0,s0,s1 +8000011c: c622 sw s0,12(sp) +8000011e: 4601 li a2,0 +80000120: 65a1 lui a1,0x8 +80000122: 8df1 and a1,a1,a2 +80000124: c82e sw a1,16(sp) +80000126: 00001117 auipc sp,0x1 +8000012a: eee10113 addi sp,sp,-274 # 80001014 +8000012e: 4705 li a4,1 +80000130: 4681 li a3,0 +80000132: 8ef9 and a3,a3,a4 +80000134: c036 sw a3,0(sp) +80000136: 4405 li s0,1 +80000138: 4785 li a5,1 +8000013a: 8fe1 and a5,a5,s0 +8000013c: c23e sw a5,4(sp) +8000013e: 4585 li a1,1 +80000140: fff00493 li s1,-1 +80000144: 8ced and s1,s1,a1 +80000146: c426 sw s1,8(sp) +80000148: 4685 li a3,1 +8000014a: 00008637 lui a2,0x8 +8000014e: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +80000152: 8e75 and a2,a2,a3 +80000154: c632 sw a2,12(sp) +80000156: 4785 li a5,1 +80000158: 6721 lui a4,0x8 +8000015a: 8f7d and a4,a4,a5 +8000015c: c83a sw a4,16(sp) +8000015e: 00001117 auipc sp,0x1 +80000162: eca10113 addi sp,sp,-310 # 80001028 +80000166: fff00493 li s1,-1 +8000016a: 4401 li s0,0 +8000016c: 8c65 and s0,s0,s1 +8000016e: c022 sw s0,0(sp) +80000170: fff00613 li a2,-1 +80000174: 4585 li a1,1 +80000176: 8df1 and a1,a1,a2 +80000178: c22e sw a1,4(sp) +8000017a: fff00713 li a4,-1 +8000017e: fff00693 li a3,-1 +80000182: 8ef9 and a3,a3,a4 +80000184: c436 sw a3,8(sp) +80000186: fff00413 li s0,-1 +8000018a: 000087b7 lui a5,0x8 +8000018e: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80000192: 8fe1 and a5,a5,s0 +80000194: c63e sw a5,12(sp) +80000196: fff00593 li a1,-1 +8000019a: 64a1 lui s1,0x8 +8000019c: 8ced and s1,s1,a1 +8000019e: c826 sw s1,16(sp) +800001a0: 00001117 auipc sp,0x1 +800001a4: e9c10113 addi sp,sp,-356 # 8000103c +800001a8: 000086b7 lui a3,0x8 +800001ac: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +800001b0: 4601 li a2,0 +800001b2: 8e75 and a2,a2,a3 +800001b4: c032 sw a2,0(sp) +800001b6: 000087b7 lui a5,0x8 +800001ba: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800001be: 4705 li a4,1 +800001c0: 8f7d and a4,a4,a5 +800001c2: c23a sw a4,4(sp) +800001c4: 000084b7 lui s1,0x8 +800001c8: fff48493 addi s1,s1,-1 # 7fff <_start-0x7fff8001> +800001cc: fff00413 li s0,-1 +800001d0: 8c65 and s0,s0,s1 +800001d2: c422 sw s0,8(sp) +800001d4: 00008637 lui a2,0x8 +800001d8: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +800001dc: 000085b7 lui a1,0x8 +800001e0: fff58593 addi a1,a1,-1 # 7fff <_start-0x7fff8001> +800001e4: 8df1 and a1,a1,a2 +800001e6: c62e sw a1,12(sp) +800001e8: 00008737 lui a4,0x8 +800001ec: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +800001f0: 66a1 lui a3,0x8 +800001f2: 8ef9 and a3,a3,a4 +800001f4: c836 sw a3,16(sp) +800001f6: 00001117 auipc sp,0x1 +800001fa: e5a10113 addi sp,sp,-422 # 80001050 +800001fe: 6421 lui s0,0x8 +80000200: 4781 li a5,0 +80000202: 8fe1 and a5,a5,s0 +80000204: c03e sw a5,0(sp) +80000206: 65a1 lui a1,0x8 +80000208: 4485 li s1,1 +8000020a: 8ced and s1,s1,a1 +8000020c: c226 sw s1,4(sp) +8000020e: 66a1 lui a3,0x8 +80000210: fff00613 li a2,-1 +80000214: 8e75 and a2,a2,a3 +80000216: c432 sw a2,8(sp) +80000218: 67a1 lui a5,0x8 +8000021a: 00008737 lui a4,0x8 +8000021e: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80000222: 8f7d and a4,a4,a5 +80000224: c63a sw a4,12(sp) +80000226: 64a1 lui s1,0x8 +80000228: 6421 lui s0,0x8 +8000022a: 8c65 and s0,s0,s1 +8000022c: c822 sw s0,16(sp) +8000022e: 00001517 auipc a0,0x1 +80000232: dd250513 addi a0,a0,-558 # 80001000 +80000236: 00001597 auipc a1,0x1 +8000023a: e3a58593 addi a1,a1,-454 # 80001070 <_end> +8000023e: f0100637 lui a2,0xf0100 +80000242: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +80000246 : +80000246: 00b50c63 beq a0,a1,8000025e +8000024a: 4554 lw a3,12(a0) +8000024c: c214 sw a3,0(a2) +8000024e: 4514 lw a3,8(a0) +80000250: c214 sw a3,0(a2) +80000252: 4154 lw a3,4(a0) +80000254: c214 sw a3,0(a2) +80000256: 4114 lw a3,0(a0) +80000258: c214 sw a3,0(a2) +8000025a: 0541 addi a0,a0,16 +8000025c: b7ed j 80000246 + +8000025e : +8000025e: f0100537 lui a0,0xf0100 +80000262: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000266: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.ANDI.elf.objdump b/src/test/resources/asm/C.ANDI.elf.objdump new file mode 100644 index 0000000..525df9d --- /dev/null +++ b/src/test/resources/asm/C.ANDI.elf.objdump @@ -0,0 +1,304 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.ANDI.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4581 li a1,0 +800000f8: 8981 andi a1,a1,0 +800000fa: c02e sw a1,0(sp) +800000fc: 4601 li a2,0 +800000fe: 8a05 andi a2,a2,1 +80000100: c232 sw a2,4(sp) +80000102: 4681 li a3,0 +80000104: 8ac1 andi a3,a3,16 +80000106: c436 sw a3,8(sp) +80000108: 4701 li a4,0 +8000010a: 8b7d andi a4,a4,31 +8000010c: c63a sw a4,12(sp) +8000010e: 4781 li a5,0 +80000110: 9b85 andi a5,a5,-31 +80000112: c83e sw a5,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f0010113 addi sp,sp,-256 # 80001014 +8000011c: 4405 li s0,1 +8000011e: 8801 andi s0,s0,0 +80000120: c022 sw s0,0(sp) +80000122: 4485 li s1,1 +80000124: 8885 andi s1,s1,1 +80000126: c226 sw s1,4(sp) +80000128: 4585 li a1,1 +8000012a: 89c1 andi a1,a1,16 +8000012c: c42e sw a1,8(sp) +8000012e: 4605 li a2,1 +80000130: 8a7d andi a2,a2,31 +80000132: c632 sw a2,12(sp) +80000134: 4685 li a3,1 +80000136: 9a85 andi a3,a3,-31 +80000138: c836 sw a3,16(sp) +8000013a: 00001117 auipc sp,0x1 +8000013e: eee10113 addi sp,sp,-274 # 80001028 +80000142: fff00713 li a4,-1 +80000146: 8b01 andi a4,a4,0 +80000148: c03a sw a4,0(sp) +8000014a: fff00793 li a5,-1 +8000014e: 8b85 andi a5,a5,1 +80000150: c23e sw a5,4(sp) +80000152: fff00413 li s0,-1 +80000156: 8841 andi s0,s0,16 +80000158: c422 sw s0,8(sp) +8000015a: fff00493 li s1,-1 +8000015e: 88fd andi s1,s1,31 +80000160: c626 sw s1,12(sp) +80000162: fff00593 li a1,-1 +80000166: 9985 andi a1,a1,-31 +80000168: c82e sw a1,16(sp) +8000016a: 00001117 auipc sp,0x1 +8000016e: ed210113 addi sp,sp,-302 # 8000103c +80000172: 00080637 lui a2,0x80 +80000176: fff60613 addi a2,a2,-1 # 7ffff <_start-0x7ff80001> +8000017a: 8a01 andi a2,a2,0 +8000017c: c032 sw a2,0(sp) +8000017e: 000806b7 lui a3,0x80 +80000182: fff68693 addi a3,a3,-1 # 7ffff <_start-0x7ff80001> +80000186: 8a85 andi a3,a3,1 +80000188: c236 sw a3,4(sp) +8000018a: 00080737 lui a4,0x80 +8000018e: fff70713 addi a4,a4,-1 # 7ffff <_start-0x7ff80001> +80000192: 8b41 andi a4,a4,16 +80000194: c43a sw a4,8(sp) +80000196: 000807b7 lui a5,0x80 +8000019a: fff78793 addi a5,a5,-1 # 7ffff <_start-0x7ff80001> +8000019e: 8bfd andi a5,a5,31 +800001a0: c63e sw a5,12(sp) +800001a2: 00080437 lui s0,0x80 +800001a6: fff40413 addi s0,s0,-1 # 7ffff <_start-0x7ff80001> +800001aa: 9805 andi s0,s0,-31 +800001ac: c822 sw s0,16(sp) +800001ae: 00001117 auipc sp,0x1 +800001b2: ea210113 addi sp,sp,-350 # 80001050 +800001b6: 000804b7 lui s1,0x80 +800001ba: 8881 andi s1,s1,0 +800001bc: c026 sw s1,0(sp) +800001be: 000805b7 lui a1,0x80 +800001c2: 8985 andi a1,a1,1 +800001c4: c22e sw a1,4(sp) +800001c6: 00080637 lui a2,0x80 +800001ca: 8a41 andi a2,a2,16 +800001cc: c432 sw a2,8(sp) +800001ce: 000806b7 lui a3,0x80 +800001d2: 8afd andi a3,a3,31 +800001d4: c636 sw a3,12(sp) +800001d6: 00080737 lui a4,0x80 +800001da: 9b05 andi a4,a4,-31 +800001dc: c83a sw a4,16(sp) +800001de: 00001517 auipc a0,0x1 +800001e2: e2250513 addi a0,a0,-478 # 80001000 +800001e6: 00001597 auipc a1,0x1 +800001ea: e8a58593 addi a1,a1,-374 # 80001070 <_end> +800001ee: f0100637 lui a2,0xf0100 +800001f2: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +800001f6 : +800001f6: 00b50c63 beq a0,a1,8000020e +800001fa: 4554 lw a3,12(a0) +800001fc: c214 sw a3,0(a2) +800001fe: 4514 lw a3,8(a0) +80000200: c214 sw a3,0(a2) +80000202: 4154 lw a3,4(a0) +80000204: c214 sw a3,0(a2) +80000206: 4114 lw a3,0(a0) +80000208: c214 sw a3,0(a2) +8000020a: 0541 addi a0,a0,16 +8000020c: b7ed j 800001f6 + +8000020e : +8000020e: f0100537 lui a0,0xf0100 +80000212: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000216: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.BEQZ.elf.objdump b/src/test/resources/asm/C.BEQZ.elf.objdump new file mode 100644 index 0000000..f94b96f --- /dev/null +++ b/src/test/resources/asm/C.BEQZ.elf.objdump @@ -0,0 +1,215 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.BEQZ.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4781 li a5,0 +800000f8: 8f9d sub a5,a5,a5 +800000fa: c789 beqz a5,80000104 <_start+0x104> +800000fc: 000127b7 lui a5,0x12 +80000100: 3ab78793 addi a5,a5,939 # 123ab <_start-0x7ffedc55> +80000104: c03e sw a5,0(sp) +80000106: 00001117 auipc sp,0x1 +8000010a: efe10113 addi sp,sp,-258 # 80001004 +8000010e: 4405 li s0,1 +80000110: 8c01 sub s0,s0,s0 +80000112: c409 beqz s0,8000011c <_start+0x11c> +80000114: 00012437 lui s0,0x12 +80000118: 3ab40413 addi s0,s0,939 # 123ab <_start-0x7ffedc55> +8000011c: c022 sw s0,0(sp) +8000011e: 00001117 auipc sp,0x1 +80000122: eea10113 addi sp,sp,-278 # 80001008 +80000126: 54fd li s1,-1 +80000128: 8c85 sub s1,s1,s1 +8000012a: c489 beqz s1,80000134 <_start+0x134> +8000012c: 000124b7 lui s1,0x12 +80000130: 3ab48493 addi s1,s1,939 # 123ab <_start-0x7ffedc55> +80000134: c026 sw s1,0(sp) +80000136: 00001117 auipc sp,0x1 +8000013a: ed610113 addi sp,sp,-298 # 8000100c +8000013e: 000085b7 lui a1,0x8 +80000142: fff58593 addi a1,a1,-1 # 7fff <_start-0x7fff8001> +80000146: 8d8d sub a1,a1,a1 +80000148: c589 beqz a1,80000152 <_start+0x152> +8000014a: 000125b7 lui a1,0x12 +8000014e: 3ab58593 addi a1,a1,939 # 123ab <_start-0x7ffedc55> +80000152: c02e sw a1,0(sp) +80000154: 00001117 auipc sp,0x1 +80000158: ebc10113 addi sp,sp,-324 # 80001010 +8000015c: 6621 lui a2,0x8 +8000015e: 8e11 sub a2,a2,a2 +80000160: c609 beqz a2,8000016a <_start+0x16a> +80000162: 00012637 lui a2,0x12 +80000166: 3ab60613 addi a2,a2,939 # 123ab <_start-0x7ffedc55> +8000016a: c032 sw a2,0(sp) +8000016c: 00001517 auipc a0,0x1 +80000170: e9450513 addi a0,a0,-364 # 80001000 +80000174: 00001597 auipc a1,0x1 +80000178: eac58593 addi a1,a1,-340 # 80001020 <_end> +8000017c: f0100637 lui a2,0xf0100 +80000180: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +80000184 : +80000184: 00b50c63 beq a0,a1,8000019c +80000188: 4554 lw a3,12(a0) +8000018a: c214 sw a3,0(a2) +8000018c: 4514 lw a3,8(a0) +8000018e: c214 sw a3,0(a2) +80000190: 4154 lw a3,4(a0) +80000192: c214 sw a3,0(a2) +80000194: 4114 lw a3,0(a0) +80000196: c214 sw a3,0(a2) +80000198: 0541 addi a0,a0,16 +8000019a: b7ed j 80000184 + +8000019c : +8000019c: f0100537 lui a0,0xf0100 +800001a0: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +800001a4: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.BNEZ.elf.objdump b/src/test/resources/asm/C.BNEZ.elf.objdump new file mode 100644 index 0000000..1519203 --- /dev/null +++ b/src/test/resources/asm/C.BNEZ.elf.objdump @@ -0,0 +1,205 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.BNEZ.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4681 li a3,0 +800000f8: e291 bnez a3,800000fc <_start+0xfc> +800000fa: 4681 li a3,0 +800000fc: c036 sw a3,0(sp) +800000fe: 00001117 auipc sp,0x1 +80000102: f0610113 addi sp,sp,-250 # 80001004 +80000106: 4705 li a4,1 +80000108: e311 bnez a4,8000010c <_start+0x10c> +8000010a: 4701 li a4,0 +8000010c: c03a sw a4,0(sp) +8000010e: 00001117 auipc sp,0x1 +80000112: efa10113 addi sp,sp,-262 # 80001008 +80000116: 57fd li a5,-1 +80000118: e391 bnez a5,8000011c <_start+0x11c> +8000011a: 4781 li a5,0 +8000011c: c03e sw a5,0(sp) +8000011e: 00001117 auipc sp,0x1 +80000122: eee10113 addi sp,sp,-274 # 8000100c +80000126: 00008437 lui s0,0x8 +8000012a: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> +8000012e: e011 bnez s0,80000132 <_start+0x132> +80000130: 4401 li s0,0 +80000132: c022 sw s0,0(sp) +80000134: 00001117 auipc sp,0x1 +80000138: edc10113 addi sp,sp,-292 # 80001010 +8000013c: 64a1 lui s1,0x8 +8000013e: e091 bnez s1,80000142 <_start+0x142> +80000140: 4481 li s1,0 +80000142: c026 sw s1,0(sp) +80000144: 00001517 auipc a0,0x1 +80000148: ebc50513 addi a0,a0,-324 # 80001000 +8000014c: 00001597 auipc a1,0x1 +80000150: ed458593 addi a1,a1,-300 # 80001020 <_end> +80000154: f0100637 lui a2,0xf0100 +80000158: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +8000015c : +8000015c: 00b50c63 beq a0,a1,80000174 +80000160: 4554 lw a3,12(a0) +80000162: c214 sw a3,0(a2) +80000164: 4514 lw a3,8(a0) +80000166: c214 sw a3,0(a2) +80000168: 4154 lw a3,4(a0) +8000016a: c214 sw a3,0(a2) +8000016c: 4114 lw a3,0(a0) +8000016e: c214 sw a3,0(a2) +80000170: 0541 addi a0,a0,16 +80000172: b7ed j 8000015c + +80000174 : +80000174: f0100537 lui a0,0xf0100 +80000178: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +8000017c: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.J.elf.objdump b/src/test/resources/asm/C.J.elf.objdump new file mode 100644 index 0000000..717bca1 --- /dev/null +++ b/src/test/resources/asm/C.J.elf.objdump @@ -0,0 +1,211 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.J.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4581 li a1,0 +800000f8: a029 j 80000102 <_start+0x102> +800000fa: 000125b7 lui a1,0x12 +800000fe: 3ab58593 addi a1,a1,939 # 123ab <_start-0x7ffedc55> +80000102: c02e sw a1,0(sp) +80000104: 00001117 auipc sp,0x1 +80000108: f0010113 addi sp,sp,-256 # 80001004 +8000010c: 4605 li a2,1 +8000010e: a029 j 80000118 <_start+0x118> +80000110: 00012637 lui a2,0x12 +80000114: 3ab60613 addi a2,a2,939 # 123ab <_start-0x7ffedc55> +80000118: c032 sw a2,0(sp) +8000011a: 00001117 auipc sp,0x1 +8000011e: eee10113 addi sp,sp,-274 # 80001008 +80000122: 56fd li a3,-1 +80000124: a029 j 8000012e <_start+0x12e> +80000126: 000126b7 lui a3,0x12 +8000012a: 3ab68693 addi a3,a3,939 # 123ab <_start-0x7ffedc55> +8000012e: c036 sw a3,0(sp) +80000130: 00001117 auipc sp,0x1 +80000134: edc10113 addi sp,sp,-292 # 8000100c +80000138: 00008737 lui a4,0x8 +8000013c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80000140: a029 j 8000014a <_start+0x14a> +80000142: 00012737 lui a4,0x12 +80000146: 3ab70713 addi a4,a4,939 # 123ab <_start-0x7ffedc55> +8000014a: c03a sw a4,0(sp) +8000014c: 00001117 auipc sp,0x1 +80000150: ec410113 addi sp,sp,-316 # 80001010 +80000154: 67a1 lui a5,0x8 +80000156: a029 j 80000160 <_start+0x160> +80000158: 000127b7 lui a5,0x12 +8000015c: 3ab78793 addi a5,a5,939 # 123ab <_start-0x7ffedc55> +80000160: c03e sw a5,0(sp) +80000162: 00001517 auipc a0,0x1 +80000166: e9e50513 addi a0,a0,-354 # 80001000 +8000016a: 00001597 auipc a1,0x1 +8000016e: eb658593 addi a1,a1,-330 # 80001020 <_end> +80000172: f0100637 lui a2,0xf0100 +80000176: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +8000017a : +8000017a: 00b50c63 beq a0,a1,80000192 +8000017e: 4554 lw a3,12(a0) +80000180: c214 sw a3,0(a2) +80000182: 4514 lw a3,8(a0) +80000184: c214 sw a3,0(a2) +80000186: 4154 lw a3,4(a0) +80000188: c214 sw a3,0(a2) +8000018a: 4114 lw a3,0(a0) +8000018c: c214 sw a3,0(a2) +8000018e: 0541 addi a0,a0,16 +80000190: b7ed j 8000017a + +80000192 : +80000192: f0100537 lui a0,0xf0100 +80000196: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +8000019a: 00052023 sw zero,0(a0) +8000019e: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.JAL.elf.objdump b/src/test/resources/asm/C.JAL.elf.objdump new file mode 100644 index 0000000..b8a4de7 --- /dev/null +++ b/src/test/resources/asm/C.JAL.elf.objdump @@ -0,0 +1,211 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.JAL.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4401 li s0,0 +800000f8: 2029 jal 80000102 <_start+0x102> +800000fa: 00012437 lui s0,0x12 +800000fe: 3ab40413 addi s0,s0,939 # 123ab <_start-0x7ffedc55> +80000102: c022 sw s0,0(sp) +80000104: 00001117 auipc sp,0x1 +80000108: f0010113 addi sp,sp,-256 # 80001004 +8000010c: 4485 li s1,1 +8000010e: 2029 jal 80000118 <_start+0x118> +80000110: 000124b7 lui s1,0x12 +80000114: 3ab48493 addi s1,s1,939 # 123ab <_start-0x7ffedc55> +80000118: c026 sw s1,0(sp) +8000011a: 00001117 auipc sp,0x1 +8000011e: eee10113 addi sp,sp,-274 # 80001008 +80000122: 55fd li a1,-1 +80000124: 2029 jal 8000012e <_start+0x12e> +80000126: 000125b7 lui a1,0x12 +8000012a: 3ab58593 addi a1,a1,939 # 123ab <_start-0x7ffedc55> +8000012e: c02e sw a1,0(sp) +80000130: 00001117 auipc sp,0x1 +80000134: edc10113 addi sp,sp,-292 # 8000100c +80000138: 00008637 lui a2,0x8 +8000013c: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +80000140: 2029 jal 8000014a <_start+0x14a> +80000142: 00012637 lui a2,0x12 +80000146: 3ab60613 addi a2,a2,939 # 123ab <_start-0x7ffedc55> +8000014a: c032 sw a2,0(sp) +8000014c: 00001117 auipc sp,0x1 +80000150: ec410113 addi sp,sp,-316 # 80001010 +80000154: 66a1 lui a3,0x8 +80000156: 2029 jal 80000160 <_start+0x160> +80000158: 000126b7 lui a3,0x12 +8000015c: 3ab68693 addi a3,a3,939 # 123ab <_start-0x7ffedc55> +80000160: c036 sw a3,0(sp) +80000162: 00001517 auipc a0,0x1 +80000166: e9e50513 addi a0,a0,-354 # 80001000 +8000016a: 00001597 auipc a1,0x1 +8000016e: eb658593 addi a1,a1,-330 # 80001020 <_end> +80000172: f0100637 lui a2,0xf0100 +80000176: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +8000017a : +8000017a: 00b50c63 beq a0,a1,80000192 +8000017e: 4554 lw a3,12(a0) +80000180: c214 sw a3,0(a2) +80000182: 4514 lw a3,8(a0) +80000184: c214 sw a3,0(a2) +80000186: 4154 lw a3,4(a0) +80000188: c214 sw a3,0(a2) +8000018a: 4114 lw a3,0(a0) +8000018c: c214 sw a3,0(a2) +8000018e: 0541 addi a0,a0,16 +80000190: b7ed j 8000017a + +80000192 : +80000192: f0100537 lui a0,0xf0100 +80000196: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +8000019a: 00052023 sw zero,0(a0) +8000019e: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.JALR.elf.objdump b/src/test/resources/asm/C.JALR.elf.objdump new file mode 100644 index 0000000..2959f30 --- /dev/null +++ b/src/test/resources/asm/C.JALR.elf.objdump @@ -0,0 +1,220 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.JALR.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4501 li a0,0 +800000f8: 00000617 auipc a2,0x0 +800000fc: 01260613 addi a2,a2,18 # 8000010a <_start+0x10a> +80000100: 9602 jalr a2 +80000102: 00012537 lui a0,0x12 +80000106: 3ab50513 addi a0,a0,939 # 123ab <_start-0x7ffedc55> +8000010a: c032 sw a2,0(sp) +8000010c: 00001117 auipc sp,0x1 +80000110: ef810113 addi sp,sp,-264 # 80001004 +80000114: 4505 li a0,1 +80000116: 00000697 auipc a3,0x0 +8000011a: 01268693 addi a3,a3,18 # 80000128 <_start+0x128> +8000011e: 9682 jalr a3 +80000120: 00012537 lui a0,0x12 +80000124: 3ab50513 addi a0,a0,939 # 123ab <_start-0x7ffedc55> +80000128: c036 sw a3,0(sp) +8000012a: 00001117 auipc sp,0x1 +8000012e: ede10113 addi sp,sp,-290 # 80001008 +80000132: 557d li a0,-1 +80000134: 00000717 auipc a4,0x0 +80000138: 01270713 addi a4,a4,18 # 80000146 <_start+0x146> +8000013c: 9702 jalr a4 +8000013e: 00012537 lui a0,0x12 +80000142: 3ab50513 addi a0,a0,939 # 123ab <_start-0x7ffedc55> +80000146: c03a sw a4,0(sp) +80000148: 00001117 auipc sp,0x1 +8000014c: ec410113 addi sp,sp,-316 # 8000100c +80000150: 00008537 lui a0,0x8 +80000154: fff50513 addi a0,a0,-1 # 7fff <_start-0x7fff8001> +80000158: 00000797 auipc a5,0x0 +8000015c: 01278793 addi a5,a5,18 # 8000016a <_start+0x16a> +80000160: 9782 jalr a5 +80000162: 00012537 lui a0,0x12 +80000166: 3ab50513 addi a0,a0,939 # 123ab <_start-0x7ffedc55> +8000016a: c03e sw a5,0(sp) +8000016c: 00001117 auipc sp,0x1 +80000170: ea410113 addi sp,sp,-348 # 80001010 +80000174: 6521 lui a0,0x8 +80000176: 00000817 auipc a6,0x0 +8000017a: 01280813 addi a6,a6,18 # 80000188 <_start+0x188> +8000017e: 9802 jalr a6 +80000180: 00012537 lui a0,0x12 +80000184: 3ab50513 addi a0,a0,939 # 123ab <_start-0x7ffedc55> +80000188: c042 sw a6,0(sp) +8000018a: 00001517 auipc a0,0x1 +8000018e: e7650513 addi a0,a0,-394 # 80001000 +80000192: 00001597 auipc a1,0x1 +80000196: e8e58593 addi a1,a1,-370 # 80001020 <_end> +8000019a: f0100637 lui a2,0xf0100 +8000019e: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +800001a2 : +800001a2: 00b50c63 beq a0,a1,800001ba +800001a6: 4554 lw a3,12(a0) +800001a8: c214 sw a3,0(a2) +800001aa: 4514 lw a3,8(a0) +800001ac: c214 sw a3,0(a2) +800001ae: 4154 lw a3,4(a0) +800001b0: c214 sw a3,0(a2) +800001b2: 4114 lw a3,0(a0) +800001b4: c214 sw a3,0(a2) +800001b6: 0541 addi a0,a0,16 +800001b8: b7ed j 800001a2 + +800001ba : +800001ba: f0100537 lui a0,0xf0100 +800001be: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +800001c2: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.JR.elf.objdump b/src/test/resources/asm/C.JR.elf.objdump new file mode 100644 index 0000000..0b05122 --- /dev/null +++ b/src/test/resources/asm/C.JR.elf.objdump @@ -0,0 +1,220 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.JR.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4501 li a0,0 +800000f8: 00000197 auipc gp,0x0 +800000fc: 01218193 addi gp,gp,18 # 8000010a <_start+0x10a> +80000100: 8182 jr gp +80000102: 00012537 lui a0,0x12 +80000106: 3ab50513 addi a0,a0,939 # 123ab <_start-0x7ffedc55> +8000010a: c00e sw gp,0(sp) +8000010c: 00001117 auipc sp,0x1 +80000110: ef810113 addi sp,sp,-264 # 80001004 +80000114: 4505 li a0,1 +80000116: 00000217 auipc tp,0x0 +8000011a: 01220213 addi tp,tp,18 # 80000128 <_start+0x128> +8000011e: 8202 jr tp +80000120: 00012537 lui a0,0x12 +80000124: 3ab50513 addi a0,a0,939 # 123ab <_start-0x7ffedc55> +80000128: c012 sw tp,0(sp) +8000012a: 00001117 auipc sp,0x1 +8000012e: ede10113 addi sp,sp,-290 # 80001008 +80000132: 557d li a0,-1 +80000134: 00000417 auipc s0,0x0 +80000138: 01240413 addi s0,s0,18 # 80000146 <_start+0x146> +8000013c: 8402 jr s0 +8000013e: 00012537 lui a0,0x12 +80000142: 3ab50513 addi a0,a0,939 # 123ab <_start-0x7ffedc55> +80000146: c022 sw s0,0(sp) +80000148: 00001117 auipc sp,0x1 +8000014c: ec410113 addi sp,sp,-316 # 8000100c +80000150: 00008537 lui a0,0x8 +80000154: fff50513 addi a0,a0,-1 # 7fff <_start-0x7fff8001> +80000158: 00000497 auipc s1,0x0 +8000015c: 01248493 addi s1,s1,18 # 8000016a <_start+0x16a> +80000160: 8482 jr s1 +80000162: 00012537 lui a0,0x12 +80000166: 3ab50513 addi a0,a0,939 # 123ab <_start-0x7ffedc55> +8000016a: c026 sw s1,0(sp) +8000016c: 00001117 auipc sp,0x1 +80000170: ea410113 addi sp,sp,-348 # 80001010 +80000174: 6521 lui a0,0x8 +80000176: 00000597 auipc a1,0x0 +8000017a: 01258593 addi a1,a1,18 # 80000188 <_start+0x188> +8000017e: 8582 jr a1 +80000180: 00012537 lui a0,0x12 +80000184: 3ab50513 addi a0,a0,939 # 123ab <_start-0x7ffedc55> +80000188: c02e sw a1,0(sp) +8000018a: 00001517 auipc a0,0x1 +8000018e: e7650513 addi a0,a0,-394 # 80001000 +80000192: 00001597 auipc a1,0x1 +80000196: e8e58593 addi a1,a1,-370 # 80001020 <_end> +8000019a: f0100637 lui a2,0xf0100 +8000019e: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fef0c> + +800001a2 : +800001a2: 00b50c63 beq a0,a1,800001ba +800001a6: 4554 lw a3,12(a0) +800001a8: c214 sw a3,0(a2) +800001aa: 4514 lw a3,8(a0) +800001ac: c214 sw a3,0(a2) +800001ae: 4154 lw a3,4(a0) +800001b0: c214 sw a3,0(a2) +800001b2: 4114 lw a3,0(a0) +800001b4: c214 sw a3,0(a2) +800001b6: 0541 addi a0,a0,16 +800001b8: b7ed j 800001a2 + +800001ba : +800001ba: f0100537 lui a0,0xf0100 +800001be: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fef00> +800001c2: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.LI.elf.objdump b/src/test/resources/asm/C.LI.elf.objdump new file mode 100644 index 0000000..f1b51bd --- /dev/null +++ b/src/test/resources/asm/C.LI.elf.objdump @@ -0,0 +1,304 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.LI.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4181 li gp,0 +800000f8: 4181 li gp,0 +800000fa: c00e sw gp,0(sp) +800000fc: 4201 li tp,0 +800000fe: 4205 li tp,1 +80000100: c212 sw tp,4(sp) +80000102: 4401 li s0,0 +80000104: 4441 li s0,16 +80000106: c422 sw s0,8(sp) +80000108: 4481 li s1,0 +8000010a: 44fd li s1,31 +8000010c: c626 sw s1,12(sp) +8000010e: 4581 li a1,0 +80000110: 5585 li a1,-31 +80000112: c82e sw a1,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f0010113 addi sp,sp,-256 # 80001014 +8000011c: 4605 li a2,1 +8000011e: 4601 li a2,0 +80000120: c032 sw a2,0(sp) +80000122: 4685 li a3,1 +80000124: 4685 li a3,1 +80000126: c236 sw a3,4(sp) +80000128: 4705 li a4,1 +8000012a: 4741 li a4,16 +8000012c: c43a sw a4,8(sp) +8000012e: 4785 li a5,1 +80000130: 47fd li a5,31 +80000132: c63e sw a5,12(sp) +80000134: 4805 li a6,1 +80000136: 5805 li a6,-31 +80000138: c842 sw a6,16(sp) +8000013a: 00001117 auipc sp,0x1 +8000013e: eee10113 addi sp,sp,-274 # 80001028 +80000142: fff00893 li a7,-1 +80000146: 4881 li a7,0 +80000148: c046 sw a7,0(sp) +8000014a: fff00913 li s2,-1 +8000014e: 4905 li s2,1 +80000150: c24a sw s2,4(sp) +80000152: fff00993 li s3,-1 +80000156: 49c1 li s3,16 +80000158: c44e sw s3,8(sp) +8000015a: fff00a13 li s4,-1 +8000015e: 4a7d li s4,31 +80000160: c652 sw s4,12(sp) +80000162: fff00a93 li s5,-1 +80000166: 5a85 li s5,-31 +80000168: c856 sw s5,16(sp) +8000016a: 00001117 auipc sp,0x1 +8000016e: ed210113 addi sp,sp,-302 # 8000103c +80000172: 00080b37 lui s6,0x80 +80000176: fffb0b13 addi s6,s6,-1 # 7ffff <_start-0x7ff80001> +8000017a: 4b01 li s6,0 +8000017c: c05a sw s6,0(sp) +8000017e: 00080bb7 lui s7,0x80 +80000182: fffb8b93 addi s7,s7,-1 # 7ffff <_start-0x7ff80001> +80000186: 4b85 li s7,1 +80000188: c25e sw s7,4(sp) +8000018a: 00080c37 lui s8,0x80 +8000018e: fffc0c13 addi s8,s8,-1 # 7ffff <_start-0x7ff80001> +80000192: 4c41 li s8,16 +80000194: c462 sw s8,8(sp) +80000196: 00080cb7 lui s9,0x80 +8000019a: fffc8c93 addi s9,s9,-1 # 7ffff <_start-0x7ff80001> +8000019e: 4cfd li s9,31 +800001a0: c666 sw s9,12(sp) +800001a2: 00080d37 lui s10,0x80 +800001a6: fffd0d13 addi s10,s10,-1 # 7ffff <_start-0x7ff80001> +800001aa: 5d05 li s10,-31 +800001ac: c86a sw s10,16(sp) +800001ae: 00001117 auipc sp,0x1 +800001b2: ea210113 addi sp,sp,-350 # 80001050 +800001b6: 00080db7 lui s11,0x80 +800001ba: 4d81 li s11,0 +800001bc: c06e sw s11,0(sp) +800001be: 00080e37 lui t3,0x80 +800001c2: 4e05 li t3,1 +800001c4: c272 sw t3,4(sp) +800001c6: 00080eb7 lui t4,0x80 +800001ca: 4ec1 li t4,16 +800001cc: c476 sw t4,8(sp) +800001ce: 00080f37 lui t5,0x80 +800001d2: 4f7d li t5,31 +800001d4: c67a sw t5,12(sp) +800001d6: 00080fb7 lui t6,0x80 +800001da: 5f85 li t6,-31 +800001dc: c87e sw t6,16(sp) +800001de: 00001517 auipc a0,0x1 +800001e2: e2250513 addi a0,a0,-478 # 80001000 +800001e6: 00001597 auipc a1,0x1 +800001ea: e8a58593 addi a1,a1,-374 # 80001070 <_end> +800001ee: f0100637 lui a2,0xf0100 +800001f2: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +800001f6 : +800001f6: 00b50c63 beq a0,a1,8000020e +800001fa: 4554 lw a3,12(a0) +800001fc: c214 sw a3,0(a2) +800001fe: 4514 lw a3,8(a0) +80000200: c214 sw a3,0(a2) +80000202: 4154 lw a3,4(a0) +80000204: c214 sw a3,0(a2) +80000206: 4114 lw a3,0(a0) +80000208: c214 sw a3,0(a2) +8000020a: 0541 addi a0,a0,16 +8000020c: b7ed j 800001f6 + +8000020e : +8000020e: f0100537 lui a0,0xf0100 +80000212: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000216: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.LUI.elf.objdump b/src/test/resources/asm/C.LUI.elf.objdump new file mode 100644 index 0000000..980309e --- /dev/null +++ b/src/test/resources/asm/C.LUI.elf.objdump @@ -0,0 +1,304 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.LUI.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4181 li gp,0 +800000f8: 6185 lui gp,0x1 +800000fa: c00e sw gp,0(sp) +800000fc: 4201 li tp,0 +800000fe: 6209 lui tp,0x2 +80000100: c212 sw tp,4(sp) +80000102: 4401 li s0,0 +80000104: 643d lui s0,0xf +80000106: c422 sw s0,8(sp) +80000108: 4481 li s1,0 +8000010a: 64fd lui s1,0x1f +8000010c: c626 sw s1,12(sp) +8000010e: 4581 li a1,0 +80000110: 75fd lui a1,0xfffff +80000112: c82e sw a1,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f0010113 addi sp,sp,-256 # 80001014 +8000011c: 4605 li a2,1 +8000011e: 6605 lui a2,0x1 +80000120: c032 sw a2,0(sp) +80000122: 4685 li a3,1 +80000124: 6689 lui a3,0x2 +80000126: c236 sw a3,4(sp) +80000128: 4705 li a4,1 +8000012a: 673d lui a4,0xf +8000012c: c43a sw a4,8(sp) +8000012e: 4785 li a5,1 +80000130: 67fd lui a5,0x1f +80000132: c63e sw a5,12(sp) +80000134: 4805 li a6,1 +80000136: 787d lui a6,0xfffff +80000138: c842 sw a6,16(sp) +8000013a: 00001117 auipc sp,0x1 +8000013e: eee10113 addi sp,sp,-274 # 80001028 +80000142: fff00893 li a7,-1 +80000146: 6885 lui a7,0x1 +80000148: c046 sw a7,0(sp) +8000014a: fff00913 li s2,-1 +8000014e: 6909 lui s2,0x2 +80000150: c24a sw s2,4(sp) +80000152: fff00993 li s3,-1 +80000156: 69bd lui s3,0xf +80000158: c44e sw s3,8(sp) +8000015a: fff00a13 li s4,-1 +8000015e: 6a7d lui s4,0x1f +80000160: c652 sw s4,12(sp) +80000162: fff00a93 li s5,-1 +80000166: 7afd lui s5,0xfffff +80000168: c856 sw s5,16(sp) +8000016a: 00001117 auipc sp,0x1 +8000016e: ed210113 addi sp,sp,-302 # 8000103c +80000172: 00080b37 lui s6,0x80 +80000176: fffb0b13 addi s6,s6,-1 # 7ffff <_start-0x7ff80001> +8000017a: 6b05 lui s6,0x1 +8000017c: c05a sw s6,0(sp) +8000017e: 00080bb7 lui s7,0x80 +80000182: fffb8b93 addi s7,s7,-1 # 7ffff <_start-0x7ff80001> +80000186: 6b89 lui s7,0x2 +80000188: c25e sw s7,4(sp) +8000018a: 00080c37 lui s8,0x80 +8000018e: fffc0c13 addi s8,s8,-1 # 7ffff <_start-0x7ff80001> +80000192: 6c3d lui s8,0xf +80000194: c462 sw s8,8(sp) +80000196: 00080cb7 lui s9,0x80 +8000019a: fffc8c93 addi s9,s9,-1 # 7ffff <_start-0x7ff80001> +8000019e: 6cfd lui s9,0x1f +800001a0: c666 sw s9,12(sp) +800001a2: 00080d37 lui s10,0x80 +800001a6: fffd0d13 addi s10,s10,-1 # 7ffff <_start-0x7ff80001> +800001aa: 7d7d lui s10,0xfffff +800001ac: c86a sw s10,16(sp) +800001ae: 00001117 auipc sp,0x1 +800001b2: ea210113 addi sp,sp,-350 # 80001050 +800001b6: 00080db7 lui s11,0x80 +800001ba: 6d85 lui s11,0x1 +800001bc: c06e sw s11,0(sp) +800001be: 00080e37 lui t3,0x80 +800001c2: 6e09 lui t3,0x2 +800001c4: c272 sw t3,4(sp) +800001c6: 00080eb7 lui t4,0x80 +800001ca: 6ebd lui t4,0xf +800001cc: c476 sw t4,8(sp) +800001ce: 00080f37 lui t5,0x80 +800001d2: 6f7d lui t5,0x1f +800001d4: c67a sw t5,12(sp) +800001d6: 00080fb7 lui t6,0x80 +800001da: 7ffd lui t6,0xfffff +800001dc: c87e sw t6,16(sp) +800001de: 00001517 auipc a0,0x1 +800001e2: e2250513 addi a0,a0,-478 # 80001000 +800001e6: 00001597 auipc a1,0x1 +800001ea: e8a58593 addi a1,a1,-374 # 80001070 <_end> +800001ee: f0100637 lui a2,0xf0100 +800001f2: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +800001f6 : +800001f6: 00b50c63 beq a0,a1,8000020e +800001fa: 4554 lw a3,12(a0) +800001fc: c214 sw a3,0(a2) +800001fe: 4514 lw a3,8(a0) +80000200: c214 sw a3,0(a2) +80000202: 4154 lw a3,4(a0) +80000204: c214 sw a3,0(a2) +80000206: 4114 lw a3,0(a0) +80000208: c214 sw a3,0(a2) +8000020a: 0541 addi a0,a0,16 +8000020c: b7ed j 800001f6 + +8000020e : +8000020e: f0100537 lui a0,0xf0100 +80000212: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000216: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.LW.elf.objdump b/src/test/resources/asm/C.LW.elf.objdump new file mode 100644 index 0000000..93bca0e --- /dev/null +++ b/src/test/resources/asm/C.LW.elf.objdump @@ -0,0 +1,263 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.LW.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 00001717 auipc a4,0x1 +800000fa: f1e70713 addi a4,a4,-226 # 80001014 +800000fe: 4318 lw a4,0(a4) +80000100: c03a sw a4,0(sp) +80000102: 00001117 auipc sp,0x1 +80000106: f0210113 addi sp,sp,-254 # 80001004 +8000010a: 00001797 auipc a5,0x1 +8000010e: f0a78793 addi a5,a5,-246 # 80001014 +80000112: 43dc lw a5,4(a5) +80000114: c03e sw a5,0(sp) +80000116: 00001117 auipc sp,0x1 +8000011a: ef210113 addi sp,sp,-270 # 80001008 +8000011e: 00001417 auipc s0,0x1 +80000122: ef640413 addi s0,s0,-266 # 80001014 +80000126: 4400 lw s0,8(s0) +80000128: c022 sw s0,0(sp) +8000012a: 00001117 auipc sp,0x1 +8000012e: ee210113 addi sp,sp,-286 # 8000100c +80000132: 00001497 auipc s1,0x1 +80000136: ee248493 addi s1,s1,-286 # 80001014 +8000013a: 50e4 lw s1,100(s1) +8000013c: c026 sw s1,0(sp) +8000013e: 00001117 auipc sp,0x1 +80000142: ed210113 addi sp,sp,-302 # 80001010 +80000146: 00001697 auipc a3,0x1 +8000014a: ece68693 addi a3,a3,-306 # 80001014 +8000014e: 5ef4 lw a3,124(a3) +80000150: c036 sw a3,0(sp) +80000152: 00001517 auipc a0,0x1 +80000156: eae50513 addi a0,a0,-338 # 80001000 +8000015a: 00001597 auipc a1,0x1 +8000015e: f4658593 addi a1,a1,-186 # 800010a0 <_end> +80000162: f0100637 lui a2,0xf0100 +80000166: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee8c> + +8000016a : +8000016a: 00b50c63 beq a0,a1,80000182 +8000016e: 4554 lw a3,12(a0) +80000170: c214 sw a3,0(a2) +80000172: 4514 lw a3,8(a0) +80000174: c214 sw a3,0(a2) +80000176: 4154 lw a3,4(a0) +80000178: c214 sw a3,0(a2) +8000017a: 4114 lw a3,0(a0) +8000017c: c214 sw a3,0(a2) +8000017e: 0541 addi a0,a0,16 +80000180: b7ed j 8000016a + +80000182 : +80000182: f0100537 lui a0,0xf0100 +80000186: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee80> +8000018a: 00052023 sw zero,0(a0) +8000018e: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: 0000 unimp +80001016: 0000 unimp +80001018: 0001 nop +8000101a: 0000 unimp +8000101c: 0002 c.slli zero,0x0 +8000101e: 0000 unimp +80001020: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> +80001024: 0004 0x4 +80001026: 0000 unimp +80001028: 0005 c.nop 1 +8000102a: 0000 unimp +8000102c: 0006 c.slli zero,0x1 +8000102e: 0000 unimp +80001030: 00000007 0x7 +80001034: 0008 0x8 +80001036: 0000 unimp +80001038: 0009 c.nop 2 +8000103a: 0000 unimp +8000103c: 000a c.slli zero,0x2 +8000103e: 0000 unimp +80001040: 0000000b 0xb +80001044: 000c 0xc +80001046: 0000 unimp +80001048: 000d c.nop 3 +8000104a: 0000 unimp +8000104c: 000e c.slli zero,0x3 +8000104e: 0000 unimp +80001050: 0000000f fence unknown,unknown +80001054: 0010 0x10 +80001056: 0000 unimp +80001058: 0011 c.nop 4 +8000105a: 0000 unimp +8000105c: 0012 c.slli zero,0x4 +8000105e: 0000 unimp +80001060: 00000013 nop +80001064: 0014 0x14 +80001066: 0000 unimp +80001068: 0015 c.nop 5 +8000106a: 0000 unimp +8000106c: 0016 c.slli zero,0x5 +8000106e: 0000 unimp +80001070: 00000017 auipc zero,0x0 +80001074: 0018 0x18 +80001076: 0000 unimp +80001078: 0019 c.nop 6 +8000107a: 0000 unimp +8000107c: 001a c.slli zero,0x6 +8000107e: 0000 unimp +80001080: 0000001b 0x1b +80001084: 001c 0x1c +80001086: 0000 unimp +80001088: 001d c.nop 7 +8000108a: 0000 unimp +8000108c: 001e c.slli zero,0x7 +8000108e: 0000 unimp +80001090: 001f 0000 0000 0x1f + ... diff --git a/src/test/resources/asm/C.LWSP.elf.objdump b/src/test/resources/asm/C.LWSP.elf.objdump new file mode 100644 index 0000000..a8f61ca --- /dev/null +++ b/src/test/resources/asm/C.LWSP.elf.objdump @@ -0,0 +1,262 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.LWSP.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001097 auipc ra,0x1 +800000f2: f1208093 addi ra,ra,-238 # 80001000 +800000f6: 00001117 auipc sp,0x1 +800000fa: f1e10113 addi sp,sp,-226 # 80001014 +800000fe: 4202 lw tp,0(sp) +80000100: 0040a023 sw tp,0(ra) +80000104: 00001097 auipc ra,0x1 +80000108: f0008093 addi ra,ra,-256 # 80001004 +8000010c: 00001117 auipc sp,0x1 +80000110: f0810113 addi sp,sp,-248 # 80001014 +80000114: 4412 lw s0,4(sp) +80000116: 0080a023 sw s0,0(ra) +8000011a: 00001097 auipc ra,0x1 +8000011e: eee08093 addi ra,ra,-274 # 80001008 +80000122: 00001117 auipc sp,0x1 +80000126: ef210113 addi sp,sp,-270 # 80001014 +8000012a: 4822 lw a6,8(sp) +8000012c: 0100a023 sw a6,0(ra) +80000130: 00001097 auipc ra,0x1 +80000134: edc08093 addi ra,ra,-292 # 8000100c +80000138: 00001117 auipc sp,0x1 +8000013c: edc10113 addi sp,sp,-292 # 80001014 +80000140: 5ff6 lw t6,124(sp) +80000142: 01f0a023 sw t6,0(ra) +80000146: 00001097 auipc ra,0x1 +8000014a: eca08093 addi ra,ra,-310 # 80001010 +8000014e: 00001117 auipc sp,0x1 +80000152: ec610113 addi sp,sp,-314 # 80001014 +80000156: 5afe lw s5,252(sp) +80000158: 0150a023 sw s5,0(ra) +8000015c: 00001517 auipc a0,0x1 +80000160: ea450513 addi a0,a0,-348 # 80001000 +80000164: 00001597 auipc a1,0x1 +80000168: f3c58593 addi a1,a1,-196 # 800010a0 <_end> +8000016c: f0100637 lui a2,0xf0100 +80000170: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee8c> + +80000174 : +80000174: 00b50c63 beq a0,a1,8000018c +80000178: 4554 lw a3,12(a0) +8000017a: c214 sw a3,0(a2) +8000017c: 4514 lw a3,8(a0) +8000017e: c214 sw a3,0(a2) +80000180: 4154 lw a3,4(a0) +80000182: c214 sw a3,0(a2) +80000184: 4114 lw a3,0(a0) +80000186: c214 sw a3,0(a2) +80000188: 0541 addi a0,a0,16 +8000018a: b7ed j 80000174 + +8000018c : +8000018c: f0100537 lui a0,0xf0100 +80000190: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee80> +80000194: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: 0000 unimp +80001016: 0000 unimp +80001018: 0001 nop +8000101a: 0000 unimp +8000101c: 0002 c.slli zero,0x0 +8000101e: 0000 unimp +80001020: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> +80001024: 0004 0x4 +80001026: 0000 unimp +80001028: 0005 c.nop 1 +8000102a: 0000 unimp +8000102c: 0006 c.slli zero,0x1 +8000102e: 0000 unimp +80001030: 00000007 0x7 +80001034: 0008 0x8 +80001036: 0000 unimp +80001038: 0009 c.nop 2 +8000103a: 0000 unimp +8000103c: 000a c.slli zero,0x2 +8000103e: 0000 unimp +80001040: 0000000b 0xb +80001044: 000c 0xc +80001046: 0000 unimp +80001048: 000d c.nop 3 +8000104a: 0000 unimp +8000104c: 000e c.slli zero,0x3 +8000104e: 0000 unimp +80001050: 0000000f fence unknown,unknown +80001054: 0010 0x10 +80001056: 0000 unimp +80001058: 0011 c.nop 4 +8000105a: 0000 unimp +8000105c: 0012 c.slli zero,0x4 +8000105e: 0000 unimp +80001060: 00000013 nop +80001064: 0014 0x14 +80001066: 0000 unimp +80001068: 0015 c.nop 5 +8000106a: 0000 unimp +8000106c: 0016 c.slli zero,0x5 +8000106e: 0000 unimp +80001070: 00000017 auipc zero,0x0 +80001074: 0018 0x18 +80001076: 0000 unimp +80001078: 0019 c.nop 6 +8000107a: 0000 unimp +8000107c: 001a c.slli zero,0x6 +8000107e: 0000 unimp +80001080: 0000001b 0x1b +80001084: 001c 0x1c +80001086: 0000 unimp +80001088: 001d c.nop 7 +8000108a: 0000 unimp +8000108c: 001e c.slli zero,0x7 +8000108e: 0000 unimp +80001090: 001f 0000 0000 0x1f + ... diff --git a/src/test/resources/asm/C.MV.elf.objdump b/src/test/resources/asm/C.MV.elf.objdump new file mode 100644 index 0000000..491d682 --- /dev/null +++ b/src/test/resources/asm/C.MV.elf.objdump @@ -0,0 +1,334 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.MV.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4601 li a2,0 +800000f8: 4581 li a1,0 +800000fa: 85b2 mv a1,a2 +800000fc: c02e sw a1,0(sp) +800000fe: 4701 li a4,0 +80000100: 4685 li a3,1 +80000102: 86ba mv a3,a4 +80000104: c236 sw a3,4(sp) +80000106: 4401 li s0,0 +80000108: fff00793 li a5,-1 +8000010c: 87a2 mv a5,s0 +8000010e: c43e sw a5,8(sp) +80000110: 4581 li a1,0 +80000112: 000084b7 lui s1,0x8 +80000116: fff48493 addi s1,s1,-1 # 7fff <_start-0x7fff8001> +8000011a: 84ae mv s1,a1 +8000011c: c626 sw s1,12(sp) +8000011e: 4681 li a3,0 +80000120: 6621 lui a2,0x8 +80000122: 8636 mv a2,a3 +80000124: c832 sw a2,16(sp) +80000126: 00001117 auipc sp,0x1 +8000012a: eee10113 addi sp,sp,-274 # 80001014 +8000012e: 4785 li a5,1 +80000130: 4701 li a4,0 +80000132: 873e mv a4,a5 +80000134: c03a sw a4,0(sp) +80000136: 4485 li s1,1 +80000138: 4405 li s0,1 +8000013a: 8426 mv s0,s1 +8000013c: c222 sw s0,4(sp) +8000013e: 4605 li a2,1 +80000140: fff00593 li a1,-1 +80000144: 85b2 mv a1,a2 +80000146: c42e sw a1,8(sp) +80000148: 4705 li a4,1 +8000014a: 000086b7 lui a3,0x8 +8000014e: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +80000152: 86ba mv a3,a4 +80000154: c636 sw a3,12(sp) +80000156: 4405 li s0,1 +80000158: 67a1 lui a5,0x8 +8000015a: 87a2 mv a5,s0 +8000015c: c83e sw a5,16(sp) +8000015e: 00001117 auipc sp,0x1 +80000162: eca10113 addi sp,sp,-310 # 80001028 +80000166: fff00593 li a1,-1 +8000016a: 4481 li s1,0 +8000016c: 84ae mv s1,a1 +8000016e: c026 sw s1,0(sp) +80000170: fff00693 li a3,-1 +80000174: 4605 li a2,1 +80000176: 8636 mv a2,a3 +80000178: c232 sw a2,4(sp) +8000017a: fff00793 li a5,-1 +8000017e: fff00713 li a4,-1 +80000182: 873e mv a4,a5 +80000184: c43a sw a4,8(sp) +80000186: fff00493 li s1,-1 +8000018a: 00008437 lui s0,0x8 +8000018e: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> +80000192: 8426 mv s0,s1 +80000194: c622 sw s0,12(sp) +80000196: fff00613 li a2,-1 +8000019a: 65a1 lui a1,0x8 +8000019c: 85b2 mv a1,a2 +8000019e: c82e sw a1,16(sp) +800001a0: 00001117 auipc sp,0x1 +800001a4: e9c10113 addi sp,sp,-356 # 8000103c +800001a8: 00008737 lui a4,0x8 +800001ac: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +800001b0: 4681 li a3,0 +800001b2: 86ba mv a3,a4 +800001b4: c036 sw a3,0(sp) +800001b6: 00008437 lui s0,0x8 +800001ba: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> +800001be: 4785 li a5,1 +800001c0: 87a2 mv a5,s0 +800001c2: c23e sw a5,4(sp) +800001c4: 000085b7 lui a1,0x8 +800001c8: fff58593 addi a1,a1,-1 # 7fff <_start-0x7fff8001> +800001cc: fff00493 li s1,-1 +800001d0: 84ae mv s1,a1 +800001d2: c426 sw s1,8(sp) +800001d4: 000086b7 lui a3,0x8 +800001d8: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +800001dc: 00008637 lui a2,0x8 +800001e0: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +800001e4: 8636 mv a2,a3 +800001e6: c632 sw a2,12(sp) +800001e8: 000087b7 lui a5,0x8 +800001ec: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800001f0: 6721 lui a4,0x8 +800001f2: 873e mv a4,a5 +800001f4: c83a sw a4,16(sp) +800001f6: 00001117 auipc sp,0x1 +800001fa: e5a10113 addi sp,sp,-422 # 80001050 +800001fe: 64a1 lui s1,0x8 +80000200: 4401 li s0,0 +80000202: 8426 mv s0,s1 +80000204: c022 sw s0,0(sp) +80000206: 6621 lui a2,0x8 +80000208: 4585 li a1,1 +8000020a: 85b2 mv a1,a2 +8000020c: c22e sw a1,4(sp) +8000020e: 6721 lui a4,0x8 +80000210: fff00693 li a3,-1 +80000214: 86ba mv a3,a4 +80000216: c436 sw a3,8(sp) +80000218: 6421 lui s0,0x8 +8000021a: 000087b7 lui a5,0x8 +8000021e: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80000222: 87a2 mv a5,s0 +80000224: c63e sw a5,12(sp) +80000226: 65a1 lui a1,0x8 +80000228: 64a1 lui s1,0x8 +8000022a: 84ae mv s1,a1 +8000022c: c826 sw s1,16(sp) +8000022e: 00001517 auipc a0,0x1 +80000232: dd250513 addi a0,a0,-558 # 80001000 +80000236: 00001597 auipc a1,0x1 +8000023a: e3a58593 addi a1,a1,-454 # 80001070 <_end> +8000023e: f0100637 lui a2,0xf0100 +80000242: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +80000246 : +80000246: 00b50c63 beq a0,a1,8000025e +8000024a: 4554 lw a3,12(a0) +8000024c: c214 sw a3,0(a2) +8000024e: 4514 lw a3,8(a0) +80000250: c214 sw a3,0(a2) +80000252: 4154 lw a3,4(a0) +80000254: c214 sw a3,0(a2) +80000256: 4114 lw a3,0(a0) +80000258: c214 sw a3,0(a2) +8000025a: 0541 addi a0,a0,16 +8000025c: b7ed j 80000246 + +8000025e : +8000025e: f0100537 lui a0,0xf0100 +80000262: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000266: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.OR.elf.objdump b/src/test/resources/asm/C.OR.elf.objdump new file mode 100644 index 0000000..0bd35cb --- /dev/null +++ b/src/test/resources/asm/C.OR.elf.objdump @@ -0,0 +1,334 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.OR.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4401 li s0,0 +800000f8: 4781 li a5,0 +800000fa: 8fc1 or a5,a5,s0 +800000fc: c03e sw a5,0(sp) +800000fe: 4581 li a1,0 +80000100: 4485 li s1,1 +80000102: 8ccd or s1,s1,a1 +80000104: c226 sw s1,4(sp) +80000106: 4681 li a3,0 +80000108: fff00613 li a2,-1 +8000010c: 8e55 or a2,a2,a3 +8000010e: c432 sw a2,8(sp) +80000110: 4781 li a5,0 +80000112: 00008737 lui a4,0x8 +80000116: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +8000011a: 8f5d or a4,a4,a5 +8000011c: c63a sw a4,12(sp) +8000011e: 4481 li s1,0 +80000120: 6421 lui s0,0x8 +80000122: 8c45 or s0,s0,s1 +80000124: c822 sw s0,16(sp) +80000126: 00001117 auipc sp,0x1 +8000012a: eee10113 addi sp,sp,-274 # 80001014 +8000012e: 4605 li a2,1 +80000130: 4581 li a1,0 +80000132: 8dd1 or a1,a1,a2 +80000134: c02e sw a1,0(sp) +80000136: 4705 li a4,1 +80000138: 4685 li a3,1 +8000013a: 8ed9 or a3,a3,a4 +8000013c: c236 sw a3,4(sp) +8000013e: 4405 li s0,1 +80000140: fff00793 li a5,-1 +80000144: 8fc1 or a5,a5,s0 +80000146: c43e sw a5,8(sp) +80000148: 4585 li a1,1 +8000014a: 000084b7 lui s1,0x8 +8000014e: fff48493 addi s1,s1,-1 # 7fff <_start-0x7fff8001> +80000152: 8ccd or s1,s1,a1 +80000154: c626 sw s1,12(sp) +80000156: 4685 li a3,1 +80000158: 6621 lui a2,0x8 +8000015a: 8e55 or a2,a2,a3 +8000015c: c832 sw a2,16(sp) +8000015e: 00001117 auipc sp,0x1 +80000162: eca10113 addi sp,sp,-310 # 80001028 +80000166: fff00793 li a5,-1 +8000016a: 4701 li a4,0 +8000016c: 8f5d or a4,a4,a5 +8000016e: c03a sw a4,0(sp) +80000170: fff00493 li s1,-1 +80000174: 4405 li s0,1 +80000176: 8c45 or s0,s0,s1 +80000178: c222 sw s0,4(sp) +8000017a: fff00613 li a2,-1 +8000017e: fff00593 li a1,-1 +80000182: 8dd1 or a1,a1,a2 +80000184: c42e sw a1,8(sp) +80000186: fff00713 li a4,-1 +8000018a: 000086b7 lui a3,0x8 +8000018e: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +80000192: 8ed9 or a3,a3,a4 +80000194: c636 sw a3,12(sp) +80000196: fff00413 li s0,-1 +8000019a: 67a1 lui a5,0x8 +8000019c: 8fc1 or a5,a5,s0 +8000019e: c83e sw a5,16(sp) +800001a0: 00001117 auipc sp,0x1 +800001a4: e9c10113 addi sp,sp,-356 # 8000103c +800001a8: 000085b7 lui a1,0x8 +800001ac: fff58593 addi a1,a1,-1 # 7fff <_start-0x7fff8001> +800001b0: 4481 li s1,0 +800001b2: 8ccd or s1,s1,a1 +800001b4: c026 sw s1,0(sp) +800001b6: 000086b7 lui a3,0x8 +800001ba: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +800001be: 4605 li a2,1 +800001c0: 8e55 or a2,a2,a3 +800001c2: c232 sw a2,4(sp) +800001c4: 000087b7 lui a5,0x8 +800001c8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800001cc: fff00713 li a4,-1 +800001d0: 8f5d or a4,a4,a5 +800001d2: c43a sw a4,8(sp) +800001d4: 000084b7 lui s1,0x8 +800001d8: fff48493 addi s1,s1,-1 # 7fff <_start-0x7fff8001> +800001dc: 00008437 lui s0,0x8 +800001e0: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> +800001e4: 8c45 or s0,s0,s1 +800001e6: c622 sw s0,12(sp) +800001e8: 00008637 lui a2,0x8 +800001ec: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +800001f0: 65a1 lui a1,0x8 +800001f2: 8dd1 or a1,a1,a2 +800001f4: c82e sw a1,16(sp) +800001f6: 00001117 auipc sp,0x1 +800001fa: e5a10113 addi sp,sp,-422 # 80001050 +800001fe: 6721 lui a4,0x8 +80000200: 4681 li a3,0 +80000202: 8ed9 or a3,a3,a4 +80000204: c036 sw a3,0(sp) +80000206: 6421 lui s0,0x8 +80000208: 4785 li a5,1 +8000020a: 8fc1 or a5,a5,s0 +8000020c: c23e sw a5,4(sp) +8000020e: 65a1 lui a1,0x8 +80000210: fff00493 li s1,-1 +80000214: 8ccd or s1,s1,a1 +80000216: c426 sw s1,8(sp) +80000218: 66a1 lui a3,0x8 +8000021a: 00008637 lui a2,0x8 +8000021e: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +80000222: 8e55 or a2,a2,a3 +80000224: c632 sw a2,12(sp) +80000226: 67a1 lui a5,0x8 +80000228: 6721 lui a4,0x8 +8000022a: 8f5d or a4,a4,a5 +8000022c: c83a sw a4,16(sp) +8000022e: 00001517 auipc a0,0x1 +80000232: dd250513 addi a0,a0,-558 # 80001000 +80000236: 00001597 auipc a1,0x1 +8000023a: e3a58593 addi a1,a1,-454 # 80001070 <_end> +8000023e: f0100637 lui a2,0xf0100 +80000242: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +80000246 : +80000246: 00b50c63 beq a0,a1,8000025e +8000024a: 4554 lw a3,12(a0) +8000024c: c214 sw a3,0(a2) +8000024e: 4514 lw a3,8(a0) +80000250: c214 sw a3,0(a2) +80000252: 4154 lw a3,4(a0) +80000254: c214 sw a3,0(a2) +80000256: 4114 lw a3,0(a0) +80000258: c214 sw a3,0(a2) +8000025a: 0541 addi a0,a0,16 +8000025c: b7ed j 80000246 + +8000025e : +8000025e: f0100537 lui a0,0xf0100 +80000262: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000266: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.SLLI.elf.objdump b/src/test/resources/asm/C.SLLI.elf.objdump new file mode 100644 index 0000000..a0f3226 --- /dev/null +++ b/src/test/resources/asm/C.SLLI.elf.objdump @@ -0,0 +1,304 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.SLLI.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4181 li gp,0 +800000f8: 0186 slli gp,gp,0x1 +800000fa: c00e sw gp,0(sp) +800000fc: 4201 li tp,0 +800000fe: 020a slli tp,tp,0x2 +80000100: c212 sw tp,4(sp) +80000102: 4401 li s0,0 +80000104: 043e slli s0,s0,0xf +80000106: c422 sw s0,8(sp) +80000108: 4481 li s1,0 +8000010a: 04c2 slli s1,s1,0x10 +8000010c: c626 sw s1,12(sp) +8000010e: 4581 li a1,0 +80000110: 05fe slli a1,a1,0x1f +80000112: c82e sw a1,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f0010113 addi sp,sp,-256 # 80001014 +8000011c: 4605 li a2,1 +8000011e: 0606 slli a2,a2,0x1 +80000120: c032 sw a2,0(sp) +80000122: 4685 li a3,1 +80000124: 068a slli a3,a3,0x2 +80000126: c236 sw a3,4(sp) +80000128: 4705 li a4,1 +8000012a: 073e slli a4,a4,0xf +8000012c: c43a sw a4,8(sp) +8000012e: 4785 li a5,1 +80000130: 07c2 slli a5,a5,0x10 +80000132: c63e sw a5,12(sp) +80000134: 4805 li a6,1 +80000136: 087e slli a6,a6,0x1f +80000138: c842 sw a6,16(sp) +8000013a: 00001117 auipc sp,0x1 +8000013e: eee10113 addi sp,sp,-274 # 80001028 +80000142: fff00893 li a7,-1 +80000146: 0886 slli a7,a7,0x1 +80000148: c046 sw a7,0(sp) +8000014a: fff00913 li s2,-1 +8000014e: 090a slli s2,s2,0x2 +80000150: c24a sw s2,4(sp) +80000152: fff00993 li s3,-1 +80000156: 09be slli s3,s3,0xf +80000158: c44e sw s3,8(sp) +8000015a: fff00a13 li s4,-1 +8000015e: 0a42 slli s4,s4,0x10 +80000160: c652 sw s4,12(sp) +80000162: fff00a93 li s5,-1 +80000166: 0afe slli s5,s5,0x1f +80000168: c856 sw s5,16(sp) +8000016a: 00001117 auipc sp,0x1 +8000016e: ed210113 addi sp,sp,-302 # 8000103c +80000172: 00080b37 lui s6,0x80 +80000176: fffb0b13 addi s6,s6,-1 # 7ffff <_start-0x7ff80001> +8000017a: 0b06 slli s6,s6,0x1 +8000017c: c05a sw s6,0(sp) +8000017e: 00080bb7 lui s7,0x80 +80000182: fffb8b93 addi s7,s7,-1 # 7ffff <_start-0x7ff80001> +80000186: 0b8a slli s7,s7,0x2 +80000188: c25e sw s7,4(sp) +8000018a: 00080c37 lui s8,0x80 +8000018e: fffc0c13 addi s8,s8,-1 # 7ffff <_start-0x7ff80001> +80000192: 0c3e slli s8,s8,0xf +80000194: c462 sw s8,8(sp) +80000196: 00080cb7 lui s9,0x80 +8000019a: fffc8c93 addi s9,s9,-1 # 7ffff <_start-0x7ff80001> +8000019e: 0cc2 slli s9,s9,0x10 +800001a0: c666 sw s9,12(sp) +800001a2: 00080d37 lui s10,0x80 +800001a6: fffd0d13 addi s10,s10,-1 # 7ffff <_start-0x7ff80001> +800001aa: 0d7e slli s10,s10,0x1f +800001ac: c86a sw s10,16(sp) +800001ae: 00001117 auipc sp,0x1 +800001b2: ea210113 addi sp,sp,-350 # 80001050 +800001b6: 00080db7 lui s11,0x80 +800001ba: 0d86 slli s11,s11,0x1 +800001bc: c06e sw s11,0(sp) +800001be: 00080e37 lui t3,0x80 +800001c2: 0e0a slli t3,t3,0x2 +800001c4: c272 sw t3,4(sp) +800001c6: 00080eb7 lui t4,0x80 +800001ca: 0ebe slli t4,t4,0xf +800001cc: c476 sw t4,8(sp) +800001ce: 00080f37 lui t5,0x80 +800001d2: 0f42 slli t5,t5,0x10 +800001d4: c67a sw t5,12(sp) +800001d6: 00080fb7 lui t6,0x80 +800001da: 0ffe slli t6,t6,0x1f +800001dc: c87e sw t6,16(sp) +800001de: 00001517 auipc a0,0x1 +800001e2: e2250513 addi a0,a0,-478 # 80001000 +800001e6: 00001597 auipc a1,0x1 +800001ea: e8a58593 addi a1,a1,-374 # 80001070 <_end> +800001ee: f0100637 lui a2,0xf0100 +800001f2: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +800001f6 : +800001f6: 00b50c63 beq a0,a1,8000020e +800001fa: 4554 lw a3,12(a0) +800001fc: c214 sw a3,0(a2) +800001fe: 4514 lw a3,8(a0) +80000200: c214 sw a3,0(a2) +80000202: 4154 lw a3,4(a0) +80000204: c214 sw a3,0(a2) +80000206: 4114 lw a3,0(a0) +80000208: c214 sw a3,0(a2) +8000020a: 0541 addi a0,a0,16 +8000020c: b7ed j 800001f6 + +8000020e : +8000020e: f0100537 lui a0,0xf0100 +80000212: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000216: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.SRAI.elf.objdump b/src/test/resources/asm/C.SRAI.elf.objdump new file mode 100644 index 0000000..b5a4de3 --- /dev/null +++ b/src/test/resources/asm/C.SRAI.elf.objdump @@ -0,0 +1,304 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.SRAI.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4481 li s1,0 +800000f8: 8485 srai s1,s1,0x1 +800000fa: c026 sw s1,0(sp) +800000fc: 4581 li a1,0 +800000fe: 8589 srai a1,a1,0x2 +80000100: c22e sw a1,4(sp) +80000102: 4601 li a2,0 +80000104: 863d srai a2,a2,0xf +80000106: c432 sw a2,8(sp) +80000108: 4681 li a3,0 +8000010a: 86c1 srai a3,a3,0x10 +8000010c: c636 sw a3,12(sp) +8000010e: 4701 li a4,0 +80000110: 877d srai a4,a4,0x1f +80000112: c83a sw a4,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f0010113 addi sp,sp,-256 # 80001014 +8000011c: 4785 li a5,1 +8000011e: 8785 srai a5,a5,0x1 +80000120: c03e sw a5,0(sp) +80000122: 4405 li s0,1 +80000124: 8409 srai s0,s0,0x2 +80000126: c222 sw s0,4(sp) +80000128: 4485 li s1,1 +8000012a: 84bd srai s1,s1,0xf +8000012c: c426 sw s1,8(sp) +8000012e: 4585 li a1,1 +80000130: 85c1 srai a1,a1,0x10 +80000132: c62e sw a1,12(sp) +80000134: 4605 li a2,1 +80000136: 867d srai a2,a2,0x1f +80000138: c832 sw a2,16(sp) +8000013a: 00001117 auipc sp,0x1 +8000013e: eee10113 addi sp,sp,-274 # 80001028 +80000142: fff00693 li a3,-1 +80000146: 8685 srai a3,a3,0x1 +80000148: c036 sw a3,0(sp) +8000014a: fff00713 li a4,-1 +8000014e: 8709 srai a4,a4,0x2 +80000150: c23a sw a4,4(sp) +80000152: fff00793 li a5,-1 +80000156: 87bd srai a5,a5,0xf +80000158: c43e sw a5,8(sp) +8000015a: fff00413 li s0,-1 +8000015e: 8441 srai s0,s0,0x10 +80000160: c622 sw s0,12(sp) +80000162: fff00493 li s1,-1 +80000166: 84fd srai s1,s1,0x1f +80000168: c826 sw s1,16(sp) +8000016a: 00001117 auipc sp,0x1 +8000016e: ed210113 addi sp,sp,-302 # 8000103c +80000172: 000805b7 lui a1,0x80 +80000176: fff58593 addi a1,a1,-1 # 7ffff <_start-0x7ff80001> +8000017a: 8585 srai a1,a1,0x1 +8000017c: c02e sw a1,0(sp) +8000017e: 00080637 lui a2,0x80 +80000182: fff60613 addi a2,a2,-1 # 7ffff <_start-0x7ff80001> +80000186: 8609 srai a2,a2,0x2 +80000188: c232 sw a2,4(sp) +8000018a: 000806b7 lui a3,0x80 +8000018e: fff68693 addi a3,a3,-1 # 7ffff <_start-0x7ff80001> +80000192: 86bd srai a3,a3,0xf +80000194: c436 sw a3,8(sp) +80000196: 00080737 lui a4,0x80 +8000019a: fff70713 addi a4,a4,-1 # 7ffff <_start-0x7ff80001> +8000019e: 8741 srai a4,a4,0x10 +800001a0: c63a sw a4,12(sp) +800001a2: 000807b7 lui a5,0x80 +800001a6: fff78793 addi a5,a5,-1 # 7ffff <_start-0x7ff80001> +800001aa: 87fd srai a5,a5,0x1f +800001ac: c83e sw a5,16(sp) +800001ae: 00001117 auipc sp,0x1 +800001b2: ea210113 addi sp,sp,-350 # 80001050 +800001b6: 00080437 lui s0,0x80 +800001ba: 8405 srai s0,s0,0x1 +800001bc: c022 sw s0,0(sp) +800001be: 000804b7 lui s1,0x80 +800001c2: 8489 srai s1,s1,0x2 +800001c4: c226 sw s1,4(sp) +800001c6: 000805b7 lui a1,0x80 +800001ca: 85bd srai a1,a1,0xf +800001cc: c42e sw a1,8(sp) +800001ce: 00080637 lui a2,0x80 +800001d2: 8641 srai a2,a2,0x10 +800001d4: c632 sw a2,12(sp) +800001d6: 000806b7 lui a3,0x80 +800001da: 86fd srai a3,a3,0x1f +800001dc: c836 sw a3,16(sp) +800001de: 00001517 auipc a0,0x1 +800001e2: e2250513 addi a0,a0,-478 # 80001000 +800001e6: 00001597 auipc a1,0x1 +800001ea: e8a58593 addi a1,a1,-374 # 80001070 <_end> +800001ee: f0100637 lui a2,0xf0100 +800001f2: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +800001f6 : +800001f6: 00b50c63 beq a0,a1,8000020e +800001fa: 4554 lw a3,12(a0) +800001fc: c214 sw a3,0(a2) +800001fe: 4514 lw a3,8(a0) +80000200: c214 sw a3,0(a2) +80000202: 4154 lw a3,4(a0) +80000204: c214 sw a3,0(a2) +80000206: 4114 lw a3,0(a0) +80000208: c214 sw a3,0(a2) +8000020a: 0541 addi a0,a0,16 +8000020c: b7ed j 800001f6 + +8000020e : +8000020e: f0100537 lui a0,0xf0100 +80000212: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000216: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.SRLI.elf.objdump b/src/test/resources/asm/C.SRLI.elf.objdump new file mode 100644 index 0000000..ac89194 --- /dev/null +++ b/src/test/resources/asm/C.SRLI.elf.objdump @@ -0,0 +1,304 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.SRLI.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4701 li a4,0 +800000f8: 8305 srli a4,a4,0x1 +800000fa: c03a sw a4,0(sp) +800000fc: 4781 li a5,0 +800000fe: 8389 srli a5,a5,0x2 +80000100: c23e sw a5,4(sp) +80000102: 4401 li s0,0 +80000104: 803d srli s0,s0,0xf +80000106: c422 sw s0,8(sp) +80000108: 4481 li s1,0 +8000010a: 80c1 srli s1,s1,0x10 +8000010c: c626 sw s1,12(sp) +8000010e: 4581 li a1,0 +80000110: 81fd srli a1,a1,0x1f +80000112: c82e sw a1,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f0010113 addi sp,sp,-256 # 80001014 +8000011c: 4605 li a2,1 +8000011e: 8205 srli a2,a2,0x1 +80000120: c032 sw a2,0(sp) +80000122: 4685 li a3,1 +80000124: 8289 srli a3,a3,0x2 +80000126: c236 sw a3,4(sp) +80000128: 4705 li a4,1 +8000012a: 833d srli a4,a4,0xf +8000012c: c43a sw a4,8(sp) +8000012e: 4785 li a5,1 +80000130: 83c1 srli a5,a5,0x10 +80000132: c63e sw a5,12(sp) +80000134: 4405 li s0,1 +80000136: 807d srli s0,s0,0x1f +80000138: c822 sw s0,16(sp) +8000013a: 00001117 auipc sp,0x1 +8000013e: eee10113 addi sp,sp,-274 # 80001028 +80000142: fff00493 li s1,-1 +80000146: 8085 srli s1,s1,0x1 +80000148: c026 sw s1,0(sp) +8000014a: fff00593 li a1,-1 +8000014e: 8189 srli a1,a1,0x2 +80000150: c22e sw a1,4(sp) +80000152: fff00613 li a2,-1 +80000156: 823d srli a2,a2,0xf +80000158: c432 sw a2,8(sp) +8000015a: fff00693 li a3,-1 +8000015e: 82c1 srli a3,a3,0x10 +80000160: c636 sw a3,12(sp) +80000162: fff00713 li a4,-1 +80000166: 837d srli a4,a4,0x1f +80000168: c83a sw a4,16(sp) +8000016a: 00001117 auipc sp,0x1 +8000016e: ed210113 addi sp,sp,-302 # 8000103c +80000172: 000807b7 lui a5,0x80 +80000176: fff78793 addi a5,a5,-1 # 7ffff <_start-0x7ff80001> +8000017a: 8385 srli a5,a5,0x1 +8000017c: c03e sw a5,0(sp) +8000017e: 00080437 lui s0,0x80 +80000182: fff40413 addi s0,s0,-1 # 7ffff <_start-0x7ff80001> +80000186: 8009 srli s0,s0,0x2 +80000188: c222 sw s0,4(sp) +8000018a: 000804b7 lui s1,0x80 +8000018e: fff48493 addi s1,s1,-1 # 7ffff <_start-0x7ff80001> +80000192: 80bd srli s1,s1,0xf +80000194: c426 sw s1,8(sp) +80000196: 000805b7 lui a1,0x80 +8000019a: fff58593 addi a1,a1,-1 # 7ffff <_start-0x7ff80001> +8000019e: 81c1 srli a1,a1,0x10 +800001a0: c62e sw a1,12(sp) +800001a2: 00080637 lui a2,0x80 +800001a6: fff60613 addi a2,a2,-1 # 7ffff <_start-0x7ff80001> +800001aa: 827d srli a2,a2,0x1f +800001ac: c832 sw a2,16(sp) +800001ae: 00001117 auipc sp,0x1 +800001b2: ea210113 addi sp,sp,-350 # 80001050 +800001b6: 000806b7 lui a3,0x80 +800001ba: 8285 srli a3,a3,0x1 +800001bc: c036 sw a3,0(sp) +800001be: 00080737 lui a4,0x80 +800001c2: 8309 srli a4,a4,0x2 +800001c4: c23a sw a4,4(sp) +800001c6: 000807b7 lui a5,0x80 +800001ca: 83bd srli a5,a5,0xf +800001cc: c43e sw a5,8(sp) +800001ce: 00080437 lui s0,0x80 +800001d2: 8041 srli s0,s0,0x10 +800001d4: c622 sw s0,12(sp) +800001d6: 000804b7 lui s1,0x80 +800001da: 80fd srli s1,s1,0x1f +800001dc: c826 sw s1,16(sp) +800001de: 00001517 auipc a0,0x1 +800001e2: e2250513 addi a0,a0,-478 # 80001000 +800001e6: 00001597 auipc a1,0x1 +800001ea: e8a58593 addi a1,a1,-374 # 80001070 <_end> +800001ee: f0100637 lui a2,0xf0100 +800001f2: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +800001f6 : +800001f6: 00b50c63 beq a0,a1,8000020e +800001fa: 4554 lw a3,12(a0) +800001fc: c214 sw a3,0(a2) +800001fe: 4514 lw a3,8(a0) +80000200: c214 sw a3,0(a2) +80000202: 4154 lw a3,4(a0) +80000204: c214 sw a3,0(a2) +80000206: 4114 lw a3,0(a0) +80000208: c214 sw a3,0(a2) +8000020a: 0541 addi a0,a0,16 +8000020c: b7ed j 800001f6 + +8000020e : +8000020e: f0100537 lui a0,0xf0100 +80000212: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000216: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.SUB.elf.objdump b/src/test/resources/asm/C.SUB.elf.objdump new file mode 100644 index 0000000..800d933 --- /dev/null +++ b/src/test/resources/asm/C.SUB.elf.objdump @@ -0,0 +1,334 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.SUB.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4581 li a1,0 +800000f8: 4481 li s1,0 +800000fa: 8c8d sub s1,s1,a1 +800000fc: c026 sw s1,0(sp) +800000fe: 4681 li a3,0 +80000100: 4605 li a2,1 +80000102: 8e15 sub a2,a2,a3 +80000104: c232 sw a2,4(sp) +80000106: 4781 li a5,0 +80000108: fff00713 li a4,-1 +8000010c: 8f1d sub a4,a4,a5 +8000010e: c43a sw a4,8(sp) +80000110: 4481 li s1,0 +80000112: 00008437 lui s0,0x8 +80000116: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> +8000011a: 8c05 sub s0,s0,s1 +8000011c: c622 sw s0,12(sp) +8000011e: 4601 li a2,0 +80000120: 65a1 lui a1,0x8 +80000122: 8d91 sub a1,a1,a2 +80000124: c82e sw a1,16(sp) +80000126: 00001117 auipc sp,0x1 +8000012a: eee10113 addi sp,sp,-274 # 80001014 +8000012e: 4705 li a4,1 +80000130: 4681 li a3,0 +80000132: 8e99 sub a3,a3,a4 +80000134: c036 sw a3,0(sp) +80000136: 4405 li s0,1 +80000138: 4785 li a5,1 +8000013a: 8f81 sub a5,a5,s0 +8000013c: c23e sw a5,4(sp) +8000013e: 4585 li a1,1 +80000140: fff00493 li s1,-1 +80000144: 8c8d sub s1,s1,a1 +80000146: c426 sw s1,8(sp) +80000148: 4685 li a3,1 +8000014a: 00008637 lui a2,0x8 +8000014e: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +80000152: 8e15 sub a2,a2,a3 +80000154: c632 sw a2,12(sp) +80000156: 4785 li a5,1 +80000158: 6721 lui a4,0x8 +8000015a: 8f1d sub a4,a4,a5 +8000015c: c83a sw a4,16(sp) +8000015e: 00001117 auipc sp,0x1 +80000162: eca10113 addi sp,sp,-310 # 80001028 +80000166: fff00493 li s1,-1 +8000016a: 4401 li s0,0 +8000016c: 8c05 sub s0,s0,s1 +8000016e: c022 sw s0,0(sp) +80000170: fff00613 li a2,-1 +80000174: 4585 li a1,1 +80000176: 8d91 sub a1,a1,a2 +80000178: c22e sw a1,4(sp) +8000017a: fff00713 li a4,-1 +8000017e: fff00693 li a3,-1 +80000182: 8e99 sub a3,a3,a4 +80000184: c436 sw a3,8(sp) +80000186: fff00413 li s0,-1 +8000018a: 000087b7 lui a5,0x8 +8000018e: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80000192: 8f81 sub a5,a5,s0 +80000194: c63e sw a5,12(sp) +80000196: fff00593 li a1,-1 +8000019a: 64a1 lui s1,0x8 +8000019c: 8c8d sub s1,s1,a1 +8000019e: c826 sw s1,16(sp) +800001a0: 00001117 auipc sp,0x1 +800001a4: e9c10113 addi sp,sp,-356 # 8000103c +800001a8: 000086b7 lui a3,0x8 +800001ac: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +800001b0: 4601 li a2,0 +800001b2: 8e15 sub a2,a2,a3 +800001b4: c032 sw a2,0(sp) +800001b6: 000087b7 lui a5,0x8 +800001ba: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800001be: 4705 li a4,1 +800001c0: 8f1d sub a4,a4,a5 +800001c2: c23a sw a4,4(sp) +800001c4: 000084b7 lui s1,0x8 +800001c8: fff48493 addi s1,s1,-1 # 7fff <_start-0x7fff8001> +800001cc: fff00413 li s0,-1 +800001d0: 8c05 sub s0,s0,s1 +800001d2: c422 sw s0,8(sp) +800001d4: 00008637 lui a2,0x8 +800001d8: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +800001dc: 000085b7 lui a1,0x8 +800001e0: fff58593 addi a1,a1,-1 # 7fff <_start-0x7fff8001> +800001e4: 8d91 sub a1,a1,a2 +800001e6: c62e sw a1,12(sp) +800001e8: 00008737 lui a4,0x8 +800001ec: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +800001f0: 66a1 lui a3,0x8 +800001f2: 8e99 sub a3,a3,a4 +800001f4: c836 sw a3,16(sp) +800001f6: 00001117 auipc sp,0x1 +800001fa: e5a10113 addi sp,sp,-422 # 80001050 +800001fe: 6421 lui s0,0x8 +80000200: 4781 li a5,0 +80000202: 8f81 sub a5,a5,s0 +80000204: c03e sw a5,0(sp) +80000206: 65a1 lui a1,0x8 +80000208: 4485 li s1,1 +8000020a: 8c8d sub s1,s1,a1 +8000020c: c226 sw s1,4(sp) +8000020e: 66a1 lui a3,0x8 +80000210: fff00613 li a2,-1 +80000214: 8e15 sub a2,a2,a3 +80000216: c432 sw a2,8(sp) +80000218: 67a1 lui a5,0x8 +8000021a: 00008737 lui a4,0x8 +8000021e: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80000222: 8f1d sub a4,a4,a5 +80000224: c63a sw a4,12(sp) +80000226: 64a1 lui s1,0x8 +80000228: 6421 lui s0,0x8 +8000022a: 8c05 sub s0,s0,s1 +8000022c: c822 sw s0,16(sp) +8000022e: 00001517 auipc a0,0x1 +80000232: dd250513 addi a0,a0,-558 # 80001000 +80000236: 00001597 auipc a1,0x1 +8000023a: e3a58593 addi a1,a1,-454 # 80001070 <_end> +8000023e: f0100637 lui a2,0xf0100 +80000242: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +80000246 : +80000246: 00b50c63 beq a0,a1,8000025e +8000024a: 4554 lw a3,12(a0) +8000024c: c214 sw a3,0(a2) +8000024e: 4514 lw a3,8(a0) +80000250: c214 sw a3,0(a2) +80000252: 4154 lw a3,4(a0) +80000254: c214 sw a3,0(a2) +80000256: 4114 lw a3,0(a0) +80000258: c214 sw a3,0(a2) +8000025a: 0541 addi a0,a0,16 +8000025c: b7ed j 80000246 + +8000025e : +8000025e: f0100537 lui a0,0xf0100 +80000262: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000266: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.SW.elf.objdump b/src/test/resources/asm/C.SW.elf.objdump new file mode 100644 index 0000000..4ab3204 --- /dev/null +++ b/src/test/resources/asm/C.SW.elf.objdump @@ -0,0 +1,281 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.SW.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4401 li s0,0 +800000f8: 00001617 auipc a2,0x1 +800000fc: f1c60613 addi a2,a2,-228 # 80001014 +80000100: c200 sw s0,0(a2) +80000102: 4200 lw s0,0(a2) +80000104: c022 sw s0,0(sp) +80000106: 00001117 auipc sp,0x1 +8000010a: efe10113 addi sp,sp,-258 # 80001004 +8000010e: 4485 li s1,1 +80000110: 00001797 auipc a5,0x1 +80000114: f0478793 addi a5,a5,-252 # 80001014 +80000118: c3c4 sw s1,4(a5) +8000011a: 43c4 lw s1,4(a5) +8000011c: c026 sw s1,0(sp) +8000011e: 00001117 auipc sp,0x1 +80000122: eea10113 addi sp,sp,-278 # 80001008 +80000126: 557d li a0,-1 +80000128: 00001497 auipc s1,0x1 +8000012c: eec48493 addi s1,s1,-276 # 80001014 +80000130: c488 sw a0,8(s1) +80000132: 4488 lw a0,8(s1) +80000134: c02a sw a0,0(sp) +80000136: 00001117 auipc sp,0x1 +8000013a: ed610113 addi sp,sp,-298 # 8000100c +8000013e: 000086b7 lui a3,0x8 +80000142: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +80000146: 00001717 auipc a4,0x1 +8000014a: ece70713 addi a4,a4,-306 # 80001014 +8000014e: cb14 sw a3,16(a4) +80000150: 4b14 lw a3,16(a4) +80000152: c036 sw a3,0(sp) +80000154: 00001117 auipc sp,0x1 +80000158: ebc10113 addi sp,sp,-324 # 80001010 +8000015c: 67a1 lui a5,0x8 +8000015e: 00001617 auipc a2,0x1 +80000162: eb660613 addi a2,a2,-330 # 80001014 +80000166: de7c sw a5,124(a2) +80000168: 5e7c lw a5,124(a2) +8000016a: c03e sw a5,0(sp) +8000016c: 00001517 auipc a0,0x1 +80000170: e9450513 addi a0,a0,-364 # 80001000 +80000174: 00001597 auipc a1,0x1 +80000178: f2c58593 addi a1,a1,-212 # 800010a0 <_end> +8000017c: f0100637 lui a2,0xf0100 +80000180: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee8c> + +80000184 : +80000184: 00b50c63 beq a0,a1,8000019c +80000188: 4554 lw a3,12(a0) +8000018a: c214 sw a3,0(a2) +8000018c: 4514 lw a3,8(a0) +8000018e: c214 sw a3,0(a2) +80000190: 4154 lw a3,4(a0) +80000192: c214 sw a3,0(a2) +80000194: 4114 lw a3,0(a0) +80000196: c214 sw a3,0(a2) +80000198: 0541 addi a0,a0,16 +8000019a: b7ed j 80000184 + +8000019c : +8000019c: f0100537 lui a0,0xf0100 +800001a0: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee80> +800001a4: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.SWSP.elf.objdump b/src/test/resources/asm/C.SWSP.elf.objdump new file mode 100644 index 0000000..ae87ddd --- /dev/null +++ b/src/test/resources/asm/C.SWSP.elf.objdump @@ -0,0 +1,280 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.SWSP.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001097 auipc ra,0x1 +800000f2: f1208093 addi ra,ra,-238 # 80001000 +800000f6: 00001117 auipc sp,0x1 +800000fa: f1e10113 addi sp,sp,-226 # 80001014 +800000fe: 4181 li gp,0 +80000100: c00e sw gp,0(sp) +80000102: 4182 lw gp,0(sp) +80000104: 0030a023 sw gp,0(ra) +80000108: 00001097 auipc ra,0x1 +8000010c: efc08093 addi ra,ra,-260 # 80001004 +80000110: 00001117 auipc sp,0x1 +80000114: f0410113 addi sp,sp,-252 # 80001014 +80000118: 4205 li tp,1 +8000011a: c212 sw tp,4(sp) +8000011c: 4212 lw tp,4(sp) +8000011e: 0040a023 sw tp,0(ra) +80000122: 00001097 auipc ra,0x1 +80000126: ee608093 addi ra,ra,-282 # 80001008 +8000012a: 00001117 auipc sp,0x1 +8000012e: eea10113 addi sp,sp,-278 # 80001014 +80000132: 587d li a6,-1 +80000134: c0c2 sw a6,64(sp) +80000136: 4806 lw a6,64(sp) +80000138: 0100a023 sw a6,0(ra) +8000013c: 00001097 auipc ra,0x1 +80000140: ed008093 addi ra,ra,-304 # 8000100c +80000144: 00001117 auipc sp,0x1 +80000148: ed010113 addi sp,sp,-304 # 80001014 +8000014c: 00008c37 lui s8,0x8 +80000150: fffc0c13 addi s8,s8,-1 # 7fff <_start-0x7fff8001> +80000154: dce2 sw s8,120(sp) +80000156: 5c66 lw s8,120(sp) +80000158: 0180a023 sw s8,0(ra) +8000015c: 00001097 auipc ra,0x1 +80000160: eb408093 addi ra,ra,-332 # 80001010 +80000164: 00001117 auipc sp,0x1 +80000168: eb010113 addi sp,sp,-336 # 80001014 +8000016c: 6fa1 lui t6,0x8 +8000016e: dffe sw t6,252(sp) +80000170: 5ffe lw t6,252(sp) +80000172: 01f0a023 sw t6,0(ra) +80000176: 00001517 auipc a0,0x1 +8000017a: e8a50513 addi a0,a0,-374 # 80001000 +8000017e: 00001597 auipc a1,0x1 +80000182: f2258593 addi a1,a1,-222 # 800010a0 <_end> +80000186: f0100637 lui a2,0xf0100 +8000018a: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee8c> + +8000018e : +8000018e: 00b50c63 beq a0,a1,800001a6 +80000192: 4554 lw a3,12(a0) +80000194: c214 sw a3,0(a2) +80000196: 4514 lw a3,8(a0) +80000198: c214 sw a3,0(a2) +8000019a: 4154 lw a3,4(a0) +8000019c: c214 sw a3,0(a2) +8000019e: 4114 lw a3,0(a0) +800001a0: c214 sw a3,0(a2) +800001a2: 0541 addi a0,a0,16 +800001a4: b7ed j 8000018e + +800001a6 : +800001a6: f0100537 lui a0,0xf0100 +800001aa: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee80> +800001ae: 00052023 sw zero,0(a0) + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff + +80001004 : +80001004: ffff 0xffff +80001006: ffff 0xffff + +80001008 : +80001008: ffff 0xffff +8000100a: ffff 0xffff + +8000100c : +8000100c: ffff 0xffff +8000100e: ffff 0xffff + +80001010 : +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff + ... diff --git a/src/test/resources/asm/C.XOR.elf.objdump b/src/test/resources/asm/C.XOR.elf.objdump new file mode 100644 index 0000000..b60bcb6 --- /dev/null +++ b/src/test/resources/asm/C.XOR.elf.objdump @@ -0,0 +1,334 @@ + +/home/spinalvm/hdl/riscv-compliance/work//C.XOR.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 0001 nop +80000002: 0001 nop +80000004: 0001 nop +80000006: 0001 nop +80000008: 0001 nop +8000000a: 0001 nop +8000000c: 0001 nop +8000000e: 0001 nop +80000010: 0001 nop +80000012: 0001 nop +80000014: 0001 nop +80000016: 0001 nop +80000018: 0001 nop +8000001a: 0001 nop +8000001c: 0001 nop +8000001e: 0001 nop +80000020: 0001 nop +80000022: 0001 nop +80000024: 0001 nop +80000026: 0001 nop +80000028: 0001 nop +8000002a: 0001 nop +8000002c: 0001 nop +8000002e: 0001 nop +80000030: 0001 nop +80000032: 0001 nop +80000034: 0001 nop +80000036: 0001 nop +80000038: 0001 nop +8000003a: 0001 nop +8000003c: 0001 nop +8000003e: 0001 nop +80000040: 0001 nop +80000042: 0001 nop +80000044: 0001 nop +80000046: 0001 nop +80000048: 0001 nop +8000004a: 0001 nop +8000004c: 0001 nop +8000004e: 0001 nop +80000050: 0001 nop +80000052: 0001 nop +80000054: 0001 nop +80000056: 0001 nop +80000058: 0001 nop +8000005a: 0001 nop +8000005c: 0001 nop +8000005e: 0001 nop +80000060: 0001 nop +80000062: 0001 nop +80000064: 0001 nop +80000066: 0001 nop +80000068: 0001 nop +8000006a: 0001 nop +8000006c: 0001 nop +8000006e: 0001 nop +80000070: 0001 nop +80000072: 0001 nop +80000074: 0001 nop +80000076: 0001 nop +80000078: 0001 nop +8000007a: 0001 nop +8000007c: 0001 nop +8000007e: 0001 nop +80000080: 0001 nop +80000082: 0001 nop +80000084: 0001 nop +80000086: 0001 nop +80000088: 0001 nop +8000008a: 0001 nop +8000008c: 0001 nop +8000008e: 0001 nop +80000090: 0001 nop +80000092: 0001 nop +80000094: 0001 nop +80000096: 0001 nop +80000098: 0001 nop +8000009a: 0001 nop +8000009c: 0001 nop +8000009e: 0001 nop +800000a0: 0001 nop +800000a2: 0001 nop +800000a4: 0001 nop +800000a6: 0001 nop +800000a8: 0001 nop +800000aa: 0001 nop +800000ac: 0001 nop +800000ae: 0001 nop +800000b0: 0001 nop +800000b2: 0001 nop +800000b4: 0001 nop +800000b6: 0001 nop +800000b8: 0001 nop +800000ba: 0001 nop +800000bc: 0001 nop +800000be: 0001 nop +800000c0: 0001 nop +800000c2: 0001 nop +800000c4: 0001 nop +800000c6: 0001 nop +800000c8: 0001 nop +800000ca: 0001 nop +800000cc: 0001 nop +800000ce: 0001 nop +800000d0: 0001 nop +800000d2: 0001 nop +800000d4: 0001 nop +800000d6: 0001 nop +800000d8: 0001 nop +800000da: 0001 nop +800000dc: 0001 nop +800000de: 0001 nop +800000e0: 0001 nop +800000e2: 0001 nop +800000e4: 0001 nop +800000e6: 0001 nop +800000e8: 0001 nop +800000ea: 0001 nop +800000ec: 0001 nop +800000ee: 00001117 auipc sp,0x1 +800000f2: f1210113 addi sp,sp,-238 # 80001000 +800000f6: 4481 li s1,0 +800000f8: 4401 li s0,0 +800000fa: 8c25 xor s0,s0,s1 +800000fc: c022 sw s0,0(sp) +800000fe: 4601 li a2,0 +80000100: 4585 li a1,1 +80000102: 8db1 xor a1,a1,a2 +80000104: c22e sw a1,4(sp) +80000106: 4701 li a4,0 +80000108: fff00693 li a3,-1 +8000010c: 8eb9 xor a3,a3,a4 +8000010e: c436 sw a3,8(sp) +80000110: 4401 li s0,0 +80000112: 000087b7 lui a5,0x8 +80000116: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +8000011a: 8fa1 xor a5,a5,s0 +8000011c: c63e sw a5,12(sp) +8000011e: 4581 li a1,0 +80000120: 64a1 lui s1,0x8 +80000122: 8cad xor s1,s1,a1 +80000124: c826 sw s1,16(sp) +80000126: 00001117 auipc sp,0x1 +8000012a: eee10113 addi sp,sp,-274 # 80001014 +8000012e: 4685 li a3,1 +80000130: 4601 li a2,0 +80000132: 8e35 xor a2,a2,a3 +80000134: c032 sw a2,0(sp) +80000136: 4785 li a5,1 +80000138: 4705 li a4,1 +8000013a: 8f3d xor a4,a4,a5 +8000013c: c23a sw a4,4(sp) +8000013e: 4485 li s1,1 +80000140: fff00413 li s0,-1 +80000144: 8c25 xor s0,s0,s1 +80000146: c422 sw s0,8(sp) +80000148: 4605 li a2,1 +8000014a: 000085b7 lui a1,0x8 +8000014e: fff58593 addi a1,a1,-1 # 7fff <_start-0x7fff8001> +80000152: 8db1 xor a1,a1,a2 +80000154: c62e sw a1,12(sp) +80000156: 4705 li a4,1 +80000158: 66a1 lui a3,0x8 +8000015a: 8eb9 xor a3,a3,a4 +8000015c: c836 sw a3,16(sp) +8000015e: 00001117 auipc sp,0x1 +80000162: eca10113 addi sp,sp,-310 # 80001028 +80000166: fff00413 li s0,-1 +8000016a: 4781 li a5,0 +8000016c: 8fa1 xor a5,a5,s0 +8000016e: c03e sw a5,0(sp) +80000170: fff00593 li a1,-1 +80000174: 4485 li s1,1 +80000176: 8cad xor s1,s1,a1 +80000178: c226 sw s1,4(sp) +8000017a: fff00693 li a3,-1 +8000017e: fff00613 li a2,-1 +80000182: 8e35 xor a2,a2,a3 +80000184: c432 sw a2,8(sp) +80000186: fff00793 li a5,-1 +8000018a: 00008737 lui a4,0x8 +8000018e: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80000192: 8f3d xor a4,a4,a5 +80000194: c63a sw a4,12(sp) +80000196: fff00493 li s1,-1 +8000019a: 6421 lui s0,0x8 +8000019c: 8c25 xor s0,s0,s1 +8000019e: c822 sw s0,16(sp) +800001a0: 00001117 auipc sp,0x1 +800001a4: e9c10113 addi sp,sp,-356 # 8000103c +800001a8: 00008637 lui a2,0x8 +800001ac: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +800001b0: 4581 li a1,0 +800001b2: 8db1 xor a1,a1,a2 +800001b4: c02e sw a1,0(sp) +800001b6: 00008737 lui a4,0x8 +800001ba: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +800001be: 4685 li a3,1 +800001c0: 8eb9 xor a3,a3,a4 +800001c2: c236 sw a3,4(sp) +800001c4: 00008437 lui s0,0x8 +800001c8: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> +800001cc: fff00793 li a5,-1 +800001d0: 8fa1 xor a5,a5,s0 +800001d2: c43e sw a5,8(sp) +800001d4: 000085b7 lui a1,0x8 +800001d8: fff58593 addi a1,a1,-1 # 7fff <_start-0x7fff8001> +800001dc: 000084b7 lui s1,0x8 +800001e0: fff48493 addi s1,s1,-1 # 7fff <_start-0x7fff8001> +800001e4: 8cad xor s1,s1,a1 +800001e6: c626 sw s1,12(sp) +800001e8: 000086b7 lui a3,0x8 +800001ec: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +800001f0: 6621 lui a2,0x8 +800001f2: 8e35 xor a2,a2,a3 +800001f4: c832 sw a2,16(sp) +800001f6: 00001117 auipc sp,0x1 +800001fa: e5a10113 addi sp,sp,-422 # 80001050 +800001fe: 67a1 lui a5,0x8 +80000200: 4701 li a4,0 +80000202: 8f3d xor a4,a4,a5 +80000204: c03a sw a4,0(sp) +80000206: 64a1 lui s1,0x8 +80000208: 4405 li s0,1 +8000020a: 8c25 xor s0,s0,s1 +8000020c: c222 sw s0,4(sp) +8000020e: 6621 lui a2,0x8 +80000210: fff00593 li a1,-1 +80000214: 8db1 xor a1,a1,a2 +80000216: c42e sw a1,8(sp) +80000218: 6721 lui a4,0x8 +8000021a: 000086b7 lui a3,0x8 +8000021e: fff68693 addi a3,a3,-1 # 7fff <_start-0x7fff8001> +80000222: 8eb9 xor a3,a3,a4 +80000224: c636 sw a3,12(sp) +80000226: 6421 lui s0,0x8 +80000228: 67a1 lui a5,0x8 +8000022a: 8fa1 xor a5,a5,s0 +8000022c: c83e sw a5,16(sp) +8000022e: 00001517 auipc a0,0x1 +80000232: dd250513 addi a0,a0,-558 # 80001000 +80000236: 00001597 auipc a1,0x1 +8000023a: e3a58593 addi a1,a1,-454 # 80001070 <_end> +8000023e: f0100637 lui a2,0xf0100 +80000242: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700feebc> + +80000246 : +80000246: 00b50c63 beq a0,a1,8000025e +8000024a: 4554 lw a3,12(a0) +8000024c: c214 sw a3,0(a2) +8000024e: 4514 lw a3,8(a0) +80000250: c214 sw a3,0(a2) +80000252: 4154 lw a3,4(a0) +80000254: c214 sw a3,0(a2) +80000256: 4114 lw a3,0(a0) +80000258: c214 sw a3,0(a2) +8000025a: 0541 addi a0,a0,16 +8000025c: b7ed j 80000246 + +8000025e : +8000025e: f0100537 lui a0,0xf0100 +80000262: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700feeb0> +80000266: 00052023 sw zero,0(a0) + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + ... diff --git a/src/test/resources/asm/DIV.elf.objdump b/src/test/resources/asm/DIV.elf.objdump new file mode 100644 index 0000000..9846875 --- /dev/null +++ b/src/test/resources/asm/DIV.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//DIV.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001117 auipc sp,0x1 +80000004: 00010113 mv sp,sp +80000008: 00000913 li s2,0 +8000000c: 00000893 li a7,0 +80000010: 031948b3 div a7,s2,a7 +80000014: 01112023 sw a7,0(sp) # 80001000 +80000018: 00000a13 li s4,0 +8000001c: 00100993 li s3,1 +80000020: 033a49b3 div s3,s4,s3 +80000024: 01312223 sw s3,4(sp) +80000028: 00000b13 li s6,0 +8000002c: fff00a93 li s5,-1 +80000030: 035b4ab3 div s5,s6,s5 +80000034: 01512423 sw s5,8(sp) +80000038: 00000c13 li s8,0 +8000003c: 80000bb7 lui s7,0x80000 +80000040: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000044: 037c4bb3 div s7,s8,s7 +80000048: 01712623 sw s7,12(sp) +8000004c: 00000d13 li s10,0 +80000050: 80000cb7 lui s9,0x80000 +80000054: 039d4cb3 div s9,s10,s9 +80000058: 01912823 sw s9,16(sp) +8000005c: 00001117 auipc sp,0x1 +80000060: fb810113 addi sp,sp,-72 # 80001014 +80000064: 00100e13 li t3,1 +80000068: 00000d93 li s11,0 +8000006c: 03be4db3 div s11,t3,s11 +80000070: 01b12023 sw s11,0(sp) +80000074: 00100f13 li t5,1 +80000078: 00100e93 li t4,1 +8000007c: 03df4eb3 div t4,t5,t4 +80000080: 01d12223 sw t4,4(sp) +80000084: 00100193 li gp,1 +80000088: fff00f93 li t6,-1 +8000008c: 03f1cfb3 div t6,gp,t6 +80000090: 01f12423 sw t6,8(sp) +80000094: 00100413 li s0,1 +80000098: 80000237 lui tp,0x80000 +8000009c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef2f> +800000a0: 02444233 div tp,s0,tp +800000a4: 00412623 sw tp,12(sp) +800000a8: 00100593 li a1,1 +800000ac: 800004b7 lui s1,0x80000 +800000b0: 0295c4b3 div s1,a1,s1 +800000b4: 00912823 sw s1,16(sp) +800000b8: 00001117 auipc sp,0x1 +800000bc: f7010113 addi sp,sp,-144 # 80001028 +800000c0: fff00693 li a3,-1 +800000c4: 00000613 li a2,0 +800000c8: 02c6c633 div a2,a3,a2 +800000cc: 00c12023 sw a2,0(sp) +800000d0: fff00793 li a5,-1 +800000d4: 00100713 li a4,1 +800000d8: 02e7c733 div a4,a5,a4 +800000dc: 00e12223 sw a4,4(sp) +800000e0: fff00893 li a7,-1 +800000e4: fff00813 li a6,-1 +800000e8: 0308c833 div a6,a7,a6 +800000ec: 01012423 sw a6,8(sp) +800000f0: fff00993 li s3,-1 +800000f4: 80000937 lui s2,0x80000 +800000f8: fff90913 addi s2,s2,-1 # 7fffffff <_end+0xffffef2f> +800000fc: 0329c933 div s2,s3,s2 +80000100: 01212623 sw s2,12(sp) +80000104: fff00a93 li s5,-1 +80000108: 80000a37 lui s4,0x80000 +8000010c: 034aca33 div s4,s5,s4 +80000110: 01412823 sw s4,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f2810113 addi sp,sp,-216 # 8000103c +8000011c: 80000bb7 lui s7,0x80000 +80000120: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000124: 00000b13 li s6,0 +80000128: 036bcb33 div s6,s7,s6 +8000012c: 01612023 sw s6,0(sp) +80000130: 80000cb7 lui s9,0x80000 +80000134: fffc8c93 addi s9,s9,-1 # 7fffffff <_end+0xffffef2f> +80000138: 00100c13 li s8,1 +8000013c: 038ccc33 div s8,s9,s8 +80000140: 01812223 sw s8,4(sp) +80000144: 80000db7 lui s11,0x80000 +80000148: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef2f> +8000014c: fff00d13 li s10,-1 +80000150: 03adcd33 div s10,s11,s10 +80000154: 01a12423 sw s10,8(sp) +80000158: 80000eb7 lui t4,0x80000 +8000015c: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffef2f> +80000160: 80000e37 lui t3,0x80000 +80000164: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef2f> +80000168: 03cece33 div t3,t4,t3 +8000016c: 01c12623 sw t3,12(sp) +80000170: 80000fb7 lui t6,0x80000 +80000174: ffff8f93 addi t6,t6,-1 # 7fffffff <_end+0xffffef2f> +80000178: 80000f37 lui t5,0x80000 +8000017c: 03efcf33 div t5,t6,t5 +80000180: 01e12823 sw t5,16(sp) +80000184: 00001117 auipc sp,0x1 +80000188: ecc10113 addi sp,sp,-308 # 80001050 +8000018c: 80000237 lui tp,0x80000 +80000190: 00000193 li gp,0 +80000194: 023241b3 div gp,tp,gp +80000198: 00312023 sw gp,0(sp) +8000019c: 800004b7 lui s1,0x80000 +800001a0: 00100413 li s0,1 +800001a4: 0284c433 div s0,s1,s0 +800001a8: 00812223 sw s0,4(sp) +800001ac: 80000637 lui a2,0x80000 +800001b0: fff00593 li a1,-1 +800001b4: 02b645b3 div a1,a2,a1 +800001b8: 00b12423 sw a1,8(sp) +800001bc: 80000737 lui a4,0x80000 +800001c0: 800006b7 lui a3,0x80000 +800001c4: fff68693 addi a3,a3,-1 # 7fffffff <_end+0xffffef2f> +800001c8: 02d746b3 div a3,a4,a3 +800001cc: 00d12623 sw a3,12(sp) +800001d0: 80000837 lui a6,0x80000 +800001d4: 800007b7 lui a5,0x80000 +800001d8: 02f847b3 div a5,a6,a5 +800001dc: 00f12823 sw a5,16(sp) +800001e0: 00001517 auipc a0,0x1 +800001e4: e2050513 addi a0,a0,-480 # 80001000 +800001e8: 00001597 auipc a1,0x1 +800001ec: ee858593 addi a1,a1,-280 # 800010d0 <_end> +800001f0: f0100637 lui a2,0xf0100 +800001f4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001f8 : +800001f8: 02b50663 beq a0,a1,80000224 +800001fc: 00c52683 lw a3,12(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 00852683 lw a3,8(a0) +80000208: 00d62023 sw a3,0(a2) +8000020c: 00452683 lw a3,4(a0) +80000210: 00d62023 sw a3,0(a2) +80000214: 00052683 lw a3,0(a0) +80000218: 00d62023 sw a3,0(a2) +8000021c: 01050513 addi a0,a0,16 +80000220: fd9ff06f j 800001f8 + +80000224 : +80000224: f0100537 lui a0,0xf0100 +80000228: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +8000022c: 00052023 sw zero,0(a0) +80000230: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + +80001064 : +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff + +8000108c : +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + ... diff --git a/src/test/resources/asm/DIVU.elf.objdump b/src/test/resources/asm/DIVU.elf.objdump new file mode 100644 index 0000000..4f855b3 --- /dev/null +++ b/src/test/resources/asm/DIVU.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//DIVU.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001117 auipc sp,0x1 +80000004: 00010113 mv sp,sp +80000008: 00000913 li s2,0 +8000000c: 00000893 li a7,0 +80000010: 031958b3 divu a7,s2,a7 +80000014: 01112023 sw a7,0(sp) # 80001000 +80000018: 00000a13 li s4,0 +8000001c: 00100993 li s3,1 +80000020: 033a59b3 divu s3,s4,s3 +80000024: 01312223 sw s3,4(sp) +80000028: 00000b13 li s6,0 +8000002c: fff00a93 li s5,-1 +80000030: 035b5ab3 divu s5,s6,s5 +80000034: 01512423 sw s5,8(sp) +80000038: 00000c13 li s8,0 +8000003c: 80000bb7 lui s7,0x80000 +80000040: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000044: 037c5bb3 divu s7,s8,s7 +80000048: 01712623 sw s7,12(sp) +8000004c: 00000d13 li s10,0 +80000050: 80000cb7 lui s9,0x80000 +80000054: 039d5cb3 divu s9,s10,s9 +80000058: 01912823 sw s9,16(sp) +8000005c: 00001117 auipc sp,0x1 +80000060: fb810113 addi sp,sp,-72 # 80001014 +80000064: 00100e13 li t3,1 +80000068: 00000d93 li s11,0 +8000006c: 03be5db3 divu s11,t3,s11 +80000070: 01b12023 sw s11,0(sp) +80000074: 00100f13 li t5,1 +80000078: 00100e93 li t4,1 +8000007c: 03df5eb3 divu t4,t5,t4 +80000080: 01d12223 sw t4,4(sp) +80000084: 00100193 li gp,1 +80000088: fff00f93 li t6,-1 +8000008c: 03f1dfb3 divu t6,gp,t6 +80000090: 01f12423 sw t6,8(sp) +80000094: 00100413 li s0,1 +80000098: 80000237 lui tp,0x80000 +8000009c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef2f> +800000a0: 02445233 divu tp,s0,tp +800000a4: 00412623 sw tp,12(sp) +800000a8: 00100593 li a1,1 +800000ac: 800004b7 lui s1,0x80000 +800000b0: 0295d4b3 divu s1,a1,s1 +800000b4: 00912823 sw s1,16(sp) +800000b8: 00001117 auipc sp,0x1 +800000bc: f7010113 addi sp,sp,-144 # 80001028 +800000c0: fff00693 li a3,-1 +800000c4: 00000613 li a2,0 +800000c8: 02c6d633 divu a2,a3,a2 +800000cc: 00c12023 sw a2,0(sp) +800000d0: fff00793 li a5,-1 +800000d4: 00100713 li a4,1 +800000d8: 02e7d733 divu a4,a5,a4 +800000dc: 00e12223 sw a4,4(sp) +800000e0: fff00893 li a7,-1 +800000e4: fff00813 li a6,-1 +800000e8: 0308d833 divu a6,a7,a6 +800000ec: 01012423 sw a6,8(sp) +800000f0: fff00993 li s3,-1 +800000f4: 80000937 lui s2,0x80000 +800000f8: fff90913 addi s2,s2,-1 # 7fffffff <_end+0xffffef2f> +800000fc: 0329d933 divu s2,s3,s2 +80000100: 01212623 sw s2,12(sp) +80000104: fff00a93 li s5,-1 +80000108: 80000a37 lui s4,0x80000 +8000010c: 034ada33 divu s4,s5,s4 +80000110: 01412823 sw s4,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f2810113 addi sp,sp,-216 # 8000103c +8000011c: 80000bb7 lui s7,0x80000 +80000120: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000124: 00000b13 li s6,0 +80000128: 036bdb33 divu s6,s7,s6 +8000012c: 01612023 sw s6,0(sp) +80000130: 80000cb7 lui s9,0x80000 +80000134: fffc8c93 addi s9,s9,-1 # 7fffffff <_end+0xffffef2f> +80000138: 00100c13 li s8,1 +8000013c: 038cdc33 divu s8,s9,s8 +80000140: 01812223 sw s8,4(sp) +80000144: 80000db7 lui s11,0x80000 +80000148: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef2f> +8000014c: fff00d13 li s10,-1 +80000150: 03addd33 divu s10,s11,s10 +80000154: 01a12423 sw s10,8(sp) +80000158: 80000eb7 lui t4,0x80000 +8000015c: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffef2f> +80000160: 80000e37 lui t3,0x80000 +80000164: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef2f> +80000168: 03cede33 divu t3,t4,t3 +8000016c: 01c12623 sw t3,12(sp) +80000170: 80000fb7 lui t6,0x80000 +80000174: ffff8f93 addi t6,t6,-1 # 7fffffff <_end+0xffffef2f> +80000178: 80000f37 lui t5,0x80000 +8000017c: 03efdf33 divu t5,t6,t5 +80000180: 01e12823 sw t5,16(sp) +80000184: 00001117 auipc sp,0x1 +80000188: ecc10113 addi sp,sp,-308 # 80001050 +8000018c: 80000237 lui tp,0x80000 +80000190: 00000193 li gp,0 +80000194: 023251b3 divu gp,tp,gp +80000198: 00312023 sw gp,0(sp) +8000019c: 800004b7 lui s1,0x80000 +800001a0: 00100413 li s0,1 +800001a4: 0284d433 divu s0,s1,s0 +800001a8: 00812223 sw s0,4(sp) +800001ac: 80000637 lui a2,0x80000 +800001b0: fff00593 li a1,-1 +800001b4: 02b655b3 divu a1,a2,a1 +800001b8: 00b12423 sw a1,8(sp) +800001bc: 80000737 lui a4,0x80000 +800001c0: 800006b7 lui a3,0x80000 +800001c4: fff68693 addi a3,a3,-1 # 7fffffff <_end+0xffffef2f> +800001c8: 02d756b3 divu a3,a4,a3 +800001cc: 00d12623 sw a3,12(sp) +800001d0: 80000837 lui a6,0x80000 +800001d4: 800007b7 lui a5,0x80000 +800001d8: 02f857b3 divu a5,a6,a5 +800001dc: 00f12823 sw a5,16(sp) +800001e0: 00001517 auipc a0,0x1 +800001e4: e2050513 addi a0,a0,-480 # 80001000 +800001e8: 00001597 auipc a1,0x1 +800001ec: ee858593 addi a1,a1,-280 # 800010d0 <_end> +800001f0: f0100637 lui a2,0xf0100 +800001f4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001f8 : +800001f8: 02b50663 beq a0,a1,80000224 +800001fc: 00c52683 lw a3,12(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 00852683 lw a3,8(a0) +80000208: 00d62023 sw a3,0(a2) +8000020c: 00452683 lw a3,4(a0) +80000210: 00d62023 sw a3,0(a2) +80000214: 00052683 lw a3,0(a0) +80000218: 00d62023 sw a3,0(a2) +8000021c: 01050513 addi a0,a0,16 +80000220: fd9ff06f j 800001f8 + +80000224 : +80000224: f0100537 lui a0,0xf0100 +80000228: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +8000022c: 00052023 sw zero,0(a0) +80000230: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + +80001064 : +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff + +8000108c : +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + ... diff --git a/src/test/resources/asm/DIVW.elf.objdump b/src/test/resources/asm/DIVW.elf.objdump new file mode 100644 index 0000000..00918b4 --- /dev/null +++ b/src/test/resources/asm/DIVW.elf.objdump @@ -0,0 +1,460 @@ + +/home/spinalvm/hdl/riscv-compliance/work//DIVW.elf: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 00000013 nop + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + +0000000080000108 : + 80000108: 00002117 auipc sp,0x2 + 8000010c: ef810113 addi sp,sp,-264 # 80002000 + 80000110: 00000213 li tp,0 + 80000114: 00000193 li gp,0 + 80000118: 023241bb divw gp,tp,gp + 8000011c: 00312023 sw gp,0(sp) + 80000120: 00000493 li s1,0 + 80000124: 00100413 li s0,1 + 80000128: 0284c43b divw s0,s1,s0 + 8000012c: 00812423 sw s0,8(sp) + 80000130: 00000613 li a2,0 + 80000134: fff00593 li a1,-1 + 80000138: 02b645bb divw a1,a2,a1 + 8000013c: 00b12823 sw a1,16(sp) + 80000140: 00000713 li a4,0 + 80000144: fff0069b addiw a3,zero,-1 + 80000148: 03f69693 slli a3,a3,0x3f + 8000014c: fff68693 addi a3,a3,-1 + 80000150: 02d746bb divw a3,a4,a3 + 80000154: 00d12c23 sw a3,24(sp) + 80000158: 00000813 li a6,0 + 8000015c: fff0079b addiw a5,zero,-1 + 80000160: 03f79793 slli a5,a5,0x3f + 80000164: 02f847bb divw a5,a6,a5 + 80000168: 02f12023 sw a5,32(sp) + 8000016c: 00002117 auipc sp,0x2 + 80000170: ebc10113 addi sp,sp,-324 # 80002028 + 80000174: 00100913 li s2,1 + 80000178: 00000893 li a7,0 + 8000017c: 031948bb divw a7,s2,a7 + 80000180: 01112023 sw a7,0(sp) + 80000184: 00100a13 li s4,1 + 80000188: 00100993 li s3,1 + 8000018c: 033a49bb divw s3,s4,s3 + 80000190: 01312423 sw s3,8(sp) + 80000194: 00100b13 li s6,1 + 80000198: fff00a93 li s5,-1 + 8000019c: 035b4abb divw s5,s6,s5 + 800001a0: 01512823 sw s5,16(sp) + 800001a4: 00100c13 li s8,1 + 800001a8: fff00b9b addiw s7,zero,-1 + 800001ac: 03fb9b93 slli s7,s7,0x3f + 800001b0: fffb8b93 addi s7,s7,-1 + 800001b4: 037c4bbb divw s7,s8,s7 + 800001b8: 01712c23 sw s7,24(sp) + 800001bc: 00100d13 li s10,1 + 800001c0: fff00c9b addiw s9,zero,-1 + 800001c4: 03fc9c93 slli s9,s9,0x3f + 800001c8: 039d4cbb divw s9,s10,s9 + 800001cc: 03912023 sw s9,32(sp) + 800001d0: 00002117 auipc sp,0x2 + 800001d4: e8010113 addi sp,sp,-384 # 80002050 + 800001d8: fff00e13 li t3,-1 + 800001dc: 00000d93 li s11,0 + 800001e0: 03be4dbb divw s11,t3,s11 + 800001e4: 01b12023 sw s11,0(sp) + 800001e8: fff00f13 li t5,-1 + 800001ec: 00100e93 li t4,1 + 800001f0: 03df4ebb divw t4,t5,t4 + 800001f4: 01d12423 sw t4,8(sp) + 800001f8: fff00193 li gp,-1 + 800001fc: fff00f93 li t6,-1 + 80000200: 03f1cfbb divw t6,gp,t6 + 80000204: 01f12823 sw t6,16(sp) + 80000208: fff00413 li s0,-1 + 8000020c: fff0021b addiw tp,zero,-1 + 80000210: 03f21213 slli tp,tp,0x3f + 80000214: fff20213 addi tp,tp,-1 + 80000218: 0244423b divw tp,s0,tp + 8000021c: 00412c23 sw tp,24(sp) + 80000220: fff00593 li a1,-1 + 80000224: fff0049b addiw s1,zero,-1 + 80000228: 03f49493 slli s1,s1,0x3f + 8000022c: 0295c4bb divw s1,a1,s1 + 80000230: 02912023 sw s1,32(sp) + 80000234: 00002117 auipc sp,0x2 + 80000238: e4410113 addi sp,sp,-444 # 80002078 + 8000023c: fff0069b addiw a3,zero,-1 + 80000240: 03f69693 slli a3,a3,0x3f + 80000244: fff68693 addi a3,a3,-1 + 80000248: 00000613 li a2,0 + 8000024c: 02c6c63b divw a2,a3,a2 + 80000250: 00c12023 sw a2,0(sp) + 80000254: fff0079b addiw a5,zero,-1 + 80000258: 03f79793 slli a5,a5,0x3f + 8000025c: fff78793 addi a5,a5,-1 + 80000260: 00100713 li a4,1 + 80000264: 02e7c73b divw a4,a5,a4 + 80000268: 00e12423 sw a4,8(sp) + 8000026c: fff0089b addiw a7,zero,-1 + 80000270: 03f89893 slli a7,a7,0x3f + 80000274: fff88893 addi a7,a7,-1 + 80000278: fff00813 li a6,-1 + 8000027c: 0308c83b divw a6,a7,a6 + 80000280: 01012823 sw a6,16(sp) + 80000284: fff0099b addiw s3,zero,-1 + 80000288: 03f99993 slli s3,s3,0x3f + 8000028c: fff98993 addi s3,s3,-1 + 80000290: fff0091b addiw s2,zero,-1 + 80000294: 03f91913 slli s2,s2,0x3f + 80000298: fff90913 addi s2,s2,-1 + 8000029c: 0329c93b divw s2,s3,s2 + 800002a0: 01212c23 sw s2,24(sp) + 800002a4: fff00a9b addiw s5,zero,-1 + 800002a8: 03fa9a93 slli s5,s5,0x3f + 800002ac: fffa8a93 addi s5,s5,-1 + 800002b0: fff00a1b addiw s4,zero,-1 + 800002b4: 03fa1a13 slli s4,s4,0x3f + 800002b8: 034aca3b divw s4,s5,s4 + 800002bc: 03412023 sw s4,32(sp) + 800002c0: 00002117 auipc sp,0x2 + 800002c4: de010113 addi sp,sp,-544 # 800020a0 + 800002c8: fff00b9b addiw s7,zero,-1 + 800002cc: 03fb9b93 slli s7,s7,0x3f + 800002d0: 00000b13 li s6,0 + 800002d4: 036bcb3b divw s6,s7,s6 + 800002d8: 01612023 sw s6,0(sp) + 800002dc: fff00c9b addiw s9,zero,-1 + 800002e0: 03fc9c93 slli s9,s9,0x3f + 800002e4: 00100c13 li s8,1 + 800002e8: 038ccc3b divw s8,s9,s8 + 800002ec: 01812423 sw s8,8(sp) + 800002f0: fff00d9b addiw s11,zero,-1 + 800002f4: 03fd9d93 slli s11,s11,0x3f + 800002f8: fff00d13 li s10,-1 + 800002fc: 03adcd3b divw s10,s11,s10 + 80000300: 01a12823 sw s10,16(sp) + 80000304: fff00e9b addiw t4,zero,-1 + 80000308: 03fe9e93 slli t4,t4,0x3f + 8000030c: fff00e1b addiw t3,zero,-1 + 80000310: 03fe1e13 slli t3,t3,0x3f + 80000314: fffe0e13 addi t3,t3,-1 + 80000318: 03cece3b divw t3,t4,t3 + 8000031c: 01c12c23 sw t3,24(sp) + 80000320: fff00f9b addiw t6,zero,-1 + 80000324: 03ff9f93 slli t6,t6,0x3f + 80000328: fff00f1b addiw t5,zero,-1 + 8000032c: 03ff1f13 slli t5,t5,0x3f + 80000330: 03efcf3b divw t5,t6,t5 + 80000334: 03e12023 sw t5,32(sp) + 80000338: 00000013 nop + 8000033c: 00100193 li gp,1 + 80000340: 00000073 ecall + +0000000080000344 : + 80000344: c0001073 unimp + ... + +Disassembly of section .tohost: + +0000000080001000 : + ... + +0000000080001100 : + ... + +Disassembly of section .data: + +0000000080002000 : + 80002000: ffff 0xffff + 80002002: ffff 0xffff + 80002004: 0000 unimp + 80002006: 0000 unimp + 80002008: ffff 0xffff + 8000200a: ffff 0xffff + 8000200c: 0000 unimp + 8000200e: 0000 unimp + 80002010: ffff 0xffff + 80002012: ffff 0xffff + 80002014: 0000 unimp + 80002016: 0000 unimp + 80002018: ffff 0xffff + 8000201a: ffff 0xffff + 8000201c: 0000 unimp + 8000201e: 0000 unimp + 80002020: ffff 0xffff + 80002022: ffff 0xffff + 80002024: 0000 unimp + ... + +0000000080002028 : + 80002028: ffff 0xffff + 8000202a: ffff 0xffff + 8000202c: 0000 unimp + 8000202e: 0000 unimp + 80002030: ffff 0xffff + 80002032: ffff 0xffff + 80002034: 0000 unimp + 80002036: 0000 unimp + 80002038: ffff 0xffff + 8000203a: ffff 0xffff + 8000203c: 0000 unimp + 8000203e: 0000 unimp + 80002040: ffff 0xffff + 80002042: ffff 0xffff + 80002044: 0000 unimp + 80002046: 0000 unimp + 80002048: ffff 0xffff + 8000204a: ffff 0xffff + 8000204c: 0000 unimp + ... + +0000000080002050 : + 80002050: ffff 0xffff + 80002052: ffff 0xffff + 80002054: 0000 unimp + 80002056: 0000 unimp + 80002058: ffff 0xffff + 8000205a: ffff 0xffff + 8000205c: 0000 unimp + 8000205e: 0000 unimp + 80002060: ffff 0xffff + 80002062: ffff 0xffff + 80002064: 0000 unimp + 80002066: 0000 unimp + 80002068: ffff 0xffff + 8000206a: ffff 0xffff + 8000206c: 0000 unimp + 8000206e: 0000 unimp + 80002070: ffff 0xffff + 80002072: ffff 0xffff + 80002074: 0000 unimp + ... + +0000000080002078 : + 80002078: ffff 0xffff + 8000207a: ffff 0xffff + 8000207c: 0000 unimp + 8000207e: 0000 unimp + 80002080: ffff 0xffff + 80002082: ffff 0xffff + 80002084: 0000 unimp + 80002086: 0000 unimp + 80002088: ffff 0xffff + 8000208a: ffff 0xffff + 8000208c: 0000 unimp + 8000208e: 0000 unimp + 80002090: ffff 0xffff + 80002092: ffff 0xffff + 80002094: 0000 unimp + 80002096: 0000 unimp + 80002098: ffff 0xffff + 8000209a: ffff 0xffff + 8000209c: 0000 unimp + ... + +00000000800020a0 : + 800020a0: ffff 0xffff + 800020a2: ffff 0xffff + 800020a4: 0000 unimp + 800020a6: 0000 unimp + 800020a8: ffff 0xffff + 800020aa: ffff 0xffff + 800020ac: 0000 unimp + 800020ae: 0000 unimp + 800020b0: ffff 0xffff + 800020b2: ffff 0xffff + 800020b4: 0000 unimp + 800020b6: 0000 unimp + 800020b8: ffff 0xffff + 800020ba: ffff 0xffff + 800020bc: 0000 unimp + 800020be: 0000 unimp + 800020c0: ffff 0xffff + 800020c2: ffff 0xffff + 800020c4: 0000 unimp + ... + +00000000800020c8 : + 800020c8: ffff 0xffff + 800020ca: ffff 0xffff + 800020cc: 0000 unimp + 800020ce: 0000 unimp + 800020d0: ffff 0xffff + 800020d2: ffff 0xffff + 800020d4: 0000 unimp + 800020d6: 0000 unimp + 800020d8: ffff 0xffff + 800020da: ffff 0xffff + 800020dc: 0000 unimp + 800020de: 0000 unimp + 800020e0: ffff 0xffff + 800020e2: ffff 0xffff + 800020e4: 0000 unimp + 800020e6: 0000 unimp + 800020e8: ffff 0xffff + 800020ea: ffff 0xffff + 800020ec: 0000 unimp + ... + +00000000800020f0 : + 800020f0: ffff 0xffff + 800020f2: ffff 0xffff + 800020f4: 0000 unimp + 800020f6: 0000 unimp + 800020f8: ffff 0xffff + 800020fa: ffff 0xffff + 800020fc: 0000 unimp + 800020fe: 0000 unimp + 80002100: ffff 0xffff + 80002102: ffff 0xffff + 80002104: 0000 unimp + 80002106: 0000 unimp + 80002108: ffff 0xffff + 8000210a: ffff 0xffff + 8000210c: 0000 unimp + 8000210e: 0000 unimp + 80002110: ffff 0xffff + 80002112: ffff 0xffff + 80002114: 0000 unimp + ... + +0000000080002118 : + 80002118: ffff 0xffff + 8000211a: ffff 0xffff + 8000211c: 0000 unimp + 8000211e: 0000 unimp + 80002120: ffff 0xffff + 80002122: ffff 0xffff + 80002124: 0000 unimp + 80002126: 0000 unimp + 80002128: ffff 0xffff + 8000212a: ffff 0xffff + 8000212c: 0000 unimp + 8000212e: 0000 unimp + 80002130: ffff 0xffff + 80002132: ffff 0xffff + 80002134: 0000 unimp + 80002136: 0000 unimp + 80002138: ffff 0xffff + 8000213a: ffff 0xffff + 8000213c: 0000 unimp + ... + +0000000080002140 : + 80002140: ffff 0xffff + 80002142: ffff 0xffff + 80002144: 0000 unimp + 80002146: 0000 unimp + 80002148: ffff 0xffff + 8000214a: ffff 0xffff + 8000214c: 0000 unimp + 8000214e: 0000 unimp + 80002150: ffff 0xffff + 80002152: ffff 0xffff + 80002154: 0000 unimp + 80002156: 0000 unimp + 80002158: ffff 0xffff + 8000215a: ffff 0xffff + 8000215c: 0000 unimp + 8000215e: 0000 unimp + 80002160: ffff 0xffff + 80002162: ffff 0xffff + 80002164: 0000 unimp + ... + +0000000080002168 : + 80002168: ffff 0xffff + 8000216a: ffff 0xffff + 8000216c: 0000 unimp + 8000216e: 0000 unimp + 80002170: ffff 0xffff + 80002172: ffff 0xffff + 80002174: 0000 unimp + 80002176: 0000 unimp + 80002178: ffff 0xffff + 8000217a: ffff 0xffff + 8000217c: 0000 unimp + 8000217e: 0000 unimp + 80002180: ffff 0xffff + 80002182: ffff 0xffff + 80002184: 0000 unimp + 80002186: 0000 unimp + 80002188: ffff 0xffff + 8000218a: ffff 0xffff + 8000218c: 0000 unimp + ... diff --git a/src/test/resources/asm/MUL.elf.objdump b/src/test/resources/asm/MUL.elf.objdump new file mode 100644 index 0000000..50d73f1 --- /dev/null +++ b/src/test/resources/asm/MUL.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//MUL.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001117 auipc sp,0x1 +80000004: 00010113 mv sp,sp +80000008: 00000913 li s2,0 +8000000c: 00000893 li a7,0 +80000010: 031908b3 mul a7,s2,a7 +80000014: 01112023 sw a7,0(sp) # 80001000 +80000018: 00000a13 li s4,0 +8000001c: 00100993 li s3,1 +80000020: 033a09b3 mul s3,s4,s3 +80000024: 01312223 sw s3,4(sp) +80000028: 00000b13 li s6,0 +8000002c: fff00a93 li s5,-1 +80000030: 035b0ab3 mul s5,s6,s5 +80000034: 01512423 sw s5,8(sp) +80000038: 00000c13 li s8,0 +8000003c: 80000bb7 lui s7,0x80000 +80000040: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000044: 037c0bb3 mul s7,s8,s7 +80000048: 01712623 sw s7,12(sp) +8000004c: 00000d13 li s10,0 +80000050: 80000cb7 lui s9,0x80000 +80000054: 039d0cb3 mul s9,s10,s9 +80000058: 01912823 sw s9,16(sp) +8000005c: 00001117 auipc sp,0x1 +80000060: fb810113 addi sp,sp,-72 # 80001014 +80000064: 00100e13 li t3,1 +80000068: 00000d93 li s11,0 +8000006c: 03be0db3 mul s11,t3,s11 +80000070: 01b12023 sw s11,0(sp) +80000074: 00100f13 li t5,1 +80000078: 00100e93 li t4,1 +8000007c: 03df0eb3 mul t4,t5,t4 +80000080: 01d12223 sw t4,4(sp) +80000084: 00100193 li gp,1 +80000088: fff00f93 li t6,-1 +8000008c: 03f18fb3 mul t6,gp,t6 +80000090: 01f12423 sw t6,8(sp) +80000094: 00100413 li s0,1 +80000098: 80000237 lui tp,0x80000 +8000009c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef2f> +800000a0: 02440233 mul tp,s0,tp +800000a4: 00412623 sw tp,12(sp) +800000a8: 00100593 li a1,1 +800000ac: 800004b7 lui s1,0x80000 +800000b0: 029584b3 mul s1,a1,s1 +800000b4: 00912823 sw s1,16(sp) +800000b8: 00001117 auipc sp,0x1 +800000bc: f7010113 addi sp,sp,-144 # 80001028 +800000c0: fff00693 li a3,-1 +800000c4: 00000613 li a2,0 +800000c8: 02c68633 mul a2,a3,a2 +800000cc: 00c12023 sw a2,0(sp) +800000d0: fff00793 li a5,-1 +800000d4: 00100713 li a4,1 +800000d8: 02e78733 mul a4,a5,a4 +800000dc: 00e12223 sw a4,4(sp) +800000e0: fff00893 li a7,-1 +800000e4: fff00813 li a6,-1 +800000e8: 03088833 mul a6,a7,a6 +800000ec: 01012423 sw a6,8(sp) +800000f0: fff00993 li s3,-1 +800000f4: 80000937 lui s2,0x80000 +800000f8: fff90913 addi s2,s2,-1 # 7fffffff <_end+0xffffef2f> +800000fc: 03298933 mul s2,s3,s2 +80000100: 01212623 sw s2,12(sp) +80000104: fff00a93 li s5,-1 +80000108: 80000a37 lui s4,0x80000 +8000010c: 034a8a33 mul s4,s5,s4 +80000110: 01412823 sw s4,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f2810113 addi sp,sp,-216 # 8000103c +8000011c: 80000bb7 lui s7,0x80000 +80000120: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000124: 00000b13 li s6,0 +80000128: 036b8b33 mul s6,s7,s6 +8000012c: 01612023 sw s6,0(sp) +80000130: 80000cb7 lui s9,0x80000 +80000134: fffc8c93 addi s9,s9,-1 # 7fffffff <_end+0xffffef2f> +80000138: 00100c13 li s8,1 +8000013c: 038c8c33 mul s8,s9,s8 +80000140: 01812223 sw s8,4(sp) +80000144: 80000db7 lui s11,0x80000 +80000148: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef2f> +8000014c: fff00d13 li s10,-1 +80000150: 03ad8d33 mul s10,s11,s10 +80000154: 01a12423 sw s10,8(sp) +80000158: 80000eb7 lui t4,0x80000 +8000015c: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffef2f> +80000160: 80000e37 lui t3,0x80000 +80000164: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef2f> +80000168: 03ce8e33 mul t3,t4,t3 +8000016c: 01c12623 sw t3,12(sp) +80000170: 80000fb7 lui t6,0x80000 +80000174: ffff8f93 addi t6,t6,-1 # 7fffffff <_end+0xffffef2f> +80000178: 80000f37 lui t5,0x80000 +8000017c: 03ef8f33 mul t5,t6,t5 +80000180: 01e12823 sw t5,16(sp) +80000184: 00001117 auipc sp,0x1 +80000188: ecc10113 addi sp,sp,-308 # 80001050 +8000018c: 80000237 lui tp,0x80000 +80000190: 00000193 li gp,0 +80000194: 023201b3 mul gp,tp,gp +80000198: 00312023 sw gp,0(sp) +8000019c: 800004b7 lui s1,0x80000 +800001a0: 00100413 li s0,1 +800001a4: 02848433 mul s0,s1,s0 +800001a8: 00812223 sw s0,4(sp) +800001ac: 80000637 lui a2,0x80000 +800001b0: fff00593 li a1,-1 +800001b4: 02b605b3 mul a1,a2,a1 +800001b8: 00b12423 sw a1,8(sp) +800001bc: 80000737 lui a4,0x80000 +800001c0: 800006b7 lui a3,0x80000 +800001c4: fff68693 addi a3,a3,-1 # 7fffffff <_end+0xffffef2f> +800001c8: 02d706b3 mul a3,a4,a3 +800001cc: 00d12623 sw a3,12(sp) +800001d0: 80000837 lui a6,0x80000 +800001d4: 800007b7 lui a5,0x80000 +800001d8: 02f807b3 mul a5,a6,a5 +800001dc: 00f12823 sw a5,16(sp) +800001e0: 00001517 auipc a0,0x1 +800001e4: e2050513 addi a0,a0,-480 # 80001000 +800001e8: 00001597 auipc a1,0x1 +800001ec: ee858593 addi a1,a1,-280 # 800010d0 <_end> +800001f0: f0100637 lui a2,0xf0100 +800001f4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001f8 : +800001f8: 02b50663 beq a0,a1,80000224 +800001fc: 00c52683 lw a3,12(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 00852683 lw a3,8(a0) +80000208: 00d62023 sw a3,0(a2) +8000020c: 00452683 lw a3,4(a0) +80000210: 00d62023 sw a3,0(a2) +80000214: 00052683 lw a3,0(a0) +80000218: 00d62023 sw a3,0(a2) +8000021c: 01050513 addi a0,a0,16 +80000220: fd9ff06f j 800001f8 + +80000224 : +80000224: f0100537 lui a0,0xf0100 +80000228: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +8000022c: 00052023 sw zero,0(a0) +80000230: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + +80001064 : +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff + +8000108c : +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + ... diff --git a/src/test/resources/asm/MULH.elf.objdump b/src/test/resources/asm/MULH.elf.objdump new file mode 100644 index 0000000..8550c72 --- /dev/null +++ b/src/test/resources/asm/MULH.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//MULH.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001117 auipc sp,0x1 +80000004: 00010113 mv sp,sp +80000008: 00000913 li s2,0 +8000000c: 00000893 li a7,0 +80000010: 031918b3 mulh a7,s2,a7 +80000014: 01112023 sw a7,0(sp) # 80001000 +80000018: 00000a13 li s4,0 +8000001c: 00100993 li s3,1 +80000020: 033a19b3 mulh s3,s4,s3 +80000024: 01312223 sw s3,4(sp) +80000028: 00000b13 li s6,0 +8000002c: fff00a93 li s5,-1 +80000030: 035b1ab3 mulh s5,s6,s5 +80000034: 01512423 sw s5,8(sp) +80000038: 00000c13 li s8,0 +8000003c: 80000bb7 lui s7,0x80000 +80000040: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000044: 037c1bb3 mulh s7,s8,s7 +80000048: 01712623 sw s7,12(sp) +8000004c: 00000d13 li s10,0 +80000050: 80000cb7 lui s9,0x80000 +80000054: 039d1cb3 mulh s9,s10,s9 +80000058: 01912823 sw s9,16(sp) +8000005c: 00001117 auipc sp,0x1 +80000060: fb810113 addi sp,sp,-72 # 80001014 +80000064: 00100e13 li t3,1 +80000068: 00000d93 li s11,0 +8000006c: 03be1db3 mulh s11,t3,s11 +80000070: 01b12023 sw s11,0(sp) +80000074: 00100f13 li t5,1 +80000078: 00100e93 li t4,1 +8000007c: 03df1eb3 mulh t4,t5,t4 +80000080: 01d12223 sw t4,4(sp) +80000084: 00100193 li gp,1 +80000088: fff00f93 li t6,-1 +8000008c: 03f19fb3 mulh t6,gp,t6 +80000090: 01f12423 sw t6,8(sp) +80000094: 00100413 li s0,1 +80000098: 80000237 lui tp,0x80000 +8000009c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef2f> +800000a0: 02441233 mulh tp,s0,tp +800000a4: 00412623 sw tp,12(sp) +800000a8: 00100593 li a1,1 +800000ac: 800004b7 lui s1,0x80000 +800000b0: 029594b3 mulh s1,a1,s1 +800000b4: 00912823 sw s1,16(sp) +800000b8: 00001117 auipc sp,0x1 +800000bc: f7010113 addi sp,sp,-144 # 80001028 +800000c0: fff00693 li a3,-1 +800000c4: 00000613 li a2,0 +800000c8: 02c69633 mulh a2,a3,a2 +800000cc: 00c12023 sw a2,0(sp) +800000d0: fff00793 li a5,-1 +800000d4: 00100713 li a4,1 +800000d8: 02e79733 mulh a4,a5,a4 +800000dc: 00e12223 sw a4,4(sp) +800000e0: fff00893 li a7,-1 +800000e4: fff00813 li a6,-1 +800000e8: 03089833 mulh a6,a7,a6 +800000ec: 01012423 sw a6,8(sp) +800000f0: fff00993 li s3,-1 +800000f4: 80000937 lui s2,0x80000 +800000f8: fff90913 addi s2,s2,-1 # 7fffffff <_end+0xffffef2f> +800000fc: 03299933 mulh s2,s3,s2 +80000100: 01212623 sw s2,12(sp) +80000104: fff00a93 li s5,-1 +80000108: 80000a37 lui s4,0x80000 +8000010c: 034a9a33 mulh s4,s5,s4 +80000110: 01412823 sw s4,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f2810113 addi sp,sp,-216 # 8000103c +8000011c: 80000bb7 lui s7,0x80000 +80000120: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000124: 00000b13 li s6,0 +80000128: 036b9b33 mulh s6,s7,s6 +8000012c: 01612023 sw s6,0(sp) +80000130: 80000cb7 lui s9,0x80000 +80000134: fffc8c93 addi s9,s9,-1 # 7fffffff <_end+0xffffef2f> +80000138: 00100c13 li s8,1 +8000013c: 038c9c33 mulh s8,s9,s8 +80000140: 01812223 sw s8,4(sp) +80000144: 80000db7 lui s11,0x80000 +80000148: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef2f> +8000014c: fff00d13 li s10,-1 +80000150: 03ad9d33 mulh s10,s11,s10 +80000154: 01a12423 sw s10,8(sp) +80000158: 80000eb7 lui t4,0x80000 +8000015c: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffef2f> +80000160: 80000e37 lui t3,0x80000 +80000164: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef2f> +80000168: 03ce9e33 mulh t3,t4,t3 +8000016c: 01c12623 sw t3,12(sp) +80000170: 80000fb7 lui t6,0x80000 +80000174: ffff8f93 addi t6,t6,-1 # 7fffffff <_end+0xffffef2f> +80000178: 80000f37 lui t5,0x80000 +8000017c: 03ef9f33 mulh t5,t6,t5 +80000180: 01e12823 sw t5,16(sp) +80000184: 00001117 auipc sp,0x1 +80000188: ecc10113 addi sp,sp,-308 # 80001050 +8000018c: 80000237 lui tp,0x80000 +80000190: 00000193 li gp,0 +80000194: 023211b3 mulh gp,tp,gp +80000198: 00312023 sw gp,0(sp) +8000019c: 800004b7 lui s1,0x80000 +800001a0: 00100413 li s0,1 +800001a4: 02849433 mulh s0,s1,s0 +800001a8: 00812223 sw s0,4(sp) +800001ac: 80000637 lui a2,0x80000 +800001b0: fff00593 li a1,-1 +800001b4: 02b615b3 mulh a1,a2,a1 +800001b8: 00b12423 sw a1,8(sp) +800001bc: 80000737 lui a4,0x80000 +800001c0: 800006b7 lui a3,0x80000 +800001c4: fff68693 addi a3,a3,-1 # 7fffffff <_end+0xffffef2f> +800001c8: 02d716b3 mulh a3,a4,a3 +800001cc: 00d12623 sw a3,12(sp) +800001d0: 80000837 lui a6,0x80000 +800001d4: 800007b7 lui a5,0x80000 +800001d8: 02f817b3 mulh a5,a6,a5 +800001dc: 00f12823 sw a5,16(sp) +800001e0: 00001517 auipc a0,0x1 +800001e4: e2050513 addi a0,a0,-480 # 80001000 +800001e8: 00001597 auipc a1,0x1 +800001ec: ee858593 addi a1,a1,-280 # 800010d0 <_end> +800001f0: f0100637 lui a2,0xf0100 +800001f4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001f8 : +800001f8: 02b50663 beq a0,a1,80000224 +800001fc: 00c52683 lw a3,12(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 00852683 lw a3,8(a0) +80000208: 00d62023 sw a3,0(a2) +8000020c: 00452683 lw a3,4(a0) +80000210: 00d62023 sw a3,0(a2) +80000214: 00052683 lw a3,0(a0) +80000218: 00d62023 sw a3,0(a2) +8000021c: 01050513 addi a0,a0,16 +80000220: fd9ff06f j 800001f8 + +80000224 : +80000224: f0100537 lui a0,0xf0100 +80000228: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +8000022c: 00052023 sw zero,0(a0) +80000230: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + +80001064 : +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff + +8000108c : +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + ... diff --git a/src/test/resources/asm/MULHSU.elf.objdump b/src/test/resources/asm/MULHSU.elf.objdump new file mode 100644 index 0000000..6a5b81f --- /dev/null +++ b/src/test/resources/asm/MULHSU.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//MULHSU.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001117 auipc sp,0x1 +80000004: 00010113 mv sp,sp +80000008: 00000913 li s2,0 +8000000c: 00000893 li a7,0 +80000010: 031928b3 mulhsu a7,s2,a7 +80000014: 01112023 sw a7,0(sp) # 80001000 +80000018: 00000a13 li s4,0 +8000001c: 00100993 li s3,1 +80000020: 033a29b3 mulhsu s3,s4,s3 +80000024: 01312223 sw s3,4(sp) +80000028: 00000b13 li s6,0 +8000002c: fff00a93 li s5,-1 +80000030: 035b2ab3 mulhsu s5,s6,s5 +80000034: 01512423 sw s5,8(sp) +80000038: 00000c13 li s8,0 +8000003c: 80000bb7 lui s7,0x80000 +80000040: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000044: 037c2bb3 mulhsu s7,s8,s7 +80000048: 01712623 sw s7,12(sp) +8000004c: 00000d13 li s10,0 +80000050: 80000cb7 lui s9,0x80000 +80000054: 039d2cb3 mulhsu s9,s10,s9 +80000058: 01912823 sw s9,16(sp) +8000005c: 00001117 auipc sp,0x1 +80000060: fb810113 addi sp,sp,-72 # 80001014 +80000064: 00100e13 li t3,1 +80000068: 00000d93 li s11,0 +8000006c: 03be2db3 mulhsu s11,t3,s11 +80000070: 01b12023 sw s11,0(sp) +80000074: 00100f13 li t5,1 +80000078: 00100e93 li t4,1 +8000007c: 03df2eb3 mulhsu t4,t5,t4 +80000080: 01d12223 sw t4,4(sp) +80000084: 00100193 li gp,1 +80000088: fff00f93 li t6,-1 +8000008c: 03f1afb3 mulhsu t6,gp,t6 +80000090: 01f12423 sw t6,8(sp) +80000094: 00100413 li s0,1 +80000098: 80000237 lui tp,0x80000 +8000009c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef2f> +800000a0: 02442233 mulhsu tp,s0,tp +800000a4: 00412623 sw tp,12(sp) +800000a8: 00100593 li a1,1 +800000ac: 800004b7 lui s1,0x80000 +800000b0: 0295a4b3 mulhsu s1,a1,s1 +800000b4: 00912823 sw s1,16(sp) +800000b8: 00001117 auipc sp,0x1 +800000bc: f7010113 addi sp,sp,-144 # 80001028 +800000c0: fff00693 li a3,-1 +800000c4: 00000613 li a2,0 +800000c8: 02c6a633 mulhsu a2,a3,a2 +800000cc: 00c12023 sw a2,0(sp) +800000d0: fff00793 li a5,-1 +800000d4: 00100713 li a4,1 +800000d8: 02e7a733 mulhsu a4,a5,a4 +800000dc: 00e12223 sw a4,4(sp) +800000e0: fff00893 li a7,-1 +800000e4: fff00813 li a6,-1 +800000e8: 0308a833 mulhsu a6,a7,a6 +800000ec: 01012423 sw a6,8(sp) +800000f0: fff00993 li s3,-1 +800000f4: 80000937 lui s2,0x80000 +800000f8: fff90913 addi s2,s2,-1 # 7fffffff <_end+0xffffef2f> +800000fc: 0329a933 mulhsu s2,s3,s2 +80000100: 01212623 sw s2,12(sp) +80000104: fff00a93 li s5,-1 +80000108: 80000a37 lui s4,0x80000 +8000010c: 034aaa33 mulhsu s4,s5,s4 +80000110: 01412823 sw s4,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f2810113 addi sp,sp,-216 # 8000103c +8000011c: 80000bb7 lui s7,0x80000 +80000120: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000124: 00000b13 li s6,0 +80000128: 036bab33 mulhsu s6,s7,s6 +8000012c: 01612023 sw s6,0(sp) +80000130: 80000cb7 lui s9,0x80000 +80000134: fffc8c93 addi s9,s9,-1 # 7fffffff <_end+0xffffef2f> +80000138: 00100c13 li s8,1 +8000013c: 038cac33 mulhsu s8,s9,s8 +80000140: 01812223 sw s8,4(sp) +80000144: 80000db7 lui s11,0x80000 +80000148: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef2f> +8000014c: fff00d13 li s10,-1 +80000150: 03adad33 mulhsu s10,s11,s10 +80000154: 01a12423 sw s10,8(sp) +80000158: 80000eb7 lui t4,0x80000 +8000015c: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffef2f> +80000160: 80000e37 lui t3,0x80000 +80000164: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef2f> +80000168: 03ceae33 mulhsu t3,t4,t3 +8000016c: 01c12623 sw t3,12(sp) +80000170: 80000fb7 lui t6,0x80000 +80000174: ffff8f93 addi t6,t6,-1 # 7fffffff <_end+0xffffef2f> +80000178: 80000f37 lui t5,0x80000 +8000017c: 03efaf33 mulhsu t5,t6,t5 +80000180: 01e12823 sw t5,16(sp) +80000184: 00001117 auipc sp,0x1 +80000188: ecc10113 addi sp,sp,-308 # 80001050 +8000018c: 80000237 lui tp,0x80000 +80000190: 00000193 li gp,0 +80000194: 023221b3 mulhsu gp,tp,gp +80000198: 00312023 sw gp,0(sp) +8000019c: 800004b7 lui s1,0x80000 +800001a0: 00100413 li s0,1 +800001a4: 0284a433 mulhsu s0,s1,s0 +800001a8: 00812223 sw s0,4(sp) +800001ac: 80000637 lui a2,0x80000 +800001b0: fff00593 li a1,-1 +800001b4: 02b625b3 mulhsu a1,a2,a1 +800001b8: 00b12423 sw a1,8(sp) +800001bc: 80000737 lui a4,0x80000 +800001c0: 800006b7 lui a3,0x80000 +800001c4: fff68693 addi a3,a3,-1 # 7fffffff <_end+0xffffef2f> +800001c8: 02d726b3 mulhsu a3,a4,a3 +800001cc: 00d12623 sw a3,12(sp) +800001d0: 80000837 lui a6,0x80000 +800001d4: 800007b7 lui a5,0x80000 +800001d8: 02f827b3 mulhsu a5,a6,a5 +800001dc: 00f12823 sw a5,16(sp) +800001e0: 00001517 auipc a0,0x1 +800001e4: e2050513 addi a0,a0,-480 # 80001000 +800001e8: 00001597 auipc a1,0x1 +800001ec: ee858593 addi a1,a1,-280 # 800010d0 <_end> +800001f0: f0100637 lui a2,0xf0100 +800001f4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001f8 : +800001f8: 02b50663 beq a0,a1,80000224 +800001fc: 00c52683 lw a3,12(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 00852683 lw a3,8(a0) +80000208: 00d62023 sw a3,0(a2) +8000020c: 00452683 lw a3,4(a0) +80000210: 00d62023 sw a3,0(a2) +80000214: 00052683 lw a3,0(a0) +80000218: 00d62023 sw a3,0(a2) +8000021c: 01050513 addi a0,a0,16 +80000220: fd9ff06f j 800001f8 + +80000224 : +80000224: f0100537 lui a0,0xf0100 +80000228: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +8000022c: 00052023 sw zero,0(a0) +80000230: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + +80001064 : +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff + +8000108c : +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + ... diff --git a/src/test/resources/asm/MULHU.elf.objdump b/src/test/resources/asm/MULHU.elf.objdump new file mode 100644 index 0000000..053db86 --- /dev/null +++ b/src/test/resources/asm/MULHU.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//MULHU.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001117 auipc sp,0x1 +80000004: 00010113 mv sp,sp +80000008: 00000913 li s2,0 +8000000c: 00000893 li a7,0 +80000010: 031938b3 mulhu a7,s2,a7 +80000014: 01112023 sw a7,0(sp) # 80001000 +80000018: 00000a13 li s4,0 +8000001c: 00100993 li s3,1 +80000020: 033a39b3 mulhu s3,s4,s3 +80000024: 01312223 sw s3,4(sp) +80000028: 00000b13 li s6,0 +8000002c: fff00a93 li s5,-1 +80000030: 035b3ab3 mulhu s5,s6,s5 +80000034: 01512423 sw s5,8(sp) +80000038: 00000c13 li s8,0 +8000003c: 80000bb7 lui s7,0x80000 +80000040: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000044: 037c3bb3 mulhu s7,s8,s7 +80000048: 01712623 sw s7,12(sp) +8000004c: 00000d13 li s10,0 +80000050: 80000cb7 lui s9,0x80000 +80000054: 039d3cb3 mulhu s9,s10,s9 +80000058: 01912823 sw s9,16(sp) +8000005c: 00001117 auipc sp,0x1 +80000060: fb810113 addi sp,sp,-72 # 80001014 +80000064: 00100e13 li t3,1 +80000068: 00000d93 li s11,0 +8000006c: 03be3db3 mulhu s11,t3,s11 +80000070: 01b12023 sw s11,0(sp) +80000074: 00100f13 li t5,1 +80000078: 00100e93 li t4,1 +8000007c: 03df3eb3 mulhu t4,t5,t4 +80000080: 01d12223 sw t4,4(sp) +80000084: 00100193 li gp,1 +80000088: fff00f93 li t6,-1 +8000008c: 03f1bfb3 mulhu t6,gp,t6 +80000090: 01f12423 sw t6,8(sp) +80000094: 00100413 li s0,1 +80000098: 80000237 lui tp,0x80000 +8000009c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef2f> +800000a0: 02443233 mulhu tp,s0,tp +800000a4: 00412623 sw tp,12(sp) +800000a8: 00100593 li a1,1 +800000ac: 800004b7 lui s1,0x80000 +800000b0: 0295b4b3 mulhu s1,a1,s1 +800000b4: 00912823 sw s1,16(sp) +800000b8: 00001117 auipc sp,0x1 +800000bc: f7010113 addi sp,sp,-144 # 80001028 +800000c0: fff00693 li a3,-1 +800000c4: 00000613 li a2,0 +800000c8: 02c6b633 mulhu a2,a3,a2 +800000cc: 00c12023 sw a2,0(sp) +800000d0: fff00793 li a5,-1 +800000d4: 00100713 li a4,1 +800000d8: 02e7b733 mulhu a4,a5,a4 +800000dc: 00e12223 sw a4,4(sp) +800000e0: fff00893 li a7,-1 +800000e4: fff00813 li a6,-1 +800000e8: 0308b833 mulhu a6,a7,a6 +800000ec: 01012423 sw a6,8(sp) +800000f0: fff00993 li s3,-1 +800000f4: 80000937 lui s2,0x80000 +800000f8: fff90913 addi s2,s2,-1 # 7fffffff <_end+0xffffef2f> +800000fc: 0329b933 mulhu s2,s3,s2 +80000100: 01212623 sw s2,12(sp) +80000104: fff00a93 li s5,-1 +80000108: 80000a37 lui s4,0x80000 +8000010c: 034aba33 mulhu s4,s5,s4 +80000110: 01412823 sw s4,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f2810113 addi sp,sp,-216 # 8000103c +8000011c: 80000bb7 lui s7,0x80000 +80000120: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000124: 00000b13 li s6,0 +80000128: 036bbb33 mulhu s6,s7,s6 +8000012c: 01612023 sw s6,0(sp) +80000130: 80000cb7 lui s9,0x80000 +80000134: fffc8c93 addi s9,s9,-1 # 7fffffff <_end+0xffffef2f> +80000138: 00100c13 li s8,1 +8000013c: 038cbc33 mulhu s8,s9,s8 +80000140: 01812223 sw s8,4(sp) +80000144: 80000db7 lui s11,0x80000 +80000148: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef2f> +8000014c: fff00d13 li s10,-1 +80000150: 03adbd33 mulhu s10,s11,s10 +80000154: 01a12423 sw s10,8(sp) +80000158: 80000eb7 lui t4,0x80000 +8000015c: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffef2f> +80000160: 80000e37 lui t3,0x80000 +80000164: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef2f> +80000168: 03cebe33 mulhu t3,t4,t3 +8000016c: 01c12623 sw t3,12(sp) +80000170: 80000fb7 lui t6,0x80000 +80000174: ffff8f93 addi t6,t6,-1 # 7fffffff <_end+0xffffef2f> +80000178: 80000f37 lui t5,0x80000 +8000017c: 03efbf33 mulhu t5,t6,t5 +80000180: 01e12823 sw t5,16(sp) +80000184: 00001117 auipc sp,0x1 +80000188: ecc10113 addi sp,sp,-308 # 80001050 +8000018c: 80000237 lui tp,0x80000 +80000190: 00000193 li gp,0 +80000194: 023231b3 mulhu gp,tp,gp +80000198: 00312023 sw gp,0(sp) +8000019c: 800004b7 lui s1,0x80000 +800001a0: 00100413 li s0,1 +800001a4: 0284b433 mulhu s0,s1,s0 +800001a8: 00812223 sw s0,4(sp) +800001ac: 80000637 lui a2,0x80000 +800001b0: fff00593 li a1,-1 +800001b4: 02b635b3 mulhu a1,a2,a1 +800001b8: 00b12423 sw a1,8(sp) +800001bc: 80000737 lui a4,0x80000 +800001c0: 800006b7 lui a3,0x80000 +800001c4: fff68693 addi a3,a3,-1 # 7fffffff <_end+0xffffef2f> +800001c8: 02d736b3 mulhu a3,a4,a3 +800001cc: 00d12623 sw a3,12(sp) +800001d0: 80000837 lui a6,0x80000 +800001d4: 800007b7 lui a5,0x80000 +800001d8: 02f837b3 mulhu a5,a6,a5 +800001dc: 00f12823 sw a5,16(sp) +800001e0: 00001517 auipc a0,0x1 +800001e4: e2050513 addi a0,a0,-480 # 80001000 +800001e8: 00001597 auipc a1,0x1 +800001ec: ee858593 addi a1,a1,-280 # 800010d0 <_end> +800001f0: f0100637 lui a2,0xf0100 +800001f4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001f8 : +800001f8: 02b50663 beq a0,a1,80000224 +800001fc: 00c52683 lw a3,12(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 00852683 lw a3,8(a0) +80000208: 00d62023 sw a3,0(a2) +8000020c: 00452683 lw a3,4(a0) +80000210: 00d62023 sw a3,0(a2) +80000214: 00052683 lw a3,0(a0) +80000218: 00d62023 sw a3,0(a2) +8000021c: 01050513 addi a0,a0,16 +80000220: fd9ff06f j 800001f8 + +80000224 : +80000224: f0100537 lui a0,0xf0100 +80000228: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +8000022c: 00052023 sw zero,0(a0) +80000230: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + +80001064 : +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff + +8000108c : +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + ... diff --git a/src/test/resources/asm/MULW.elf.objdump b/src/test/resources/asm/MULW.elf.objdump new file mode 100644 index 0000000..c891aa6 --- /dev/null +++ b/src/test/resources/asm/MULW.elf.objdump @@ -0,0 +1,460 @@ + +/home/spinalvm/hdl/riscv-compliance/work//MULW.elf: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 00000013 nop + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + +0000000080000108 : + 80000108: 00002117 auipc sp,0x2 + 8000010c: ef810113 addi sp,sp,-264 # 80002000 + 80000110: 00000213 li tp,0 + 80000114: 00000193 li gp,0 + 80000118: 023201bb mulw gp,tp,gp + 8000011c: 00312023 sw gp,0(sp) + 80000120: 00000493 li s1,0 + 80000124: 00100413 li s0,1 + 80000128: 0284843b mulw s0,s1,s0 + 8000012c: 00812423 sw s0,8(sp) + 80000130: 00000613 li a2,0 + 80000134: fff00593 li a1,-1 + 80000138: 02b605bb mulw a1,a2,a1 + 8000013c: 00b12823 sw a1,16(sp) + 80000140: 00000713 li a4,0 + 80000144: fff0069b addiw a3,zero,-1 + 80000148: 03f69693 slli a3,a3,0x3f + 8000014c: fff68693 addi a3,a3,-1 + 80000150: 02d706bb mulw a3,a4,a3 + 80000154: 00d12c23 sw a3,24(sp) + 80000158: 00000813 li a6,0 + 8000015c: fff0079b addiw a5,zero,-1 + 80000160: 03f79793 slli a5,a5,0x3f + 80000164: 02f807bb mulw a5,a6,a5 + 80000168: 02f12023 sw a5,32(sp) + 8000016c: 00002117 auipc sp,0x2 + 80000170: ebc10113 addi sp,sp,-324 # 80002028 + 80000174: 00100913 li s2,1 + 80000178: 00000893 li a7,0 + 8000017c: 031908bb mulw a7,s2,a7 + 80000180: 01112023 sw a7,0(sp) + 80000184: 00100a13 li s4,1 + 80000188: 00100993 li s3,1 + 8000018c: 033a09bb mulw s3,s4,s3 + 80000190: 01312423 sw s3,8(sp) + 80000194: 00100b13 li s6,1 + 80000198: fff00a93 li s5,-1 + 8000019c: 035b0abb mulw s5,s6,s5 + 800001a0: 01512823 sw s5,16(sp) + 800001a4: 00100c13 li s8,1 + 800001a8: fff00b9b addiw s7,zero,-1 + 800001ac: 03fb9b93 slli s7,s7,0x3f + 800001b0: fffb8b93 addi s7,s7,-1 + 800001b4: 037c0bbb mulw s7,s8,s7 + 800001b8: 01712c23 sw s7,24(sp) + 800001bc: 00100d13 li s10,1 + 800001c0: fff00c9b addiw s9,zero,-1 + 800001c4: 03fc9c93 slli s9,s9,0x3f + 800001c8: 039d0cbb mulw s9,s10,s9 + 800001cc: 03912023 sw s9,32(sp) + 800001d0: 00002117 auipc sp,0x2 + 800001d4: e8010113 addi sp,sp,-384 # 80002050 + 800001d8: fff00e13 li t3,-1 + 800001dc: 00000d93 li s11,0 + 800001e0: 03be0dbb mulw s11,t3,s11 + 800001e4: 01b12023 sw s11,0(sp) + 800001e8: fff00f13 li t5,-1 + 800001ec: 00100e93 li t4,1 + 800001f0: 03df0ebb mulw t4,t5,t4 + 800001f4: 01d12423 sw t4,8(sp) + 800001f8: fff00193 li gp,-1 + 800001fc: fff00f93 li t6,-1 + 80000200: 03f18fbb mulw t6,gp,t6 + 80000204: 01f12823 sw t6,16(sp) + 80000208: fff00413 li s0,-1 + 8000020c: fff0021b addiw tp,zero,-1 + 80000210: 03f21213 slli tp,tp,0x3f + 80000214: fff20213 addi tp,tp,-1 + 80000218: 0244023b mulw tp,s0,tp + 8000021c: 00412c23 sw tp,24(sp) + 80000220: fff00593 li a1,-1 + 80000224: fff0049b addiw s1,zero,-1 + 80000228: 03f49493 slli s1,s1,0x3f + 8000022c: 029584bb mulw s1,a1,s1 + 80000230: 02912023 sw s1,32(sp) + 80000234: 00002117 auipc sp,0x2 + 80000238: e4410113 addi sp,sp,-444 # 80002078 + 8000023c: fff0069b addiw a3,zero,-1 + 80000240: 03f69693 slli a3,a3,0x3f + 80000244: fff68693 addi a3,a3,-1 + 80000248: 00000613 li a2,0 + 8000024c: 02c6863b mulw a2,a3,a2 + 80000250: 00c12023 sw a2,0(sp) + 80000254: fff0079b addiw a5,zero,-1 + 80000258: 03f79793 slli a5,a5,0x3f + 8000025c: fff78793 addi a5,a5,-1 + 80000260: 00100713 li a4,1 + 80000264: 02e7873b mulw a4,a5,a4 + 80000268: 00e12423 sw a4,8(sp) + 8000026c: fff0089b addiw a7,zero,-1 + 80000270: 03f89893 slli a7,a7,0x3f + 80000274: fff88893 addi a7,a7,-1 + 80000278: fff00813 li a6,-1 + 8000027c: 0308883b mulw a6,a7,a6 + 80000280: 01012823 sw a6,16(sp) + 80000284: fff0099b addiw s3,zero,-1 + 80000288: 03f99993 slli s3,s3,0x3f + 8000028c: fff98993 addi s3,s3,-1 + 80000290: fff0091b addiw s2,zero,-1 + 80000294: 03f91913 slli s2,s2,0x3f + 80000298: fff90913 addi s2,s2,-1 + 8000029c: 0329893b mulw s2,s3,s2 + 800002a0: 01212c23 sw s2,24(sp) + 800002a4: fff00a9b addiw s5,zero,-1 + 800002a8: 03fa9a93 slli s5,s5,0x3f + 800002ac: fffa8a93 addi s5,s5,-1 + 800002b0: fff00a1b addiw s4,zero,-1 + 800002b4: 03fa1a13 slli s4,s4,0x3f + 800002b8: 034a8a3b mulw s4,s5,s4 + 800002bc: 03412023 sw s4,32(sp) + 800002c0: 00002117 auipc sp,0x2 + 800002c4: de010113 addi sp,sp,-544 # 800020a0 + 800002c8: fff00b9b addiw s7,zero,-1 + 800002cc: 03fb9b93 slli s7,s7,0x3f + 800002d0: 00000b13 li s6,0 + 800002d4: 036b8b3b mulw s6,s7,s6 + 800002d8: 01612023 sw s6,0(sp) + 800002dc: fff00c9b addiw s9,zero,-1 + 800002e0: 03fc9c93 slli s9,s9,0x3f + 800002e4: 00100c13 li s8,1 + 800002e8: 038c8c3b mulw s8,s9,s8 + 800002ec: 01812423 sw s8,8(sp) + 800002f0: fff00d9b addiw s11,zero,-1 + 800002f4: 03fd9d93 slli s11,s11,0x3f + 800002f8: fff00d13 li s10,-1 + 800002fc: 03ad8d3b mulw s10,s11,s10 + 80000300: 01a12823 sw s10,16(sp) + 80000304: fff00e9b addiw t4,zero,-1 + 80000308: 03fe9e93 slli t4,t4,0x3f + 8000030c: fff00e1b addiw t3,zero,-1 + 80000310: 03fe1e13 slli t3,t3,0x3f + 80000314: fffe0e13 addi t3,t3,-1 + 80000318: 03ce8e3b mulw t3,t4,t3 + 8000031c: 01c12c23 sw t3,24(sp) + 80000320: fff00f9b addiw t6,zero,-1 + 80000324: 03ff9f93 slli t6,t6,0x3f + 80000328: fff00f1b addiw t5,zero,-1 + 8000032c: 03ff1f13 slli t5,t5,0x3f + 80000330: 03ef8f3b mulw t5,t6,t5 + 80000334: 03e12023 sw t5,32(sp) + 80000338: 00000013 nop + 8000033c: 00100193 li gp,1 + 80000340: 00000073 ecall + +0000000080000344 : + 80000344: c0001073 unimp + ... + +Disassembly of section .tohost: + +0000000080001000 : + ... + +0000000080001100 : + ... + +Disassembly of section .data: + +0000000080002000 : + 80002000: ffff 0xffff + 80002002: ffff 0xffff + 80002004: 0000 unimp + 80002006: 0000 unimp + 80002008: ffff 0xffff + 8000200a: ffff 0xffff + 8000200c: 0000 unimp + 8000200e: 0000 unimp + 80002010: ffff 0xffff + 80002012: ffff 0xffff + 80002014: 0000 unimp + 80002016: 0000 unimp + 80002018: ffff 0xffff + 8000201a: ffff 0xffff + 8000201c: 0000 unimp + 8000201e: 0000 unimp + 80002020: ffff 0xffff + 80002022: ffff 0xffff + 80002024: 0000 unimp + ... + +0000000080002028 : + 80002028: ffff 0xffff + 8000202a: ffff 0xffff + 8000202c: 0000 unimp + 8000202e: 0000 unimp + 80002030: ffff 0xffff + 80002032: ffff 0xffff + 80002034: 0000 unimp + 80002036: 0000 unimp + 80002038: ffff 0xffff + 8000203a: ffff 0xffff + 8000203c: 0000 unimp + 8000203e: 0000 unimp + 80002040: ffff 0xffff + 80002042: ffff 0xffff + 80002044: 0000 unimp + 80002046: 0000 unimp + 80002048: ffff 0xffff + 8000204a: ffff 0xffff + 8000204c: 0000 unimp + ... + +0000000080002050 : + 80002050: ffff 0xffff + 80002052: ffff 0xffff + 80002054: 0000 unimp + 80002056: 0000 unimp + 80002058: ffff 0xffff + 8000205a: ffff 0xffff + 8000205c: 0000 unimp + 8000205e: 0000 unimp + 80002060: ffff 0xffff + 80002062: ffff 0xffff + 80002064: 0000 unimp + 80002066: 0000 unimp + 80002068: ffff 0xffff + 8000206a: ffff 0xffff + 8000206c: 0000 unimp + 8000206e: 0000 unimp + 80002070: ffff 0xffff + 80002072: ffff 0xffff + 80002074: 0000 unimp + ... + +0000000080002078 : + 80002078: ffff 0xffff + 8000207a: ffff 0xffff + 8000207c: 0000 unimp + 8000207e: 0000 unimp + 80002080: ffff 0xffff + 80002082: ffff 0xffff + 80002084: 0000 unimp + 80002086: 0000 unimp + 80002088: ffff 0xffff + 8000208a: ffff 0xffff + 8000208c: 0000 unimp + 8000208e: 0000 unimp + 80002090: ffff 0xffff + 80002092: ffff 0xffff + 80002094: 0000 unimp + 80002096: 0000 unimp + 80002098: ffff 0xffff + 8000209a: ffff 0xffff + 8000209c: 0000 unimp + ... + +00000000800020a0 : + 800020a0: ffff 0xffff + 800020a2: ffff 0xffff + 800020a4: 0000 unimp + 800020a6: 0000 unimp + 800020a8: ffff 0xffff + 800020aa: ffff 0xffff + 800020ac: 0000 unimp + 800020ae: 0000 unimp + 800020b0: ffff 0xffff + 800020b2: ffff 0xffff + 800020b4: 0000 unimp + 800020b6: 0000 unimp + 800020b8: ffff 0xffff + 800020ba: ffff 0xffff + 800020bc: 0000 unimp + 800020be: 0000 unimp + 800020c0: ffff 0xffff + 800020c2: ffff 0xffff + 800020c4: 0000 unimp + ... + +00000000800020c8 : + 800020c8: ffff 0xffff + 800020ca: ffff 0xffff + 800020cc: 0000 unimp + 800020ce: 0000 unimp + 800020d0: ffff 0xffff + 800020d2: ffff 0xffff + 800020d4: 0000 unimp + 800020d6: 0000 unimp + 800020d8: ffff 0xffff + 800020da: ffff 0xffff + 800020dc: 0000 unimp + 800020de: 0000 unimp + 800020e0: ffff 0xffff + 800020e2: ffff 0xffff + 800020e4: 0000 unimp + 800020e6: 0000 unimp + 800020e8: ffff 0xffff + 800020ea: ffff 0xffff + 800020ec: 0000 unimp + ... + +00000000800020f0 : + 800020f0: ffff 0xffff + 800020f2: ffff 0xffff + 800020f4: 0000 unimp + 800020f6: 0000 unimp + 800020f8: ffff 0xffff + 800020fa: ffff 0xffff + 800020fc: 0000 unimp + 800020fe: 0000 unimp + 80002100: ffff 0xffff + 80002102: ffff 0xffff + 80002104: 0000 unimp + 80002106: 0000 unimp + 80002108: ffff 0xffff + 8000210a: ffff 0xffff + 8000210c: 0000 unimp + 8000210e: 0000 unimp + 80002110: ffff 0xffff + 80002112: ffff 0xffff + 80002114: 0000 unimp + ... + +0000000080002118 : + 80002118: ffff 0xffff + 8000211a: ffff 0xffff + 8000211c: 0000 unimp + 8000211e: 0000 unimp + 80002120: ffff 0xffff + 80002122: ffff 0xffff + 80002124: 0000 unimp + 80002126: 0000 unimp + 80002128: ffff 0xffff + 8000212a: ffff 0xffff + 8000212c: 0000 unimp + 8000212e: 0000 unimp + 80002130: ffff 0xffff + 80002132: ffff 0xffff + 80002134: 0000 unimp + 80002136: 0000 unimp + 80002138: ffff 0xffff + 8000213a: ffff 0xffff + 8000213c: 0000 unimp + ... + +0000000080002140 : + 80002140: ffff 0xffff + 80002142: ffff 0xffff + 80002144: 0000 unimp + 80002146: 0000 unimp + 80002148: ffff 0xffff + 8000214a: ffff 0xffff + 8000214c: 0000 unimp + 8000214e: 0000 unimp + 80002150: ffff 0xffff + 80002152: ffff 0xffff + 80002154: 0000 unimp + 80002156: 0000 unimp + 80002158: ffff 0xffff + 8000215a: ffff 0xffff + 8000215c: 0000 unimp + 8000215e: 0000 unimp + 80002160: ffff 0xffff + 80002162: ffff 0xffff + 80002164: 0000 unimp + ... + +0000000080002168 : + 80002168: ffff 0xffff + 8000216a: ffff 0xffff + 8000216c: 0000 unimp + 8000216e: 0000 unimp + 80002170: ffff 0xffff + 80002172: ffff 0xffff + 80002174: 0000 unimp + 80002176: 0000 unimp + 80002178: ffff 0xffff + 8000217a: ffff 0xffff + 8000217c: 0000 unimp + 8000217e: 0000 unimp + 80002180: ffff 0xffff + 80002182: ffff 0xffff + 80002184: 0000 unimp + 80002186: 0000 unimp + 80002188: ffff 0xffff + 8000218a: ffff 0xffff + 8000218c: 0000 unimp + ... diff --git a/src/test/resources/asm/REM.elf.objdump b/src/test/resources/asm/REM.elf.objdump new file mode 100644 index 0000000..e8940c1 --- /dev/null +++ b/src/test/resources/asm/REM.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//REM.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001117 auipc sp,0x1 +80000004: 00010113 mv sp,sp +80000008: 00000913 li s2,0 +8000000c: 00000893 li a7,0 +80000010: 031968b3 rem a7,s2,a7 +80000014: 01112023 sw a7,0(sp) # 80001000 +80000018: 00000a13 li s4,0 +8000001c: 00100993 li s3,1 +80000020: 033a69b3 rem s3,s4,s3 +80000024: 01312223 sw s3,4(sp) +80000028: 00000b13 li s6,0 +8000002c: fff00a93 li s5,-1 +80000030: 035b6ab3 rem s5,s6,s5 +80000034: 01512423 sw s5,8(sp) +80000038: 00000c13 li s8,0 +8000003c: 80000bb7 lui s7,0x80000 +80000040: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000044: 037c6bb3 rem s7,s8,s7 +80000048: 01712623 sw s7,12(sp) +8000004c: 00000d13 li s10,0 +80000050: 80000cb7 lui s9,0x80000 +80000054: 039d6cb3 rem s9,s10,s9 +80000058: 01912823 sw s9,16(sp) +8000005c: 00001117 auipc sp,0x1 +80000060: fb810113 addi sp,sp,-72 # 80001014 +80000064: 00100e13 li t3,1 +80000068: 00000d93 li s11,0 +8000006c: 03be6db3 rem s11,t3,s11 +80000070: 01b12023 sw s11,0(sp) +80000074: 00100f13 li t5,1 +80000078: 00100e93 li t4,1 +8000007c: 03df6eb3 rem t4,t5,t4 +80000080: 01d12223 sw t4,4(sp) +80000084: 00100193 li gp,1 +80000088: fff00f93 li t6,-1 +8000008c: 03f1efb3 rem t6,gp,t6 +80000090: 01f12423 sw t6,8(sp) +80000094: 00100413 li s0,1 +80000098: 80000237 lui tp,0x80000 +8000009c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef2f> +800000a0: 02446233 rem tp,s0,tp +800000a4: 00412623 sw tp,12(sp) +800000a8: 00100593 li a1,1 +800000ac: 800004b7 lui s1,0x80000 +800000b0: 0295e4b3 rem s1,a1,s1 +800000b4: 00912823 sw s1,16(sp) +800000b8: 00001117 auipc sp,0x1 +800000bc: f7010113 addi sp,sp,-144 # 80001028 +800000c0: fff00693 li a3,-1 +800000c4: 00000613 li a2,0 +800000c8: 02c6e633 rem a2,a3,a2 +800000cc: 00c12023 sw a2,0(sp) +800000d0: fff00793 li a5,-1 +800000d4: 00100713 li a4,1 +800000d8: 02e7e733 rem a4,a5,a4 +800000dc: 00e12223 sw a4,4(sp) +800000e0: fff00893 li a7,-1 +800000e4: fff00813 li a6,-1 +800000e8: 0308e833 rem a6,a7,a6 +800000ec: 01012423 sw a6,8(sp) +800000f0: fff00993 li s3,-1 +800000f4: 80000937 lui s2,0x80000 +800000f8: fff90913 addi s2,s2,-1 # 7fffffff <_end+0xffffef2f> +800000fc: 0329e933 rem s2,s3,s2 +80000100: 01212623 sw s2,12(sp) +80000104: fff00a93 li s5,-1 +80000108: 80000a37 lui s4,0x80000 +8000010c: 034aea33 rem s4,s5,s4 +80000110: 01412823 sw s4,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f2810113 addi sp,sp,-216 # 8000103c +8000011c: 80000bb7 lui s7,0x80000 +80000120: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000124: 00000b13 li s6,0 +80000128: 036beb33 rem s6,s7,s6 +8000012c: 01612023 sw s6,0(sp) +80000130: 80000cb7 lui s9,0x80000 +80000134: fffc8c93 addi s9,s9,-1 # 7fffffff <_end+0xffffef2f> +80000138: 00100c13 li s8,1 +8000013c: 038cec33 rem s8,s9,s8 +80000140: 01812223 sw s8,4(sp) +80000144: 80000db7 lui s11,0x80000 +80000148: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef2f> +8000014c: fff00d13 li s10,-1 +80000150: 03aded33 rem s10,s11,s10 +80000154: 01a12423 sw s10,8(sp) +80000158: 80000eb7 lui t4,0x80000 +8000015c: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffef2f> +80000160: 80000e37 lui t3,0x80000 +80000164: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef2f> +80000168: 03ceee33 rem t3,t4,t3 +8000016c: 01c12623 sw t3,12(sp) +80000170: 80000fb7 lui t6,0x80000 +80000174: ffff8f93 addi t6,t6,-1 # 7fffffff <_end+0xffffef2f> +80000178: 80000f37 lui t5,0x80000 +8000017c: 03efef33 rem t5,t6,t5 +80000180: 01e12823 sw t5,16(sp) +80000184: 00001117 auipc sp,0x1 +80000188: ecc10113 addi sp,sp,-308 # 80001050 +8000018c: 80000237 lui tp,0x80000 +80000190: 00000193 li gp,0 +80000194: 023261b3 rem gp,tp,gp +80000198: 00312023 sw gp,0(sp) +8000019c: 800004b7 lui s1,0x80000 +800001a0: 00100413 li s0,1 +800001a4: 0284e433 rem s0,s1,s0 +800001a8: 00812223 sw s0,4(sp) +800001ac: 80000637 lui a2,0x80000 +800001b0: fff00593 li a1,-1 +800001b4: 02b665b3 rem a1,a2,a1 +800001b8: 00b12423 sw a1,8(sp) +800001bc: 80000737 lui a4,0x80000 +800001c0: 800006b7 lui a3,0x80000 +800001c4: fff68693 addi a3,a3,-1 # 7fffffff <_end+0xffffef2f> +800001c8: 02d766b3 rem a3,a4,a3 +800001cc: 00d12623 sw a3,12(sp) +800001d0: 80000837 lui a6,0x80000 +800001d4: 800007b7 lui a5,0x80000 +800001d8: 02f867b3 rem a5,a6,a5 +800001dc: 00f12823 sw a5,16(sp) +800001e0: 00001517 auipc a0,0x1 +800001e4: e2050513 addi a0,a0,-480 # 80001000 +800001e8: 00001597 auipc a1,0x1 +800001ec: ee858593 addi a1,a1,-280 # 800010d0 <_end> +800001f0: f0100637 lui a2,0xf0100 +800001f4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001f8 : +800001f8: 02b50663 beq a0,a1,80000224 +800001fc: 00c52683 lw a3,12(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 00852683 lw a3,8(a0) +80000208: 00d62023 sw a3,0(a2) +8000020c: 00452683 lw a3,4(a0) +80000210: 00d62023 sw a3,0(a2) +80000214: 00052683 lw a3,0(a0) +80000218: 00d62023 sw a3,0(a2) +8000021c: 01050513 addi a0,a0,16 +80000220: fd9ff06f j 800001f8 + +80000224 : +80000224: f0100537 lui a0,0xf0100 +80000228: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +8000022c: 00052023 sw zero,0(a0) +80000230: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + +80001064 : +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff + +8000108c : +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + ... diff --git a/src/test/resources/asm/REMU.elf.objdump b/src/test/resources/asm/REMU.elf.objdump new file mode 100644 index 0000000..da57519 --- /dev/null +++ b/src/test/resources/asm/REMU.elf.objdump @@ -0,0 +1,276 @@ + +/home/spinalvm/hdl/riscv-compliance/work//REMU.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 <_start>: +80000000: 00001117 auipc sp,0x1 +80000004: 00010113 mv sp,sp +80000008: 00000913 li s2,0 +8000000c: 00000893 li a7,0 +80000010: 031978b3 remu a7,s2,a7 +80000014: 01112023 sw a7,0(sp) # 80001000 +80000018: 00000a13 li s4,0 +8000001c: 00100993 li s3,1 +80000020: 033a79b3 remu s3,s4,s3 +80000024: 01312223 sw s3,4(sp) +80000028: 00000b13 li s6,0 +8000002c: fff00a93 li s5,-1 +80000030: 035b7ab3 remu s5,s6,s5 +80000034: 01512423 sw s5,8(sp) +80000038: 00000c13 li s8,0 +8000003c: 80000bb7 lui s7,0x80000 +80000040: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000044: 037c7bb3 remu s7,s8,s7 +80000048: 01712623 sw s7,12(sp) +8000004c: 00000d13 li s10,0 +80000050: 80000cb7 lui s9,0x80000 +80000054: 039d7cb3 remu s9,s10,s9 +80000058: 01912823 sw s9,16(sp) +8000005c: 00001117 auipc sp,0x1 +80000060: fb810113 addi sp,sp,-72 # 80001014 +80000064: 00100e13 li t3,1 +80000068: 00000d93 li s11,0 +8000006c: 03be7db3 remu s11,t3,s11 +80000070: 01b12023 sw s11,0(sp) +80000074: 00100f13 li t5,1 +80000078: 00100e93 li t4,1 +8000007c: 03df7eb3 remu t4,t5,t4 +80000080: 01d12223 sw t4,4(sp) +80000084: 00100193 li gp,1 +80000088: fff00f93 li t6,-1 +8000008c: 03f1ffb3 remu t6,gp,t6 +80000090: 01f12423 sw t6,8(sp) +80000094: 00100413 li s0,1 +80000098: 80000237 lui tp,0x80000 +8000009c: fff20213 addi tp,tp,-1 # 7fffffff <_end+0xffffef2f> +800000a0: 02447233 remu tp,s0,tp +800000a4: 00412623 sw tp,12(sp) +800000a8: 00100593 li a1,1 +800000ac: 800004b7 lui s1,0x80000 +800000b0: 0295f4b3 remu s1,a1,s1 +800000b4: 00912823 sw s1,16(sp) +800000b8: 00001117 auipc sp,0x1 +800000bc: f7010113 addi sp,sp,-144 # 80001028 +800000c0: fff00693 li a3,-1 +800000c4: 00000613 li a2,0 +800000c8: 02c6f633 remu a2,a3,a2 +800000cc: 00c12023 sw a2,0(sp) +800000d0: fff00793 li a5,-1 +800000d4: 00100713 li a4,1 +800000d8: 02e7f733 remu a4,a5,a4 +800000dc: 00e12223 sw a4,4(sp) +800000e0: fff00893 li a7,-1 +800000e4: fff00813 li a6,-1 +800000e8: 0308f833 remu a6,a7,a6 +800000ec: 01012423 sw a6,8(sp) +800000f0: fff00993 li s3,-1 +800000f4: 80000937 lui s2,0x80000 +800000f8: fff90913 addi s2,s2,-1 # 7fffffff <_end+0xffffef2f> +800000fc: 0329f933 remu s2,s3,s2 +80000100: 01212623 sw s2,12(sp) +80000104: fff00a93 li s5,-1 +80000108: 80000a37 lui s4,0x80000 +8000010c: 034afa33 remu s4,s5,s4 +80000110: 01412823 sw s4,16(sp) +80000114: 00001117 auipc sp,0x1 +80000118: f2810113 addi sp,sp,-216 # 8000103c +8000011c: 80000bb7 lui s7,0x80000 +80000120: fffb8b93 addi s7,s7,-1 # 7fffffff <_end+0xffffef2f> +80000124: 00000b13 li s6,0 +80000128: 036bfb33 remu s6,s7,s6 +8000012c: 01612023 sw s6,0(sp) +80000130: 80000cb7 lui s9,0x80000 +80000134: fffc8c93 addi s9,s9,-1 # 7fffffff <_end+0xffffef2f> +80000138: 00100c13 li s8,1 +8000013c: 038cfc33 remu s8,s9,s8 +80000140: 01812223 sw s8,4(sp) +80000144: 80000db7 lui s11,0x80000 +80000148: fffd8d93 addi s11,s11,-1 # 7fffffff <_end+0xffffef2f> +8000014c: fff00d13 li s10,-1 +80000150: 03adfd33 remu s10,s11,s10 +80000154: 01a12423 sw s10,8(sp) +80000158: 80000eb7 lui t4,0x80000 +8000015c: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffef2f> +80000160: 80000e37 lui t3,0x80000 +80000164: fffe0e13 addi t3,t3,-1 # 7fffffff <_end+0xffffef2f> +80000168: 03cefe33 remu t3,t4,t3 +8000016c: 01c12623 sw t3,12(sp) +80000170: 80000fb7 lui t6,0x80000 +80000174: ffff8f93 addi t6,t6,-1 # 7fffffff <_end+0xffffef2f> +80000178: 80000f37 lui t5,0x80000 +8000017c: 03efff33 remu t5,t6,t5 +80000180: 01e12823 sw t5,16(sp) +80000184: 00001117 auipc sp,0x1 +80000188: ecc10113 addi sp,sp,-308 # 80001050 +8000018c: 80000237 lui tp,0x80000 +80000190: 00000193 li gp,0 +80000194: 023271b3 remu gp,tp,gp +80000198: 00312023 sw gp,0(sp) +8000019c: 800004b7 lui s1,0x80000 +800001a0: 00100413 li s0,1 +800001a4: 0284f433 remu s0,s1,s0 +800001a8: 00812223 sw s0,4(sp) +800001ac: 80000637 lui a2,0x80000 +800001b0: fff00593 li a1,-1 +800001b4: 02b675b3 remu a1,a2,a1 +800001b8: 00b12423 sw a1,8(sp) +800001bc: 80000737 lui a4,0x80000 +800001c0: 800006b7 lui a3,0x80000 +800001c4: fff68693 addi a3,a3,-1 # 7fffffff <_end+0xffffef2f> +800001c8: 02d776b3 remu a3,a4,a3 +800001cc: 00d12623 sw a3,12(sp) +800001d0: 80000837 lui a6,0x80000 +800001d4: 800007b7 lui a5,0x80000 +800001d8: 02f877b3 remu a5,a6,a5 +800001dc: 00f12823 sw a5,16(sp) +800001e0: 00001517 auipc a0,0x1 +800001e4: e2050513 addi a0,a0,-480 # 80001000 +800001e8: 00001597 auipc a1,0x1 +800001ec: ee858593 addi a1,a1,-280 # 800010d0 <_end> +800001f0: f0100637 lui a2,0xf0100 +800001f4: f2c60613 addi a2,a2,-212 # f00fff2c <_end+0x700fee5c> + +800001f8 : +800001f8: 02b50663 beq a0,a1,80000224 +800001fc: 00c52683 lw a3,12(a0) +80000200: 00d62023 sw a3,0(a2) +80000204: 00852683 lw a3,8(a0) +80000208: 00d62023 sw a3,0(a2) +8000020c: 00452683 lw a3,4(a0) +80000210: 00d62023 sw a3,0(a2) +80000214: 00052683 lw a3,0(a0) +80000218: 00d62023 sw a3,0(a2) +8000021c: 01050513 addi a0,a0,16 +80000220: fd9ff06f j 800001f8 + +80000224 : +80000224: f0100537 lui a0,0xf0100 +80000228: f2050513 addi a0,a0,-224 # f00fff20 <_end+0x700fee50> +8000022c: 00052023 sw zero,0(a0) +80000230: 0000 unimp + ... + +Disassembly of section .data: + +80001000 : +80001000: ffff 0xffff +80001002: ffff 0xffff +80001004: ffff 0xffff +80001006: ffff 0xffff +80001008: ffff 0xffff +8000100a: ffff 0xffff +8000100c: ffff 0xffff +8000100e: ffff 0xffff +80001010: ffff 0xffff +80001012: ffff 0xffff + +80001014 : +80001014: ffff 0xffff +80001016: ffff 0xffff +80001018: ffff 0xffff +8000101a: ffff 0xffff +8000101c: ffff 0xffff +8000101e: ffff 0xffff +80001020: ffff 0xffff +80001022: ffff 0xffff +80001024: ffff 0xffff +80001026: ffff 0xffff + +80001028 : +80001028: ffff 0xffff +8000102a: ffff 0xffff +8000102c: ffff 0xffff +8000102e: ffff 0xffff +80001030: ffff 0xffff +80001032: ffff 0xffff +80001034: ffff 0xffff +80001036: ffff 0xffff +80001038: ffff 0xffff +8000103a: ffff 0xffff + +8000103c : +8000103c: ffff 0xffff +8000103e: ffff 0xffff +80001040: ffff 0xffff +80001042: ffff 0xffff +80001044: ffff 0xffff +80001046: ffff 0xffff +80001048: ffff 0xffff +8000104a: ffff 0xffff +8000104c: ffff 0xffff +8000104e: ffff 0xffff + +80001050 : +80001050: ffff 0xffff +80001052: ffff 0xffff +80001054: ffff 0xffff +80001056: ffff 0xffff +80001058: ffff 0xffff +8000105a: ffff 0xffff +8000105c: ffff 0xffff +8000105e: ffff 0xffff +80001060: ffff 0xffff +80001062: ffff 0xffff + +80001064 : +80001064: ffff 0xffff +80001066: ffff 0xffff +80001068: ffff 0xffff +8000106a: ffff 0xffff +8000106c: ffff 0xffff +8000106e: ffff 0xffff +80001070: ffff 0xffff +80001072: ffff 0xffff +80001074: ffff 0xffff +80001076: ffff 0xffff + +80001078 : +80001078: ffff 0xffff +8000107a: ffff 0xffff +8000107c: ffff 0xffff +8000107e: ffff 0xffff +80001080: ffff 0xffff +80001082: ffff 0xffff +80001084: ffff 0xffff +80001086: ffff 0xffff +80001088: ffff 0xffff +8000108a: ffff 0xffff + +8000108c : +8000108c: ffff 0xffff +8000108e: ffff 0xffff +80001090: ffff 0xffff +80001092: ffff 0xffff +80001094: ffff 0xffff +80001096: ffff 0xffff +80001098: ffff 0xffff +8000109a: ffff 0xffff +8000109c: ffff 0xffff +8000109e: ffff 0xffff + +800010a0 : +800010a0: ffff 0xffff +800010a2: ffff 0xffff +800010a4: ffff 0xffff +800010a6: ffff 0xffff +800010a8: ffff 0xffff +800010aa: ffff 0xffff +800010ac: ffff 0xffff +800010ae: ffff 0xffff +800010b0: ffff 0xffff +800010b2: ffff 0xffff + +800010b4 : +800010b4: ffff 0xffff +800010b6: ffff 0xffff +800010b8: ffff 0xffff +800010ba: ffff 0xffff +800010bc: ffff 0xffff +800010be: ffff 0xffff +800010c0: ffff 0xffff +800010c2: ffff 0xffff +800010c4: ffff 0xffff +800010c6: ffff 0xffff + ... diff --git a/src/test/resources/asm/REMUW.elf.objdump b/src/test/resources/asm/REMUW.elf.objdump new file mode 100644 index 0000000..deb88a2 --- /dev/null +++ b/src/test/resources/asm/REMUW.elf.objdump @@ -0,0 +1,460 @@ + +/home/spinalvm/hdl/riscv-compliance/work//REMUW.elf: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 00000013 nop + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + +0000000080000108 : + 80000108: 00002117 auipc sp,0x2 + 8000010c: ef810113 addi sp,sp,-264 # 80002000 + 80000110: 00000213 li tp,0 + 80000114: 00000193 li gp,0 + 80000118: 023271bb remuw gp,tp,gp + 8000011c: 00312023 sw gp,0(sp) + 80000120: 00000493 li s1,0 + 80000124: 00100413 li s0,1 + 80000128: 0284f43b remuw s0,s1,s0 + 8000012c: 00812423 sw s0,8(sp) + 80000130: 00000613 li a2,0 + 80000134: fff00593 li a1,-1 + 80000138: 02b675bb remuw a1,a2,a1 + 8000013c: 00b12823 sw a1,16(sp) + 80000140: 00000713 li a4,0 + 80000144: fff0069b addiw a3,zero,-1 + 80000148: 03f69693 slli a3,a3,0x3f + 8000014c: fff68693 addi a3,a3,-1 + 80000150: 02d776bb remuw a3,a4,a3 + 80000154: 00d12c23 sw a3,24(sp) + 80000158: 00000813 li a6,0 + 8000015c: fff0079b addiw a5,zero,-1 + 80000160: 03f79793 slli a5,a5,0x3f + 80000164: 02f877bb remuw a5,a6,a5 + 80000168: 02f12023 sw a5,32(sp) + 8000016c: 00002117 auipc sp,0x2 + 80000170: ebc10113 addi sp,sp,-324 # 80002028 + 80000174: 00100913 li s2,1 + 80000178: 00000893 li a7,0 + 8000017c: 031978bb remuw a7,s2,a7 + 80000180: 01112023 sw a7,0(sp) + 80000184: 00100a13 li s4,1 + 80000188: 00100993 li s3,1 + 8000018c: 033a79bb remuw s3,s4,s3 + 80000190: 01312423 sw s3,8(sp) + 80000194: 00100b13 li s6,1 + 80000198: fff00a93 li s5,-1 + 8000019c: 035b7abb remuw s5,s6,s5 + 800001a0: 01512823 sw s5,16(sp) + 800001a4: 00100c13 li s8,1 + 800001a8: fff00b9b addiw s7,zero,-1 + 800001ac: 03fb9b93 slli s7,s7,0x3f + 800001b0: fffb8b93 addi s7,s7,-1 + 800001b4: 037c7bbb remuw s7,s8,s7 + 800001b8: 01712c23 sw s7,24(sp) + 800001bc: 00100d13 li s10,1 + 800001c0: fff00c9b addiw s9,zero,-1 + 800001c4: 03fc9c93 slli s9,s9,0x3f + 800001c8: 039d7cbb remuw s9,s10,s9 + 800001cc: 03912023 sw s9,32(sp) + 800001d0: 00002117 auipc sp,0x2 + 800001d4: e8010113 addi sp,sp,-384 # 80002050 + 800001d8: fff00e13 li t3,-1 + 800001dc: 00000d93 li s11,0 + 800001e0: 03be7dbb remuw s11,t3,s11 + 800001e4: 01b12023 sw s11,0(sp) + 800001e8: fff00f13 li t5,-1 + 800001ec: 00100e93 li t4,1 + 800001f0: 03df7ebb remuw t4,t5,t4 + 800001f4: 01d12423 sw t4,8(sp) + 800001f8: fff00193 li gp,-1 + 800001fc: fff00f93 li t6,-1 + 80000200: 03f1ffbb remuw t6,gp,t6 + 80000204: 01f12823 sw t6,16(sp) + 80000208: fff00413 li s0,-1 + 8000020c: fff0021b addiw tp,zero,-1 + 80000210: 03f21213 slli tp,tp,0x3f + 80000214: fff20213 addi tp,tp,-1 + 80000218: 0244723b remuw tp,s0,tp + 8000021c: 00412c23 sw tp,24(sp) + 80000220: fff00593 li a1,-1 + 80000224: fff0049b addiw s1,zero,-1 + 80000228: 03f49493 slli s1,s1,0x3f + 8000022c: 0295f4bb remuw s1,a1,s1 + 80000230: 02912023 sw s1,32(sp) + 80000234: 00002117 auipc sp,0x2 + 80000238: e4410113 addi sp,sp,-444 # 80002078 + 8000023c: fff0069b addiw a3,zero,-1 + 80000240: 03f69693 slli a3,a3,0x3f + 80000244: fff68693 addi a3,a3,-1 + 80000248: 00000613 li a2,0 + 8000024c: 02c6f63b remuw a2,a3,a2 + 80000250: 00c12023 sw a2,0(sp) + 80000254: fff0079b addiw a5,zero,-1 + 80000258: 03f79793 slli a5,a5,0x3f + 8000025c: fff78793 addi a5,a5,-1 + 80000260: 00100713 li a4,1 + 80000264: 02e7f73b remuw a4,a5,a4 + 80000268: 00e12423 sw a4,8(sp) + 8000026c: fff0089b addiw a7,zero,-1 + 80000270: 03f89893 slli a7,a7,0x3f + 80000274: fff88893 addi a7,a7,-1 + 80000278: fff00813 li a6,-1 + 8000027c: 0308f83b remuw a6,a7,a6 + 80000280: 01012823 sw a6,16(sp) + 80000284: fff0099b addiw s3,zero,-1 + 80000288: 03f99993 slli s3,s3,0x3f + 8000028c: fff98993 addi s3,s3,-1 + 80000290: fff0091b addiw s2,zero,-1 + 80000294: 03f91913 slli s2,s2,0x3f + 80000298: fff90913 addi s2,s2,-1 + 8000029c: 0329f93b remuw s2,s3,s2 + 800002a0: 01212c23 sw s2,24(sp) + 800002a4: fff00a9b addiw s5,zero,-1 + 800002a8: 03fa9a93 slli s5,s5,0x3f + 800002ac: fffa8a93 addi s5,s5,-1 + 800002b0: fff00a1b addiw s4,zero,-1 + 800002b4: 03fa1a13 slli s4,s4,0x3f + 800002b8: 034afa3b remuw s4,s5,s4 + 800002bc: 03412023 sw s4,32(sp) + 800002c0: 00002117 auipc sp,0x2 + 800002c4: de010113 addi sp,sp,-544 # 800020a0 + 800002c8: fff00b9b addiw s7,zero,-1 + 800002cc: 03fb9b93 slli s7,s7,0x3f + 800002d0: 00000b13 li s6,0 + 800002d4: 036bfb3b remuw s6,s7,s6 + 800002d8: 01612023 sw s6,0(sp) + 800002dc: fff00c9b addiw s9,zero,-1 + 800002e0: 03fc9c93 slli s9,s9,0x3f + 800002e4: 00100c13 li s8,1 + 800002e8: 038cfc3b remuw s8,s9,s8 + 800002ec: 01812423 sw s8,8(sp) + 800002f0: fff00d9b addiw s11,zero,-1 + 800002f4: 03fd9d93 slli s11,s11,0x3f + 800002f8: fff00d13 li s10,-1 + 800002fc: 03adfd3b remuw s10,s11,s10 + 80000300: 01a12823 sw s10,16(sp) + 80000304: fff00e9b addiw t4,zero,-1 + 80000308: 03fe9e93 slli t4,t4,0x3f + 8000030c: fff00e1b addiw t3,zero,-1 + 80000310: 03fe1e13 slli t3,t3,0x3f + 80000314: fffe0e13 addi t3,t3,-1 + 80000318: 03cefe3b remuw t3,t4,t3 + 8000031c: 01c12c23 sw t3,24(sp) + 80000320: fff00f9b addiw t6,zero,-1 + 80000324: 03ff9f93 slli t6,t6,0x3f + 80000328: fff00f1b addiw t5,zero,-1 + 8000032c: 03ff1f13 slli t5,t5,0x3f + 80000330: 03efff3b remuw t5,t6,t5 + 80000334: 03e12023 sw t5,32(sp) + 80000338: 00000013 nop + 8000033c: 00100193 li gp,1 + 80000340: 00000073 ecall + +0000000080000344 : + 80000344: c0001073 unimp + ... + +Disassembly of section .tohost: + +0000000080001000 : + ... + +0000000080001100 : + ... + +Disassembly of section .data: + +0000000080002000 : + 80002000: ffff 0xffff + 80002002: ffff 0xffff + 80002004: 0000 unimp + 80002006: 0000 unimp + 80002008: ffff 0xffff + 8000200a: ffff 0xffff + 8000200c: 0000 unimp + 8000200e: 0000 unimp + 80002010: ffff 0xffff + 80002012: ffff 0xffff + 80002014: 0000 unimp + 80002016: 0000 unimp + 80002018: ffff 0xffff + 8000201a: ffff 0xffff + 8000201c: 0000 unimp + 8000201e: 0000 unimp + 80002020: ffff 0xffff + 80002022: ffff 0xffff + 80002024: 0000 unimp + ... + +0000000080002028 : + 80002028: ffff 0xffff + 8000202a: ffff 0xffff + 8000202c: 0000 unimp + 8000202e: 0000 unimp + 80002030: ffff 0xffff + 80002032: ffff 0xffff + 80002034: 0000 unimp + 80002036: 0000 unimp + 80002038: ffff 0xffff + 8000203a: ffff 0xffff + 8000203c: 0000 unimp + 8000203e: 0000 unimp + 80002040: ffff 0xffff + 80002042: ffff 0xffff + 80002044: 0000 unimp + 80002046: 0000 unimp + 80002048: ffff 0xffff + 8000204a: ffff 0xffff + 8000204c: 0000 unimp + ... + +0000000080002050 : + 80002050: ffff 0xffff + 80002052: ffff 0xffff + 80002054: 0000 unimp + 80002056: 0000 unimp + 80002058: ffff 0xffff + 8000205a: ffff 0xffff + 8000205c: 0000 unimp + 8000205e: 0000 unimp + 80002060: ffff 0xffff + 80002062: ffff 0xffff + 80002064: 0000 unimp + 80002066: 0000 unimp + 80002068: ffff 0xffff + 8000206a: ffff 0xffff + 8000206c: 0000 unimp + 8000206e: 0000 unimp + 80002070: ffff 0xffff + 80002072: ffff 0xffff + 80002074: 0000 unimp + ... + +0000000080002078 : + 80002078: ffff 0xffff + 8000207a: ffff 0xffff + 8000207c: 0000 unimp + 8000207e: 0000 unimp + 80002080: ffff 0xffff + 80002082: ffff 0xffff + 80002084: 0000 unimp + 80002086: 0000 unimp + 80002088: ffff 0xffff + 8000208a: ffff 0xffff + 8000208c: 0000 unimp + 8000208e: 0000 unimp + 80002090: ffff 0xffff + 80002092: ffff 0xffff + 80002094: 0000 unimp + 80002096: 0000 unimp + 80002098: ffff 0xffff + 8000209a: ffff 0xffff + 8000209c: 0000 unimp + ... + +00000000800020a0 : + 800020a0: ffff 0xffff + 800020a2: ffff 0xffff + 800020a4: 0000 unimp + 800020a6: 0000 unimp + 800020a8: ffff 0xffff + 800020aa: ffff 0xffff + 800020ac: 0000 unimp + 800020ae: 0000 unimp + 800020b0: ffff 0xffff + 800020b2: ffff 0xffff + 800020b4: 0000 unimp + 800020b6: 0000 unimp + 800020b8: ffff 0xffff + 800020ba: ffff 0xffff + 800020bc: 0000 unimp + 800020be: 0000 unimp + 800020c0: ffff 0xffff + 800020c2: ffff 0xffff + 800020c4: 0000 unimp + ... + +00000000800020c8 : + 800020c8: ffff 0xffff + 800020ca: ffff 0xffff + 800020cc: 0000 unimp + 800020ce: 0000 unimp + 800020d0: ffff 0xffff + 800020d2: ffff 0xffff + 800020d4: 0000 unimp + 800020d6: 0000 unimp + 800020d8: ffff 0xffff + 800020da: ffff 0xffff + 800020dc: 0000 unimp + 800020de: 0000 unimp + 800020e0: ffff 0xffff + 800020e2: ffff 0xffff + 800020e4: 0000 unimp + 800020e6: 0000 unimp + 800020e8: ffff 0xffff + 800020ea: ffff 0xffff + 800020ec: 0000 unimp + ... + +00000000800020f0 : + 800020f0: ffff 0xffff + 800020f2: ffff 0xffff + 800020f4: 0000 unimp + 800020f6: 0000 unimp + 800020f8: ffff 0xffff + 800020fa: ffff 0xffff + 800020fc: 0000 unimp + 800020fe: 0000 unimp + 80002100: ffff 0xffff + 80002102: ffff 0xffff + 80002104: 0000 unimp + 80002106: 0000 unimp + 80002108: ffff 0xffff + 8000210a: ffff 0xffff + 8000210c: 0000 unimp + 8000210e: 0000 unimp + 80002110: ffff 0xffff + 80002112: ffff 0xffff + 80002114: 0000 unimp + ... + +0000000080002118 : + 80002118: ffff 0xffff + 8000211a: ffff 0xffff + 8000211c: 0000 unimp + 8000211e: 0000 unimp + 80002120: ffff 0xffff + 80002122: ffff 0xffff + 80002124: 0000 unimp + 80002126: 0000 unimp + 80002128: ffff 0xffff + 8000212a: ffff 0xffff + 8000212c: 0000 unimp + 8000212e: 0000 unimp + 80002130: ffff 0xffff + 80002132: ffff 0xffff + 80002134: 0000 unimp + 80002136: 0000 unimp + 80002138: ffff 0xffff + 8000213a: ffff 0xffff + 8000213c: 0000 unimp + ... + +0000000080002140 : + 80002140: ffff 0xffff + 80002142: ffff 0xffff + 80002144: 0000 unimp + 80002146: 0000 unimp + 80002148: ffff 0xffff + 8000214a: ffff 0xffff + 8000214c: 0000 unimp + 8000214e: 0000 unimp + 80002150: ffff 0xffff + 80002152: ffff 0xffff + 80002154: 0000 unimp + 80002156: 0000 unimp + 80002158: ffff 0xffff + 8000215a: ffff 0xffff + 8000215c: 0000 unimp + 8000215e: 0000 unimp + 80002160: ffff 0xffff + 80002162: ffff 0xffff + 80002164: 0000 unimp + ... + +0000000080002168 : + 80002168: ffff 0xffff + 8000216a: ffff 0xffff + 8000216c: 0000 unimp + 8000216e: 0000 unimp + 80002170: ffff 0xffff + 80002172: ffff 0xffff + 80002174: 0000 unimp + 80002176: 0000 unimp + 80002178: ffff 0xffff + 8000217a: ffff 0xffff + 8000217c: 0000 unimp + 8000217e: 0000 unimp + 80002180: ffff 0xffff + 80002182: ffff 0xffff + 80002184: 0000 unimp + 80002186: 0000 unimp + 80002188: ffff 0xffff + 8000218a: ffff 0xffff + 8000218c: 0000 unimp + ... diff --git a/src/test/resources/asm/REMW.elf.objdump b/src/test/resources/asm/REMW.elf.objdump new file mode 100644 index 0000000..b5d64c5 --- /dev/null +++ b/src/test/resources/asm/REMW.elf.objdump @@ -0,0 +1,460 @@ + +/home/spinalvm/hdl/riscv-compliance/work//REMW.elf: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c + +0000000080000004 : + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c + 80000038: 0040006f j 8000003c + +000000008000003c : + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 : + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 + 80000048: ff9ff06f j 80000040 + +000000008000004c : + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 + 800000b4: 00000013 nop + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + +0000000080000108 : + 80000108: 00002117 auipc sp,0x2 + 8000010c: ef810113 addi sp,sp,-264 # 80002000 + 80000110: 00000213 li tp,0 + 80000114: 00000193 li gp,0 + 80000118: 023261bb remw gp,tp,gp + 8000011c: 00312023 sw gp,0(sp) + 80000120: 00000493 li s1,0 + 80000124: 00100413 li s0,1 + 80000128: 0284e43b remw s0,s1,s0 + 8000012c: 00812423 sw s0,8(sp) + 80000130: 00000613 li a2,0 + 80000134: fff00593 li a1,-1 + 80000138: 02b665bb remw a1,a2,a1 + 8000013c: 00b12823 sw a1,16(sp) + 80000140: 00000713 li a4,0 + 80000144: fff0069b addiw a3,zero,-1 + 80000148: 03f69693 slli a3,a3,0x3f + 8000014c: fff68693 addi a3,a3,-1 + 80000150: 02d766bb remw a3,a4,a3 + 80000154: 00d12c23 sw a3,24(sp) + 80000158: 00000813 li a6,0 + 8000015c: fff0079b addiw a5,zero,-1 + 80000160: 03f79793 slli a5,a5,0x3f + 80000164: 02f867bb remw a5,a6,a5 + 80000168: 02f12023 sw a5,32(sp) + 8000016c: 00002117 auipc sp,0x2 + 80000170: ebc10113 addi sp,sp,-324 # 80002028 + 80000174: 00100913 li s2,1 + 80000178: 00000893 li a7,0 + 8000017c: 031968bb remw a7,s2,a7 + 80000180: 01112023 sw a7,0(sp) + 80000184: 00100a13 li s4,1 + 80000188: 00100993 li s3,1 + 8000018c: 033a69bb remw s3,s4,s3 + 80000190: 01312423 sw s3,8(sp) + 80000194: 00100b13 li s6,1 + 80000198: fff00a93 li s5,-1 + 8000019c: 035b6abb remw s5,s6,s5 + 800001a0: 01512823 sw s5,16(sp) + 800001a4: 00100c13 li s8,1 + 800001a8: fff00b9b addiw s7,zero,-1 + 800001ac: 03fb9b93 slli s7,s7,0x3f + 800001b0: fffb8b93 addi s7,s7,-1 + 800001b4: 037c6bbb remw s7,s8,s7 + 800001b8: 01712c23 sw s7,24(sp) + 800001bc: 00100d13 li s10,1 + 800001c0: fff00c9b addiw s9,zero,-1 + 800001c4: 03fc9c93 slli s9,s9,0x3f + 800001c8: 039d6cbb remw s9,s10,s9 + 800001cc: 03912023 sw s9,32(sp) + 800001d0: 00002117 auipc sp,0x2 + 800001d4: e8010113 addi sp,sp,-384 # 80002050 + 800001d8: fff00e13 li t3,-1 + 800001dc: 00000d93 li s11,0 + 800001e0: 03be6dbb remw s11,t3,s11 + 800001e4: 01b12023 sw s11,0(sp) + 800001e8: fff00f13 li t5,-1 + 800001ec: 00100e93 li t4,1 + 800001f0: 03df6ebb remw t4,t5,t4 + 800001f4: 01d12423 sw t4,8(sp) + 800001f8: fff00193 li gp,-1 + 800001fc: fff00f93 li t6,-1 + 80000200: 03f1efbb remw t6,gp,t6 + 80000204: 01f12823 sw t6,16(sp) + 80000208: fff00413 li s0,-1 + 8000020c: fff0021b addiw tp,zero,-1 + 80000210: 03f21213 slli tp,tp,0x3f + 80000214: fff20213 addi tp,tp,-1 + 80000218: 0244623b remw tp,s0,tp + 8000021c: 00412c23 sw tp,24(sp) + 80000220: fff00593 li a1,-1 + 80000224: fff0049b addiw s1,zero,-1 + 80000228: 03f49493 slli s1,s1,0x3f + 8000022c: 0295e4bb remw s1,a1,s1 + 80000230: 02912023 sw s1,32(sp) + 80000234: 00002117 auipc sp,0x2 + 80000238: e4410113 addi sp,sp,-444 # 80002078 + 8000023c: fff0069b addiw a3,zero,-1 + 80000240: 03f69693 slli a3,a3,0x3f + 80000244: fff68693 addi a3,a3,-1 + 80000248: 00000613 li a2,0 + 8000024c: 02c6e63b remw a2,a3,a2 + 80000250: 00c12023 sw a2,0(sp) + 80000254: fff0079b addiw a5,zero,-1 + 80000258: 03f79793 slli a5,a5,0x3f + 8000025c: fff78793 addi a5,a5,-1 + 80000260: 00100713 li a4,1 + 80000264: 02e7e73b remw a4,a5,a4 + 80000268: 00e12423 sw a4,8(sp) + 8000026c: fff0089b addiw a7,zero,-1 + 80000270: 03f89893 slli a7,a7,0x3f + 80000274: fff88893 addi a7,a7,-1 + 80000278: fff00813 li a6,-1 + 8000027c: 0308e83b remw a6,a7,a6 + 80000280: 01012823 sw a6,16(sp) + 80000284: fff0099b addiw s3,zero,-1 + 80000288: 03f99993 slli s3,s3,0x3f + 8000028c: fff98993 addi s3,s3,-1 + 80000290: fff0091b addiw s2,zero,-1 + 80000294: 03f91913 slli s2,s2,0x3f + 80000298: fff90913 addi s2,s2,-1 + 8000029c: 0329e93b remw s2,s3,s2 + 800002a0: 01212c23 sw s2,24(sp) + 800002a4: fff00a9b addiw s5,zero,-1 + 800002a8: 03fa9a93 slli s5,s5,0x3f + 800002ac: fffa8a93 addi s5,s5,-1 + 800002b0: fff00a1b addiw s4,zero,-1 + 800002b4: 03fa1a13 slli s4,s4,0x3f + 800002b8: 034aea3b remw s4,s5,s4 + 800002bc: 03412023 sw s4,32(sp) + 800002c0: 00002117 auipc sp,0x2 + 800002c4: de010113 addi sp,sp,-544 # 800020a0 + 800002c8: fff00b9b addiw s7,zero,-1 + 800002cc: 03fb9b93 slli s7,s7,0x3f + 800002d0: 00000b13 li s6,0 + 800002d4: 036beb3b remw s6,s7,s6 + 800002d8: 01612023 sw s6,0(sp) + 800002dc: fff00c9b addiw s9,zero,-1 + 800002e0: 03fc9c93 slli s9,s9,0x3f + 800002e4: 00100c13 li s8,1 + 800002e8: 038cec3b remw s8,s9,s8 + 800002ec: 01812423 sw s8,8(sp) + 800002f0: fff00d9b addiw s11,zero,-1 + 800002f4: 03fd9d93 slli s11,s11,0x3f + 800002f8: fff00d13 li s10,-1 + 800002fc: 03aded3b remw s10,s11,s10 + 80000300: 01a12823 sw s10,16(sp) + 80000304: fff00e9b addiw t4,zero,-1 + 80000308: 03fe9e93 slli t4,t4,0x3f + 8000030c: fff00e1b addiw t3,zero,-1 + 80000310: 03fe1e13 slli t3,t3,0x3f + 80000314: fffe0e13 addi t3,t3,-1 + 80000318: 03ceee3b remw t3,t4,t3 + 8000031c: 01c12c23 sw t3,24(sp) + 80000320: fff00f9b addiw t6,zero,-1 + 80000324: 03ff9f93 slli t6,t6,0x3f + 80000328: fff00f1b addiw t5,zero,-1 + 8000032c: 03ff1f13 slli t5,t5,0x3f + 80000330: 03efef3b remw t5,t6,t5 + 80000334: 03e12023 sw t5,32(sp) + 80000338: 00000013 nop + 8000033c: 00100193 li gp,1 + 80000340: 00000073 ecall + +0000000080000344 : + 80000344: c0001073 unimp + ... + +Disassembly of section .tohost: + +0000000080001000 : + ... + +0000000080001100 : + ... + +Disassembly of section .data: + +0000000080002000 : + 80002000: ffff 0xffff + 80002002: ffff 0xffff + 80002004: 0000 unimp + 80002006: 0000 unimp + 80002008: ffff 0xffff + 8000200a: ffff 0xffff + 8000200c: 0000 unimp + 8000200e: 0000 unimp + 80002010: ffff 0xffff + 80002012: ffff 0xffff + 80002014: 0000 unimp + 80002016: 0000 unimp + 80002018: ffff 0xffff + 8000201a: ffff 0xffff + 8000201c: 0000 unimp + 8000201e: 0000 unimp + 80002020: ffff 0xffff + 80002022: ffff 0xffff + 80002024: 0000 unimp + ... + +0000000080002028 : + 80002028: ffff 0xffff + 8000202a: ffff 0xffff + 8000202c: 0000 unimp + 8000202e: 0000 unimp + 80002030: ffff 0xffff + 80002032: ffff 0xffff + 80002034: 0000 unimp + 80002036: 0000 unimp + 80002038: ffff 0xffff + 8000203a: ffff 0xffff + 8000203c: 0000 unimp + 8000203e: 0000 unimp + 80002040: ffff 0xffff + 80002042: ffff 0xffff + 80002044: 0000 unimp + 80002046: 0000 unimp + 80002048: ffff 0xffff + 8000204a: ffff 0xffff + 8000204c: 0000 unimp + ... + +0000000080002050 : + 80002050: ffff 0xffff + 80002052: ffff 0xffff + 80002054: 0000 unimp + 80002056: 0000 unimp + 80002058: ffff 0xffff + 8000205a: ffff 0xffff + 8000205c: 0000 unimp + 8000205e: 0000 unimp + 80002060: ffff 0xffff + 80002062: ffff 0xffff + 80002064: 0000 unimp + 80002066: 0000 unimp + 80002068: ffff 0xffff + 8000206a: ffff 0xffff + 8000206c: 0000 unimp + 8000206e: 0000 unimp + 80002070: ffff 0xffff + 80002072: ffff 0xffff + 80002074: 0000 unimp + ... + +0000000080002078 : + 80002078: ffff 0xffff + 8000207a: ffff 0xffff + 8000207c: 0000 unimp + 8000207e: 0000 unimp + 80002080: ffff 0xffff + 80002082: ffff 0xffff + 80002084: 0000 unimp + 80002086: 0000 unimp + 80002088: ffff 0xffff + 8000208a: ffff 0xffff + 8000208c: 0000 unimp + 8000208e: 0000 unimp + 80002090: ffff 0xffff + 80002092: ffff 0xffff + 80002094: 0000 unimp + 80002096: 0000 unimp + 80002098: ffff 0xffff + 8000209a: ffff 0xffff + 8000209c: 0000 unimp + ... + +00000000800020a0 : + 800020a0: ffff 0xffff + 800020a2: ffff 0xffff + 800020a4: 0000 unimp + 800020a6: 0000 unimp + 800020a8: ffff 0xffff + 800020aa: ffff 0xffff + 800020ac: 0000 unimp + 800020ae: 0000 unimp + 800020b0: ffff 0xffff + 800020b2: ffff 0xffff + 800020b4: 0000 unimp + 800020b6: 0000 unimp + 800020b8: ffff 0xffff + 800020ba: ffff 0xffff + 800020bc: 0000 unimp + 800020be: 0000 unimp + 800020c0: ffff 0xffff + 800020c2: ffff 0xffff + 800020c4: 0000 unimp + ... + +00000000800020c8 : + 800020c8: ffff 0xffff + 800020ca: ffff 0xffff + 800020cc: 0000 unimp + 800020ce: 0000 unimp + 800020d0: ffff 0xffff + 800020d2: ffff 0xffff + 800020d4: 0000 unimp + 800020d6: 0000 unimp + 800020d8: ffff 0xffff + 800020da: ffff 0xffff + 800020dc: 0000 unimp + 800020de: 0000 unimp + 800020e0: ffff 0xffff + 800020e2: ffff 0xffff + 800020e4: 0000 unimp + 800020e6: 0000 unimp + 800020e8: ffff 0xffff + 800020ea: ffff 0xffff + 800020ec: 0000 unimp + ... + +00000000800020f0 : + 800020f0: ffff 0xffff + 800020f2: ffff 0xffff + 800020f4: 0000 unimp + 800020f6: 0000 unimp + 800020f8: ffff 0xffff + 800020fa: ffff 0xffff + 800020fc: 0000 unimp + 800020fe: 0000 unimp + 80002100: ffff 0xffff + 80002102: ffff 0xffff + 80002104: 0000 unimp + 80002106: 0000 unimp + 80002108: ffff 0xffff + 8000210a: ffff 0xffff + 8000210c: 0000 unimp + 8000210e: 0000 unimp + 80002110: ffff 0xffff + 80002112: ffff 0xffff + 80002114: 0000 unimp + ... + +0000000080002118 : + 80002118: ffff 0xffff + 8000211a: ffff 0xffff + 8000211c: 0000 unimp + 8000211e: 0000 unimp + 80002120: ffff 0xffff + 80002122: ffff 0xffff + 80002124: 0000 unimp + 80002126: 0000 unimp + 80002128: ffff 0xffff + 8000212a: ffff 0xffff + 8000212c: 0000 unimp + 8000212e: 0000 unimp + 80002130: ffff 0xffff + 80002132: ffff 0xffff + 80002134: 0000 unimp + 80002136: 0000 unimp + 80002138: ffff 0xffff + 8000213a: ffff 0xffff + 8000213c: 0000 unimp + ... + +0000000080002140 : + 80002140: ffff 0xffff + 80002142: ffff 0xffff + 80002144: 0000 unimp + 80002146: 0000 unimp + 80002148: ffff 0xffff + 8000214a: ffff 0xffff + 8000214c: 0000 unimp + 8000214e: 0000 unimp + 80002150: ffff 0xffff + 80002152: ffff 0xffff + 80002154: 0000 unimp + 80002156: 0000 unimp + 80002158: ffff 0xffff + 8000215a: ffff 0xffff + 8000215c: 0000 unimp + 8000215e: 0000 unimp + 80002160: ffff 0xffff + 80002162: ffff 0xffff + 80002164: 0000 unimp + ... + +0000000080002168 : + 80002168: ffff 0xffff + 8000216a: ffff 0xffff + 8000216c: 0000 unimp + 8000216e: 0000 unimp + 80002170: ffff 0xffff + 80002172: ffff 0xffff + 80002174: 0000 unimp + 80002176: 0000 unimp + 80002178: ffff 0xffff + 8000217a: ffff 0xffff + 8000217c: 0000 unimp + 8000217e: 0000 unimp + 80002180: ffff 0xffff + 80002182: ffff 0xffff + 80002184: 0000 unimp + 80002186: 0000 unimp + 80002188: ffff 0xffff + 8000218a: ffff 0xffff + 8000218c: 0000 unimp + ... diff --git a/src/test/resources/hex/C.ADD.elf.hex b/src/test/resources/hex/C.ADD.elf.hex new file mode 100644 index 0000000..6d13438 --- /dev/null +++ b/src/test/resources/hex/C.ADD.elf.hex @@ -0,0 +1,50 @@ +:0200000480007A +:1000000001000100010001000100010001000100E8 +:1000100001000100010001000100010001000100D8 +:1000200001000100010001000100010001000100C8 +:1000300001000100010001000100010001000100B8 +:1000400001000100010001000100010001000100A8 +:100050000100010001000100010001000100010098 +:100060000100010001000100010001000100010088 +:100070000100010001000100010001000100010078 +:100080000100010001000100010001000100010068 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+:10104000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB0 +:10105000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA0 +:10106000FFFFFFFF00000000000000000000000084 +:040000058000000077 +:00000001FF diff --git a/src/test/resources/hex/C.ANDI.elf.hex b/src/test/resources/hex/C.ANDI.elf.hex new file mode 100644 index 0000000..841633f --- /dev/null +++ b/src/test/resources/hex/C.ANDI.elf.hex @@ -0,0 +1,45 @@ +:0200000480007A +:1000000001000100010001000100010001000100E8 +:1000100001000100010001000100010001000100D8 +:1000200001000100010001000100010001000100C8 +:1000300001000100010001000100010001000100B8 +:1000400001000100010001000100010001000100A8 +:100050000100010001000100010001000100010098 +:100060000100010001000100010001000100010088 +:100070000100010001000100010001000100010078 +:100080000100010001000100010001000100010068 +:100090000100010001000100010001000100010058 +:1000A0000100010001000100010001000100010048 +:1000B0000100010001000100010001000100010038 +:1000C0000100010001000100010001000100010028 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+00000000ffffffff0000000100000001 +00000000000000010000000100000000 +00000001000000000000000000000000 +00000001000000000000000100000000 diff --git a/src/test/resources/ref/I-SLTIU-01.reference_output b/src/test/resources/ref/I-SLTIU-01.reference_output index fae3854..26b9733 100644 --- a/src/test/resources/ref/I-SLTIU-01.reference_output +++ b/src/test/resources/ref/I-SLTIU-01.reference_output @@ -1,11 +1,11 @@ -00000001000000010000000100000000 -00000000000000010000000100000000 -00000001000000000000000100000001 -000000000000000000000000ffffffff -000000007fffffff0000000000000000 -00000001000000000000000100000000 -00000001000000000000000080000000 -00000000000000010000000100000000 -00000001000000010000000100000000 -00000001000000000000000100000000 -00000001000000000000000100000000 +00000001000000010000000100000000 +00000000000000010000000100000000 +00000001000000000000000100000001 +000000000000000000000000ffffffff +000000007fffffff0000000000000000 +00000001000000000000000100000000 +00000001000000000000000080000000 +00000000000000010000000100000000 +00000001000000010000000100000000 +00000001000000000000000100000000 +00000001000000000000000100000000 diff --git a/src/test/resources/ref/I-SLTU-01.reference_output b/src/test/resources/ref/I-SLTU-01.reference_output index aa67d8f..d72f1c5 100644 --- a/src/test/resources/ref/I-SLTU-01.reference_output +++ b/src/test/resources/ref/I-SLTU-01.reference_output @@ -1,12 +1,12 @@ -00000001000000010000000100000000 -00000000000000010000000100000000 -00000001000000000000000100000001 -000000000000000000000000ffffffff -000000007fffffff0000000000000000 -00000001000000000000000100000000 -00000001000000000000000080000000 -00000001000000000000000000000000 -000000010000000100000001ffffffff -00000000000000000000000100000000 -00000001000000000000000000000000 -00000001000000000000000100000000 +00000001000000010000000100000000 +00000000000000010000000100000000 +00000001000000000000000100000001 +000000000000000000000000ffffffff +000000007fffffff0000000000000000 +00000001000000000000000100000000 +00000001000000000000000080000000 +00000001000000000000000000000000 +000000010000000100000001ffffffff +00000000000000000000000100000000 +00000001000000000000000000000000 +00000001000000000000000100000000 diff --git a/src/test/resources/ref/I-SRA-01.reference_output b/src/test/resources/ref/I-SRA-01.reference_output index 5338082..6847b09 100644 --- a/src/test/resources/ref/I-SRA-01.reference_output +++ b/src/test/resources/ref/I-SRA-01.reference_output @@ -1,11 +1,11 @@ -00000000000000000000000000000000 -00000000000000010000000000000000 -00000000000000010000000000000000 -ffffffffffffffffffffffffffffffff -3fffffff7fffffffffffffffffffffff -00007fff7fffffff000000000000ffff -ffffffffffff0000c000000080000000 -d5e6f788abcdef10ffff800080000000 -fd5e6f78fabcdef1f579bde2eaf37bc4 -000000000000000000000000feaf37bc -ffffffffffff0ecac3b2a19087654321 +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +ffffffffffffffffffffffffffffffff +3fffffff7fffffffffffffffffffffff +00007fff7fffffff000000000000ffff +ffffffffffff0000c000000080000000 +d5e6f788abcdef10ffff800080000000 +fd5e6f78fabcdef1f579bde2eaf37bc4 +000000000000000000000000feaf37bc +ffffffffffff0ecac3b2a19087654321 diff --git a/src/test/resources/ref/I-SRAI-01.reference_output b/src/test/resources/ref/I-SRAI-01.reference_output index adbf5bf..76b4c6a 100644 --- a/src/test/resources/ref/I-SRAI-01.reference_output +++ b/src/test/resources/ref/I-SRAI-01.reference_output @@ -1,10 +1,10 @@ -00000000000000000000000000000000 -00000000000000010000000000000000 -00000000000000010000000000000000 -ffffffffffffffffffffffffffffffff -3fffffff7fffffffffffffffffffffff -00007fff7fffffff000000000000ffff -ffffffffffff0000c000000080000000 -d5e6f788abcdef10ffff800080000000 -fd5e6f78fabcdef1f579bde2eaf37bc4 -000000000000000000000000feaf37bc +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +ffffffffffffffffffffffffffffffff +3fffffff7fffffffffffffffffffffff +00007fff7fffffff000000000000ffff +ffffffffffff0000c000000080000000 +d5e6f788abcdef10ffff800080000000 +fd5e6f78fabcdef1f579bde2eaf37bc4 +000000000000000000000000feaf37bc diff --git a/src/test/resources/ref/I-SRL-01.reference_output b/src/test/resources/ref/I-SRL-01.reference_output index baa9cdf..eff39a5 100644 --- a/src/test/resources/ref/I-SRL-01.reference_output +++ b/src/test/resources/ref/I-SRL-01.reference_output @@ -1,11 +1,11 @@ -00000000000000000000000000000000 -00000000000000010000000000000000 -00000000000000010000000000000000 -000000010001ffff7fffffffffffffff -3fffffff7fffffff0000ffffffffffff -00007fff7fffffff000000000000ffff -00000001000100004000000080000000 -55e6f788abcdef100000800080000000 -055e6f780abcdef11579bde22af37bc4 -00000000000000000000000002af37bc -0000000100010eca43b2a19087654321 +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +000000010001ffff7fffffffffffffff +3fffffff7fffffff0000ffffffffffff +00007fff7fffffff000000000000ffff +00000001000100004000000080000000 +55e6f788abcdef100000800080000000 +055e6f780abcdef11579bde22af37bc4 +00000000000000000000000002af37bc +0000000100010eca43b2a19087654321 diff --git a/src/test/resources/ref/I-SRLI-01.reference_output b/src/test/resources/ref/I-SRLI-01.reference_output index 8cf21d8..85118f8 100644 --- a/src/test/resources/ref/I-SRLI-01.reference_output +++ b/src/test/resources/ref/I-SRLI-01.reference_output @@ -1,10 +1,10 @@ -00000000000000000000000000000000 -00000000000000010000000000000000 -00000000000000010000000000000000 -000000010001ffff7fffffffffffffff -3fffffff7fffffff0000ffffffffffff -00007fff7fffffff000000000000ffff -00000001000100004000000080000000 -55e6f788abcdef100000800080000000 -055e6f780abcdef11579bde22af37bc4 -00000000000000000000000002af37bc +00000000000000000000000000000000 +00000000000000010000000000000000 +00000000000000010000000000000000 +000000010001ffff7fffffffffffffff +3fffffff7fffffff0000ffffffffffff +00007fff7fffffff000000000000ffff +00000001000100004000000080000000 +55e6f788abcdef100000800080000000 +055e6f780abcdef11579bde22af37bc4 +00000000000000000000000002af37bc diff --git a/src/test/resources/ref/I-SUB-01.reference_output b/src/test/resources/ref/I-SUB-01.reference_output index 9bd5c2f..060a177 100644 --- a/src/test/resources/ref/I-SUB-01.reference_output +++ b/src/test/resources/ref/I-SUB-01.reference_output @@ -1,11 +1,11 @@ -00000001ffffffff0000000000000000 -00000001000000018000000080000001 -80000001800000020000000200000000 -00000000fffffffeffffffffffffffff -7fffffff7fffffff7fffffff80000000 -ffffffff00000000800000007ffffffe -800000017fffffff8000000080000000 -0000abcd000000010000000000000001 -0000abc90000abca0000abcb0000abcc -00000000000000000000abc70000abc8 -c96da7ecc96da7ec3692581400000000 +00000001ffffffff0000000000000000 +00000001000000018000000080000001 +80000001800000020000000200000000 +00000000fffffffeffffffffffffffff +7fffffff7fffffff7fffffff80000000 +ffffffff00000000800000007ffffffe +800000017fffffff8000000080000000 +0000abcd000000010000000000000001 +0000abc90000abca0000abcb0000abcc +00000000000000000000abc70000abc8 +c96da7ecc96da7ec3692581400000000 diff --git a/src/test/resources/ref/I-SW-01.reference_output b/src/test/resources/ref/I-SW-01.reference_output index 7ff05bd..a2c030c 100644 --- a/src/test/resources/ref/I-SW-01.reference_output +++ b/src/test/resources/ref/I-SW-01.reference_output @@ -1,4 +1,4 @@ -f77788f855f5f666f33344f411f1f222 -0fff00f0dd0d0eee0bbbcc0c99090aaa -765432109abcdef01122334400000000 -25814963147258361472583689abcdef +f77788f855f5f666f33344f411f1f222 +0fff00f0dd0d0eee0bbbcc0c99090aaa +765432109abcdef01122334400000000 +25814963147258361472583689abcdef diff --git a/src/test/resources/ref/I-XOR-01.reference_output b/src/test/resources/ref/I-XOR-01.reference_output index 514db10..2f48d7e 100644 --- a/src/test/resources/ref/I-XOR-01.reference_output +++ b/src/test/resources/ref/I-XOR-01.reference_output @@ -1,11 +1,11 @@ -ffffffff000000010000000000000000 -0000000100000001800000007fffffff -800000017ffffffefffffffe00000000 -00000000fffffffeffffffffffffffff -7fffffff7fffffff7fffffff80000000 -ffffffff00000000800000007ffffffe -7fffffff800000018000000080000000 -abcdffff0000007f00000000ffffffff -abcdffafabcdffa0abcdffbfabcdff80 -0000000000000000abcdffababcdffa8 -36925814369258143692581400000000 +ffffffff000000010000000000000000 +0000000100000001800000007fffffff +800000017ffffffefffffffe00000000 +00000000fffffffeffffffffffffffff +7fffffff7fffffff7fffffff80000000 +ffffffff00000000800000007ffffffe +7fffffff800000018000000080000000 +abcdffff0000007f00000000ffffffff +abcdffafabcdffa0abcdffbfabcdff80 +0000000000000000abcdffababcdffa8 +36925814369258143692581400000000 diff --git a/src/test/resources/ref/I-XORI-01.reference_output b/src/test/resources/ref/I-XORI-01.reference_output index dd8c914..6afaafb 100644 --- a/src/test/resources/ref/I-XORI-01.reference_output +++ b/src/test/resources/ref/I-XORI-01.reference_output @@ -1,11 +1,11 @@ -ffffffff000007ff0000000100000000 -0000000000000001fffff80000000000 -fffff80100000001fffffffe000007fe -00000000fffff800fffffffeffffffff -7ffffffe7fffffff000007ffffffffff -800007ff7fffffff800000007ffff800 -7fffffff800007ff8000000180000000 -abcdff80abcdffff7ffff80080000000 -abcdffa8abcdffafabcdffa0abcdffbf -000000010000000000000000abcdffab -36925814369258143692581436925814 +ffffffff000007ff0000000100000000 +0000000000000001fffff80000000000 +fffff80100000001fffffffe000007fe +00000000fffff800fffffffeffffffff +7ffffffe7fffffff000007ffffffffff +800007ff7fffffff800000007ffff800 +7fffffff800007ff8000000180000000 +abcdff80abcdffff7ffff80080000000 +abcdffa8abcdffafabcdffa0abcdffbf +000000010000000000000000abcdffab +36925814369258143692581436925814 diff --git a/src/test/resources/ref/MUL.reference_output b/src/test/resources/ref/MUL.reference_output new file mode 100644 index 0000000..8cdec59 --- /dev/null +++ b/src/test/resources/ref/MUL.reference_output @@ -0,0 +1,13 @@ +00000000000000000000000000000000 +ffffffff000000010000000000000000 +ffffffff00000000800000007fffffff +00000000800000008000000100000001 +8000000000000001800000017fffffff +80000000800000008000000000000000 +ffffffffffffffffffffffff00000000 +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +0000000000000000ffffffffffffffff diff --git a/src/test/resources/ref/MULH.reference_output b/src/test/resources/ref/MULH.reference_output new file mode 100644 index 0000000..5934644 --- /dev/null +++ b/src/test/resources/ref/MULH.reference_output @@ -0,0 +1,13 @@ +00000000000000000000000000000000 +ffffffff000000000000000000000000 +ffffffff00000000ffffffff00000000 +0000000000000000ffffffff00000000 +c00000003fffffffffffffff00000000 +c000000000000000ffffffff00000000 +ffffffffffffffffffffffff40000000 +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +0000000000000000ffffffffffffffff diff --git a/src/test/resources/ref/MULHSU.reference_output b/src/test/resources/ref/MULHSU.reference_output new file mode 100644 index 0000000..f6f8ef3 --- /dev/null +++ b/src/test/resources/ref/MULHSU.reference_output @@ -0,0 +1,13 @@ +00000000000000000000000000000000 +00000000000000000000000000000000 +ffffffff000000000000000000000000 +00000000ffffffffffffffffffffffff +3fffffff3fffffff7ffffffe00000000 +c000000080000000ffffffff00000000 +ffffffffffffffffffffffffc0000000 +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +0000000000000000ffffffffffffffff diff --git a/src/test/resources/ref/MULHU.reference_output b/src/test/resources/ref/MULHU.reference_output new file mode 100644 index 0000000..599e053 --- /dev/null +++ b/src/test/resources/ref/MULHU.reference_output @@ -0,0 +1,13 @@ +00000000000000000000000000000000 +00000000000000000000000000000000 +00000000000000000000000000000000 +000000007fffffff7ffffffefffffffe +3fffffff3fffffff7ffffffe00000000 +3fffffff7fffffff0000000000000000 +ffffffffffffffffffffffff40000000 +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +0000000000000000ffffffffffffffff diff --git a/src/test/resources/ref/REM.reference_output b/src/test/resources/ref/REM.reference_output new file mode 100644 index 0000000..1705fd4 --- /dev/null +++ b/src/test/resources/ref/REM.reference_output @@ -0,0 +1,13 @@ +00000000000000000000000000000000 +00000000000000000000000100000000 +00000000ffffffff0000000100000001 +7fffffffffffffffffffffff00000000 +7fffffff000000000000000000000000 +ffffffff000000000000000080000000 +ffffffffffffffffffffffff00000000 +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +0000000000000000ffffffffffffffff diff --git a/src/test/resources/ref/REMU.reference_output b/src/test/resources/ref/REMU.reference_output new file mode 100644 index 0000000..719349f --- /dev/null +++ b/src/test/resources/ref/REMU.reference_output @@ -0,0 +1,13 @@ +00000000000000000000000000000000 +00000001000000000000000100000000 +00000000ffffffff0000000100000001 +7fffffff7fffffff0000000100000000 +7fffffff000000007fffffff00000000 +00000001800000000000000080000000 +ffffffffffffffffffffffff00000000 +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +ffffffffffffffffffffffffffffffff +0000000000000000ffffffffffffffff From 0b8f6f6ed4bca55496469acc2b8199934df75fbb Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 12 Oct 2018 12:02:02 +0200 Subject: [PATCH 30/56] Fix broken C.LWSP reference_output --- src/test/resources/ref/C.LWSP.reference_output | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/test/resources/ref/C.LWSP.reference_output b/src/test/resources/ref/C.LWSP.reference_output index 5b82d66..574b7cb 100644 --- a/src/test/resources/ref/C.LWSP.reference_output +++ b/src/test/resources/ref/C.LWSP.reference_output @@ -1,5 +1,5 @@ 0000001f000000020000000100000000 -00000002000000010000000000000000 +000000020000000100000000ffffffff 00000006000000050000000400000003 0000000a000000090000000800000007 0000000e0000000d0000000c0000000b From eea92154aeee8a82c1407991965d624ce8c20459 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 12 Oct 2018 12:02:52 +0200 Subject: [PATCH 31/56] fetcher force PC LSB to be zero --- src/main/scala/vexriscv/plugin/Fetcher.scala | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 13c8742..fac3d4f 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -155,9 +155,12 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, pcReg := pc } + pc(0) := False + if(!pipeline(RVC_GEN)) pc(1) := False preOutput.valid := RegNext(True) init (False) preOutput.payload := pc + } val decodePc = ifGen(decodePcGen)(new Area { From 2b296900103a3b00335ff84af1cb7aad8f9e8d60 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 12 Oct 2018 12:24:52 +0200 Subject: [PATCH 32/56] Clean branch plugin lsb bit calculation BranchPlugin doesn't try anymore to catch exception when RVC is on --- .../scala/vexriscv/plugin/BranchPlugin.scala | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index b92d3b4..3d01821 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -52,9 +52,9 @@ trait PredictionInterface{ class BranchPlugin(earlyBranch : Boolean, catchAddressMisaligned : Boolean = false, - fenceiGenAsAJump : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{ - + fenceiGenAsAJump : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{ + def catchAddressMisalignedForReal = catchAddressMisaligned && !pipeline(RVC_GEN) lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory object BRANCH_CALC extends Stageable(UInt(32 bits)) @@ -131,7 +131,7 @@ class BranchPlugin(earlyBranch : Boolean, jumpInterface = pcManagerService.createJumpInterface(branchStage) - if (catchAddressMisaligned) { + if (catchAddressMisalignedForReal) { val exceptionService = pipeline.service(classOf[ExceptionService]) branchExceptionPort = exceptionService.newExceptionPort(branchStage) } @@ -186,7 +186,7 @@ class BranchPlugin(earlyBranch : Boolean, ).asUInt val branchAdder = branch_src1 + branch_src2 - insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ ((input(BRANCH_CTRL) === BranchCtrlEnum.JALR) ? False | branchAdder(0)) + insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ "0" } //Apply branchs (JAL,JALR, Bxx) @@ -199,8 +199,8 @@ class BranchPlugin(earlyBranch : Boolean, stages(indexOf(branchStage) - 1).arbitration.flushAll := True } - if(catchAddressMisaligned) { - branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && (jumpInterface.payload((if(pipeline(RVC_GEN)) 0 else 1) downto 0) =/= 0) + if(catchAddressMisalignedForReal) { + branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1) branchExceptionPort.code := 0 branchExceptionPort.badAddr := jumpInterface.payload } @@ -264,7 +264,7 @@ class BranchPlugin(earlyBranch : Boolean, } } val branchAdder = branch_src1 + branch_src2 - insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ ((input(BRANCH_CTRL) === BranchCtrlEnum.JALR) ? False | branchAdder(0)) + insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ "0" } @@ -279,8 +279,8 @@ class BranchPlugin(earlyBranch : Boolean, stages(indexOf(branchStage) - 1).arbitration.flushAll := True } - if(catchAddressMisaligned) { - val unalignedJump = input(BRANCH_DO) && (input(BRANCH_CALC)((if(pipeline(RVC_GEN)) 0 else 1) downto 0) =/= 0) + if(catchAddressMisalignedForReal) { + val unalignedJump = input(BRANCH_DO) && input(BRANCH_CALC)(1) branchExceptionPort.valid := arbitration.isValid && unalignedJump branchExceptionPort.code := 0 branchExceptionPort.badAddr := input(BRANCH_CALC) //pipeline.stages(pipeline.indexOf(branchStage)-1).input @@ -328,7 +328,7 @@ class BranchPlugin(earlyBranch : Boolean, ).asUInt val branchAdder = branch_src1 + branch_src2 - insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ ((input(BRANCH_CTRL) === BranchCtrlEnum.JALR) ? False | branchAdder(0)) + insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ "0" insert(NEXT_PC) := input(PC) + (if(pipeline(RVC_GEN)) ((input(IS_RVC)) ? U(2) | U(4)) else 4) } @@ -355,8 +355,8 @@ class BranchPlugin(earlyBranch : Boolean, stages(indexOf(branchStage) - 1).arbitration.flushAll := True } - if(catchAddressMisaligned) { - branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && (if(pipeline(RVC_GEN)) input(BRANCH_CALC)(0 downto 0) =/= 0 else input(BRANCH_CALC)(1 downto 0) =/= 0) + if(catchAddressMisalignedForReal) { + branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && input(BRANCH_CALC)(1) branchExceptionPort.code := 0 branchExceptionPort.badAddr := input(BRANCH_CALC) } From f903df4b66df0532bace2b6ad9a5c65e0910eba0 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 12 Oct 2018 17:13:54 +0200 Subject: [PATCH 33/56] sync --- src/main/scala/vexriscv/TestsWorkspace.scala | 2 +- .../scala/vexriscv/demo/SynthesisBench.scala | 22 +++++++++---------- .../vexriscv/TestIndividualFeatures.scala | 9 ++++---- 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index 70645ab..dc1feb4 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -38,7 +38,7 @@ object TestsWorkspace { prediction = STATIC, historyRamSizeLog2 = 10, catchAccessFault = true, - compressedGen = false, + compressedGen = true, busLatencyMin = 1, injectorStage = true ), diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index f0ec5cf..13ebde3 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -101,22 +101,22 @@ object VexRiscvSynthesisBench { } -// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) + val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) - val rtls = List(fullNoMmu) - -// val targets = XilinxStdTargets( -// vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" -// ) ++ AlteraStdTargets( -// quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", -// quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" -// ) ++ IcestormStdTargets().take(1) - +// val rtls = List(fullNoMmu) val targets = XilinxStdTargets( vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" - ) + ) ++ AlteraStdTargets( + quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", + quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" + ) ++ IcestormStdTargets().take(1) + + +// val targets = XilinxStdTargets( +// vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" +// ) // val targets = AlteraStdTargets( // quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala index b1ce354..a0f7f40 100644 --- a/src/test/scala/vexriscv/TestIndividualFeatures.scala +++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala @@ -268,8 +268,7 @@ class IBusDimension extends VexRiscvDimension("IBus") { val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL) val cmdForkOnSecondStage = r.nextBoolean() val cmdForkPersistence = r.nextBoolean() - val relaxedBusCmdValid = false // r.nextBoolean() && relaxedPcCalculation && prediction != DYNAMIC_TARGET - new VexRiscvPosition("Simple" + latency + (if(cmdForkOnSecondStage) "S2" else "") + (if(cmdForkPersistence) "P" else "") + (if(relaxedBusCmdValid) "Valid" else "") + (if(injectorStage) "InjStage" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{ + new VexRiscvPosition("Simple" + latency + (if(cmdForkOnSecondStage) "S2" else "") + (if(cmdForkPersistence) "P" else "") + (if(injectorStage) "InjStage" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{ override def testParam = "IBUS=SIMPLE" + (if(compressed) " COMPRESSED=yes" else "") override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin( resetVector = 0x80000000l, @@ -523,9 +522,9 @@ class TestIndividualFeatures extends FunSuite { // val seed = -2412372746600605141l -// val testId = Some(mutable.HashSet[Int](6,11,31,32,53,55,56,64,82)) -// val testId = Some(mutable.HashSet[Int](31)) -// val seed = 971825313472546699l +// val testId = Some(mutable.HashSet[Int](0,28,45,93)) +// val testId = Some(mutable.HashSet[Int](0)) +// val seed = 2094440864560126345l From 905abd5aaa8d3d95edbdf467a2fa7fb06b14d0a3 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 16 Oct 2018 13:07:30 +0200 Subject: [PATCH 34/56] Add wfiGenAsWait and wfiGenAsNop CsrPlugin cleaning Much cleaning in general Zephyr is running --- src/main/scala/vexriscv/TestsWorkspace.scala | 34 +++++++++-- src/main/scala/vexriscv/demo/Briey.scala | 2 +- src/main/scala/vexriscv/demo/GenFull.scala | 4 -- src/main/scala/vexriscv/demo/Murax.scala | 2 +- .../scala/vexriscv/demo/MuraxUtiles.scala | 5 ++ .../vexriscv/demo/VexRiscvAvalonForSim.scala | 2 +- .../VexRiscvAvalonWithIntegratedJtag.scala | 2 +- .../demo/VexRiscvAxi4WithIntegratedJtag.scala | 2 +- .../scala/vexriscv/plugin/CsrPlugin.scala | 25 ++++---- src/main/scala/vexriscv/plugin/Fetcher.scala | 6 +- .../vexriscv/plugin/IBusCachedPlugin.scala | 1 - .../vexriscv/plugin/IBusSimplePlugin.scala | 3 +- .../scala/vexriscv/plugin/RegFilePlugin.scala | 1 + src/test/cpp/regression/.cproject | 2 +- src/test/cpp/regression/.gitignore | 1 + src/test/cpp/regression/main.cpp | 56 ++++++++++++++++-- src/test/cpp/regression/makefile | 15 ++++- src/test/python/gcloud/remoteTest.py | 2 + src/test/python/gcloud/run.sh | 8 ++- .../vexriscv/TestIndividualFeatures.scala | 4 +- .../vexriscv/experimental/GenMicro.scala | 59 +++++++++++++++++-- 21 files changed, 188 insertions(+), 48 deletions(-) diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index dc1feb4..f421c46 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -35,10 +35,10 @@ object TestsWorkspace { resetVector = 0x80000000l, cmdForkOnSecondStage = false, cmdForkPersistence = false, - prediction = STATIC, + prediction = NONE, historyRamSizeLog2 = 10, - catchAccessFault = true, - compressedGen = true, + catchAccessFault = false, + compressedGen = false, busLatencyMin = 1, injectorStage = true ), @@ -67,7 +67,7 @@ object TestsWorkspace { // ), new DBusSimplePlugin( catchAddressMisaligned = true, - catchAccessFault = true, + catchAccessFault = false, earlyInjection = false ), // new DBusCachedPlugin( @@ -98,7 +98,7 @@ object TestsWorkspace { ioRange = _(31 downto 28) === 0xF ), new DecoderSimplePlugin( - catchIllegalInstruction = true + catchIllegalInstruction = false ), new RegFilePlugin( regFileReadyKind = plugin.ASYNC, @@ -129,7 +129,29 @@ object TestsWorkspace { divUnrollFactor = 1 ), // new DivPlugin, - new CsrPlugin(CsrPluginConfig.all2(0x80000020l).copy(deterministicInteruptionEntry = false, ebreakGen = true)), + new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/* + CsrPluginConfig( + catchIllegalAccess = false, + mvendorid = null, + marchid = null, + mimpid = null, + mhartid = null, + misaExtensionsInit = 0, + misaAccess = CsrAccess.READ_ONLY, + mtvecAccess = CsrAccess.WRITE_ONLY, + mtvecInit = 0x80000020l, + mepcAccess = CsrAccess.READ_WRITE, + mscratchGen = true, + mcauseAccess = CsrAccess.READ_ONLY, + mbadaddrAccess = CsrAccess.READ_ONLY, + mcycleAccess = CsrAccess.NONE, + minstretAccess = CsrAccess.NONE, + ecallGen = true, + ebreakGen = true, + wfiGenAsWait = false, + wfiGenAsNop = true, + ucycleAccess = CsrAccess.NONE + )), // new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( earlyBranch = true, diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala index 468b039..ca76f8b 100644 --- a/src/main/scala/vexriscv/demo/Briey.scala +++ b/src/main/scala/vexriscv/demo/Briey.scala @@ -146,7 +146,7 @@ object BrieyConfig{ mcycleAccess = CsrAccess.NONE, minstretAccess = CsrAccess.NONE, ecallGen = false, - wfiGen = false, + wfiGenAsWait = false, ucycleAccess = CsrAccess.NONE ) ), diff --git a/src/main/scala/vexriscv/demo/GenFull.scala b/src/main/scala/vexriscv/demo/GenFull.scala index 5f45df2..2030b05 100644 --- a/src/main/scala/vexriscv/demo/GenFull.scala +++ b/src/main/scala/vexriscv/demo/GenFull.scala @@ -12,10 +12,6 @@ object GenFull extends App{ def cpu() = new VexRiscv( config = VexRiscvConfig( plugins = List( - new PcManagerSimplePlugin( - resetVector = 0x80000000l, - relaxedPcCalculation = false - ), new IBusCachedPlugin( prediction = DYNAMIC, config = InstructionCacheConfig( diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index b833beb..675ef28 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -80,7 +80,7 @@ object MuraxConfig{ catchAccessFault = false, earlyInjection = false ), - new CsrPlugin(CsrPluginConfig.smallest(mtvecInit = if(withXip) 0xE0040020l else 0x80000000l)), + new CsrPlugin(CsrPluginConfig.smallest(mtvecInit = if(withXip) 0xE0040020l else 0x80000020l)), new DecoderSimplePlugin( catchIllegalInstruction = false ), diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala index 44ca954..9d1f044 100644 --- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala +++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala @@ -31,6 +31,11 @@ case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave master(cmd) slave(rsp) } + + def resizableAddress() : this.type = { + cmd.address.addTag(tagAutoResize) + this + } } class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{ diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala index 304a360..1e926ee 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala @@ -125,7 +125,7 @@ object VexRiscvAvalonForSim{ mcycleAccess = CsrAccess.NONE, minstretAccess = CsrAccess.NONE, ecallGen = false, - wfiGen = false, + wfiGenAsWait = false, ucycleAccess = CsrAccess.NONE ) ), diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala index 6ec2fd9..e4793d2 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala @@ -122,7 +122,7 @@ object VexRiscvAvalonWithIntegratedJtag{ mcycleAccess = CsrAccess.NONE, minstretAccess = CsrAccess.NONE, ecallGen = false, - wfiGen = false, + wfiGenAsWait = false, ucycleAccess = CsrAccess.NONE ) ), diff --git a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala index b8d7242..9f339fb 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala @@ -123,7 +123,7 @@ object VexRiscvAxi4WithIntegratedJtag{ mcycleAccess = CsrAccess.NONE, minstretAccess = CsrAccess.NONE, ecallGen = false, - wfiGen = false, + wfiGenAsWait = false, ucycleAccess = CsrAccess.NONE ) ), diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index d96e935..5420fd5 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -49,8 +49,10 @@ case class CsrPluginConfig( mcycleAccess : CsrAccess, minstretAccess : CsrAccess, ucycleAccess : CsrAccess, - wfiGen : Boolean, + wfiGenAsWait : Boolean, ecallGen : Boolean, + noCsrAlu : Boolean = false, + wfiGenAsNop : Boolean = false, ebreakGen : Boolean = false, supervisorGen : Boolean = false, sscratchGen : Boolean = false, @@ -92,7 +94,7 @@ object CsrPluginConfig{ mcycleAccess = CsrAccess.READ_WRITE, minstretAccess = CsrAccess.READ_WRITE, ecallGen = true, - wfiGen = true, + wfiGenAsWait = true, ucycleAccess = CsrAccess.READ_ONLY ) @@ -113,7 +115,7 @@ object CsrPluginConfig{ mcycleAccess = CsrAccess.READ_WRITE, minstretAccess = CsrAccess.READ_WRITE, ecallGen = true, - wfiGen = true, + wfiGenAsWait = true, ucycleAccess = CsrAccess.READ_ONLY, supervisorGen = true, sscratchGen = true, @@ -145,7 +147,7 @@ object CsrPluginConfig{ mcycleAccess = CsrAccess.NONE, minstretAccess = CsrAccess.NONE, ecallGen = false, - wfiGen = false, + wfiGenAsWait = false, ucycleAccess = CsrAccess.NONE ) @@ -166,7 +168,7 @@ object CsrPluginConfig{ mcycleAccess = CsrAccess.NONE, minstretAccess = CsrAccess.NONE, ecallGen = false, - wfiGen = false, + wfiGenAsWait = false, ucycleAccess = CsrAccess.NONE ) @@ -226,6 +228,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio import config._ import CsrAccess._ + assert(!(wfiGenAsNop && wfiGenAsWait)) + def xlen = 32 //Mannage ExceptionService calls @@ -247,7 +251,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio object EnvCtrlEnum extends SpinalEnum(binarySequential){ val NONE, XRET = newElement() - val WFI = if(wfiGen) newElement() else null + val WFI = if(wfiGenAsWait) newElement() else null val ECALL = if(ecallGen) newElement() else null val EBREAK = if(ebreakGen) newElement() else null } @@ -304,7 +308,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio MRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.XRET, HAS_SIDE_EFFECT -> True)), SRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.XRET, HAS_SIDE_EFFECT -> True)) )) - if(wfiGen) decoderService.add(WFI, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.WFI)) + if(wfiGenAsWait) decoderService.add(WFI, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.WFI)) + if(wfiGenAsNop) decoderService.add(WFI, Nil) if(ecallGen) decoderService.add(ECALL, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.ECALL, HAS_SIDE_EFFECT -> True)) if(ebreakGen) decoderService.add(EBREAK, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.EBREAK, HAS_SIDE_EFFECT -> True)) @@ -611,7 +616,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio interrupt.clearWhen(!allowInterrupts) val exception = if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionValids.last && allowException else False - val writeBackWasWfi = if(wfiGen) RegNext(writeBack.arbitration.isFiring && writeBack.input(ENV_CTRL) === EnvCtrlEnum.WFI) init(False) else False + val writeBackWasWfi = if(wfiGenAsWait) RegNext(writeBack.arbitration.isFiring && writeBack.input(ENV_CTRL) === EnvCtrlEnum.WFI) init(False) else False @@ -727,7 +732,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio execute plug new Area{ import execute._ //Manage WFI instructions - if(wfiGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){ + if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){ when(!interrupt){ arbitration.haltItself := True } @@ -776,7 +781,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val readData = B(0, 32 bits) // def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT // val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck) - val writeData = input(INSTRUCTION)(13).mux( + val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux( False -> writeSrc, True -> Mux(input(INSTRUCTION)(12), readData & ~writeSrc, readData | writeSrc) ) diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index fac3d4f..5aac4e7 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -11,8 +11,7 @@ import scala.collection.mutable.ArrayBuffer //TODO val killLastStage = jump.pcLoad.valid || decode.arbitration.isRemoved // DBUSSimple check memory halt execute optimization -abstract class IBusFetcherImpl(val catchAccessFault : Boolean, - val resetVector : BigInt, +abstract class IBusFetcherImpl(val resetVector : BigInt, val keepPcPlus4 : Boolean, val decodePcGen : Boolean, val compressedGen : Boolean, @@ -62,9 +61,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, fetcherHalt = False fetcherflushIt = False incomingInstruction = False - if(catchAccessFault) { - val exceptionService = pipeline.service(classOf[ExceptionService]) - } if(resetVector == null) externalResetVector = in(UInt(32 bits).setName("externalResetVector")) pipeline(RVC_GEN) = compressedGen diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index 2d57d23..e9623cf 100644 --- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -18,7 +18,6 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, config : InstructionCacheConfig, memoryTranslatorPortConfig : Any = null, injectorStage : Boolean = false) extends IBusFetcherImpl( - catchAccessFault = config.catchAccessFault, resetVector = resetVector, keepPcPlus4 = keepPcPlus4, decodePcGen = compressedGen, diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 5c4b476..41b4de3 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -62,7 +62,7 @@ object IBusSimpleBus{ } -case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMasterSlave { +case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle with IMasterSlave { var cmd = Stream(IBusSimpleCmd()) var rsp = Flow(IBusSimpleRsp()) @@ -155,7 +155,6 @@ class IBusSimplePlugin(resetVector : BigInt, injectorStage : Boolean = true, rspHoldValue : Boolean = false ) extends IBusFetcherImpl( - catchAccessFault = catchAccessFault, resetVector = resetVector, keepPcPlus4 = keepPcPlus4, decodePcGen = compressedGen, diff --git a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala index 12793b9..568b100 100644 --- a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala +++ b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala @@ -81,5 +81,6 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind, inputInit[Bits](REGFILE_WRITE_DATA, 0) inputInit[Bits](INSTRUCTION, 0) } + } } \ No newline at end of file diff --git a/src/test/cpp/regression/.cproject b/src/test/cpp/regression/.cproject index 57ac8aa..736b123 100644 --- a/src/test/cpp/regression/.cproject +++ b/src/test/cpp/regression/.cproject @@ -18,7 +18,7 @@ - + diff --git a/src/test/cpp/regression/.gitignore b/src/test/cpp/regression/.gitignore index b37f733..576890f 100644 --- a/src/test/cpp/regression/.gitignore +++ b/src/test/cpp/regression/.gitignore @@ -1,2 +1,3 @@ *.regTraceRef /freertos.gtkw +*.cproject diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index a5778c8..95e2511 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -301,6 +301,7 @@ public: status.mpie = status.mie; mepc = pc; pcWrite(mtvec.base << 2); + if(interrupt) livenessInterrupt = 0; //status.MPP := privilege } @@ -333,7 +334,35 @@ public: *csrPtr(csr) = value; } + + int livenessStep = 0; + int livenessInterrupt = 0; + virtual void liveness(bool mIntTimer, bool mIntExt){ + livenessStep++; + bool interruptRequest = (mie.mtie && mIntTimer); + if(interruptRequest){ + if(status.mie){ + livenessInterrupt++; + } + } else { + livenessInterrupt = 0; + } + + if(livenessStep > 1000){ + cout << "Liveness step failure" << endl; + fail(); + } + + if(livenessInterrupt > 1000){ + cout << "Liveness interrupt failure" << endl; + fail(); + } + + } + + virtual void step() { + livenessStep = 0; #define rd32 ((i >> 7) & 0x1F) #define iBits(lo, len) ((i >> lo) & ((1 << len)-1)) #define iBitsSigned(lo, len) int32_t(i) << (32-lo-len) >> (32-len) @@ -970,7 +999,7 @@ public: mTime += top->VexRiscv->writeBack_arbitration_isFiring*MTIME_INSTR_FACTOR; #endif #endif - #ifdef CSR + #ifdef TIMER_INTERRUPT top->timerInterrupt = mTime >= mTimeCmp ? 1 : 0; //if(mTime == mTimeCmp) printf("SIM timer tick\n"); #endif @@ -998,7 +1027,21 @@ public: fail(); } - if(riscvRefEnable) riscvRef.step(); + if(riscvRefEnable) { + riscvRef.step(); + bool mIntTimer = false; + bool mIntExt = false; + +#ifdef TIMER_INTERRUPT + mIntTimer = top->timerInterrupt; +#endif +#ifdef EXTERNAL_INTERRUPT + mIntExt = top->externalInterrupt; +#endif + + + riscvRef.liveness(mIntTimer, mIntExt); + } @@ -2576,10 +2619,13 @@ int main(int argc, char **argv, char **env) { for(int idx = 0;idx < 1;idx++){ - #ifdef DEBUG_PLUGIN_EXTERNAL + #if defined(DEBUG_PLUGIN_EXTERNAL) || defined(RUN_HEX) { - Workspace w("debugPluginExternal"); - w.loadHex("../../resources/hex/debugPluginExternal.hex"); + Workspace w("run"); + #ifdef RUN_HEX + //w.loadHex("/home/spinalvm/hdl/zephyr/zephyrSpinalHdl/samples/synchronization/build/zephyr/zephyr.hex"); + w.loadHex(RUN_HEX); + #endif w.noInstructionReadCheck(); //w.setIStall(false); //w.setDStall(false); diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile index 9ed8a3c..a5d5643 100644 --- a/src/test/cpp/regression/makefile +++ b/src/test/cpp/regression/makefile @@ -17,6 +17,7 @@ ATOMIC?=no NO_STALL?=no DEBUG_PLUGIN?=STD DEBUG_PLUGIN_EXTERNAL?=no +RUN_HEX=no CUSTOM_SIMD_ADD?=no CUSTOM_CSR?=no DHRYSTONE=yes @@ -41,8 +42,20 @@ ADDCFLAGS += -CFLAGS -DTHREAD_COUNT=${THREAD_COUNT} ifeq ($(DEBUG),yes) ADDCFLAGS += -CFLAGS -O0 -CFLAGS -g else - ADDCFLAGS += -CFLAGS -O3 + ADDCFLAGS += -CFLAGS -O3 +endif + +ifneq ($(shell dplus -VV | grep timerInterrupt ../../../../VexRiscv.v -w),) + ADDCFLAGS += -CFLAGS -DTIMER_INTERRUPT +endif + +ifneq ($(shell dplus -VV | grep externalInterrupt ../../../../VexRiscv.v -w),) + ADDCFLAGS += -CFLAGS -DEXTERNAL_INTERRUPT +endif + +ifneq ($(RUN_HEX),no) + ADDCFLAGS += -CFLAGS -DRUN_HEX='\"$(RUN_HEX)\"' endif ifeq ($(COMPRESSED),yes) diff --git a/src/test/python/gcloud/remoteTest.py b/src/test/python/gcloud/remoteTest.py index e1b62e1..37bd029 100755 --- a/src/test/python/gcloud/remoteTest.py +++ b/src/test/python/gcloud/remoteTest.py @@ -14,6 +14,8 @@ gci.stopScript("src/test/python/gcloud/stopScript.sh") gci.local("rm -rf archive.tar.gz; git ls-files -z | xargs -0 tar -czf archive.tar.gz") gci.localToRemote("archive.tar.gz", "") +gci.local("cd ../SpinalHDL; rm -rf spinal.tar.gz; git ls-files -z | xargs -0 tar -czf spinal.tar.gz") +gci.localToRemote("../SpinalHDL/spinal.tar.gz", "") gci.localToRemote("src/test/python/gcloud/run.sh", "") gci.remote("rm -rf run.txt; setsid nohup sh run.sh &> run.txt") diff --git a/src/test/python/gcloud/run.sh b/src/test/python/gcloud/run.sh index 7281216..0408d1d 100644 --- a/src/test/python/gcloud/run.sh +++ b/src/test/python/gcloud/run.sh @@ -1,9 +1,15 @@ rm -rf sbtTest.txt rm -rf VexRiscv +rm -rf SpinalHDL +#git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev +mkdir SpinalHDL +tar -xzf spinal.tar.gz -C SpinalHDL mkdir VexRiscv tar -xzf archive.tar.gz -C VexRiscv cd VexRiscv - +sudo git init +sudo git add * +sudo git commit -m miaou export VEXRISCV_REGRESSION_CONFIG_COUNT=16 export VEXRISCV_REGRESSION_FREERTOS_COUNT=yes sbt test diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala index a0f7f40..0c0dd7a 100644 --- a/src/test/scala/vexriscv/TestIndividualFeatures.scala +++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala @@ -523,8 +523,8 @@ class TestIndividualFeatures extends FunSuite { // val testId = Some(mutable.HashSet[Int](0,28,45,93)) -// val testId = Some(mutable.HashSet[Int](0)) -// val seed = 2094440864560126345l +// val testId = Some(mutable.HashSet[Int](9)) +// val seed = -8173808854505304814l diff --git a/src/test/scala/vexriscv/experimental/GenMicro.scala b/src/test/scala/vexriscv/experimental/GenMicro.scala index c98aac0..90666a7 100644 --- a/src/test/scala/vexriscv/experimental/GenMicro.scala +++ b/src/test/scala/vexriscv/experimental/GenMicro.scala @@ -13,12 +13,14 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin} object GenMicro extends App{ def cpu() = { val removeOneFetchStage = true + val pessimisticHazard = true val writeBackOpt = true - val onlyLoadWords = false val rspHoldValue = true + val withCompliantCsr = true + val withCompliantCsrPlusEmulation = true val earlyBranch = false val noShifter = false - val pessimisticHazard = true + val onlyLoadWords = false new VexRiscv( config = VexRiscvConfig( plugins = List( @@ -38,13 +40,13 @@ object GenMicro extends App{ rspHoldValue = rspHoldValue ), new DBusSimplePlugin( - catchAddressMisaligned = false, + catchAddressMisaligned = withCompliantCsr, catchAccessFault = false, earlyInjection = writeBackOpt, onlyLoadWords = onlyLoadWords ), new DecoderSimplePlugin( - catchIllegalInstruction = false + catchIllegalInstruction = withCompliantCsrPlusEmulation ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, @@ -71,10 +73,57 @@ object GenMicro extends App{ new HazardPessimisticPlugin(), new BranchPlugin( earlyBranch = earlyBranch, - catchAddressMisaligned = false + catchAddressMisaligned = withCompliantCsr, + fenceiGenAsAJump = withCompliantCsr ), new YamlPlugin("cpu0.yaml") ) ++ (if(noShifter) Nil else List(new LightShifterPlugin)) + ++ (if(!withCompliantCsr) Nil else List(new CsrPlugin( + config = if(withCompliantCsrPlusEmulation)CsrPluginConfig( + catchIllegalAccess = true, + mvendorid = null, + marchid = null, + mimpid = null, + mhartid = null, + misaExtensionsInit = 0, + misaAccess = CsrAccess.NONE, + mtvecAccess = CsrAccess.NONE, + mtvecInit = 0x80000020l, + mepcAccess = CsrAccess.NONE, + mscratchGen = false, + mcauseAccess = CsrAccess.READ_ONLY, + mbadaddrAccess = CsrAccess.NONE, + mcycleAccess = CsrAccess.NONE, + minstretAccess = CsrAccess.NONE, + ecallGen = false, + ebreakGen = false, + wfiGenAsWait = false, + wfiGenAsNop = false, + ucycleAccess = CsrAccess.NONE, + noCsrAlu = true + ) else CsrPluginConfig( + catchIllegalAccess = false, + mvendorid = null, + marchid = null, + mimpid = null, + mhartid = null, + misaExtensionsInit = 0, + misaAccess = CsrAccess.READ_ONLY, + mtvecAccess = CsrAccess.WRITE_ONLY, + mtvecInit = 0x80000020l, + mepcAccess = CsrAccess.READ_WRITE, + mscratchGen = true, + mcauseAccess = CsrAccess.READ_ONLY, + mbadaddrAccess = CsrAccess.READ_ONLY, + mcycleAccess = CsrAccess.NONE, + minstretAccess = CsrAccess.NONE, + ecallGen = true, + ebreakGen = true, + wfiGenAsWait = false, + wfiGenAsNop = true, + ucycleAccess = CsrAccess.NONE + ) + ))) ) ) } From 85e696b28688a76856a8eaf610967a5177a4c855 Mon Sep 17 00:00:00 2001 From: Morard Dany Date: Tue, 16 Oct 2018 14:53:41 +0200 Subject: [PATCH 35/56] CsrPlugin : Add mtvecModeGen --- .../scala/vexriscv/plugin/CsrPlugin.scala | 20 +++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 5420fd5..7dc5c78 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -51,6 +51,7 @@ case class CsrPluginConfig( ucycleAccess : CsrAccess, wfiGenAsWait : Boolean, ecallGen : Boolean, + mtvecModeGen : Boolean = false, noCsrAlu : Boolean = false, wfiGenAsNop : Boolean = false, ebreakGen : Boolean = false, @@ -224,7 +225,7 @@ trait IContextSwitching{ def isContextSwitching : Bool } -class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{ +class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{ import config._ import CsrAccess._ @@ -366,8 +367,15 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val base = Reg(UInt(2 bits)) init(U"01") allowUnsetRegToAvoidLatch val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) allowUnsetRegToAvoidLatch } - val mtvec = Reg(UInt(xlen bits)).allowUnsetRegToAvoidLatch - if(mtvecInit != null) mtvec init(mtvecInit) + + + val mtvec = new Area{ + val mode = Reg(Bits(2 bits)).allowUnsetRegToAvoidLatch + val base = Reg(UInt(xlen-2 bits)).allowUnsetRegToAvoidLatch + } + + if(mtvecInit != null) mtvec.mode init(mtvecInit & 0x3) + if(mtvecInit != null) mtvec.base init(mtvecInit / 4) val mepc = Reg(UInt(xlen bits)) val mstatus = new Area{ val MIE, MPIE = RegInit(False) @@ -407,7 +415,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio READ_WRITE(CSR.MIP, 3 -> mip.MSIP) READ_WRITE(CSR.MIE, 11 -> mie.MEIE, 7 -> mie.MTIE, 3 -> mie.MSIE) - mtvecAccess(CSR.MTVEC, mtvec) + mtvecAccess(CSR.MTVEC, 2 -> mtvec.base, 0 -> mtvec.mode) mepcAccess(CSR.MEPC, mepc) if(mscratchGen) READ_WRITE(CSR.MSCRATCH, mscratch) mcauseAccess(CSR.MCAUSE, xlen-1 -> mcause.interrupt, 0 -> mcause.exceptionCode) @@ -659,8 +667,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio } when(hadException || (interruptJump && !exception)){ - jumpInterface.valid := True - jumpInterface.payload := mtvec + jumpInterface.valid := True + jumpInterface.payload := (if(!mtvecModeGen) mtvec.base @@ "00" else (mtvec.mode === 0 || hadException) ? (mtvec.base @@ "00") | ((mtvec.base + trapCause) @@ "00") ) memory.arbitration.flushAll := True switch(targetPrivilege){ From 7c0f2dc713545b3421777f2542cf1bc9eb92d140 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 20 Oct 2018 12:39:20 +0200 Subject: [PATCH 36/56] Add SimpleBus object --- src/main/scala/vexriscv/demo/MuraxUtiles.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala index 9d1f044..213dc70 100644 --- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala +++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala @@ -22,7 +22,9 @@ case class SimpleBusRsp(config : SimpleBusConfig) extends Bundle{ val data = Bits(config.dataWidth bits) } - +object SimpleBus{ + def apply(addressWidth : Int, dataWidth : Int) = new SimpleBus(SimpleBusConfig(addressWidth, dataWidth)) +} case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave { val cmd = Stream(SimpleBusCmd(config)) val rsp = Flow(SimpleBusRsp(config)) From 7096c63d508a8379d41c328dbdf857e7c1fdb86b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 23 Oct 2018 17:46:31 +0200 Subject: [PATCH 37/56] Add more SimpleBus utilies --- .../scala/vexriscv/demo/MuraxUtiles.scala | 37 +++++++++++++++++-- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala index 213dc70..2827d85 100644 --- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala +++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala @@ -34,9 +34,40 @@ case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave slave(rsp) } - def resizableAddress() : this.type = { - cmd.address.addTag(tagAutoResize) - this + def <<(m : SimpleBus) : Unit = { + val s = this + assert(m.config.addressWidth >= s.config.addressWidth) + assert(m.config.dataWidth == s.config.dataWidth) + s.cmd.valid := m.cmd.valid + s.cmd.wr := m.cmd.wr + s.cmd.address := m.cmd.address.resized + s.cmd.data := m.cmd.data + s.cmd.mask := m.cmd.mask + m.cmd.ready := s.cmd.ready + m.rsp.valid := s.rsp.valid + m.rsp.data := s.rsp.data + } + def >>(s : SimpleBus) : Unit = s << this + + def cmdM2sPipe(): SimpleBus = { + val ret = cloneOf(this) + this.cmd.m2sPipe() >> ret.cmd + this.rsp << ret.rsp + ret + } + + def cmdS2mPipe(): SimpleBus = { + val ret = cloneOf(this) + this.cmd.s2mPipe() >> ret.cmd + this.rsp << ret.rsp + ret + } + + def rspPipe(): SimpleBus = { + val ret = cloneOf(this) + this.cmd >> ret.cmd + this.rsp << ret.rsp.stage() + ret } } From 372063582c9285b9069556c8e922aae7276a2710 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 23 Oct 2018 19:07:08 +0200 Subject: [PATCH 38/56] Improve CsrPlugin CombinatorialPaths --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 7dc5c78..ad804d1 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -643,6 +643,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception interruptJump := interrupt && pipelineLiberator.done val hadException = RegNext(exception) init(False) + pipelineLiberator.done.clearWhen(hadException) val targetPrivilege = CombInit(interruptTargetPrivilege) @@ -666,7 +667,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception } } - when(hadException || (interruptJump && !exception)){ + when(hadException || interruptJump){ jumpInterface.valid := True jumpInterface.payload := (if(!mtvecModeGen) mtvec.base @@ "00" else (mtvec.mode === 0 || hadException) ? (mtvec.base @@ "00") | ((mtvec.base + trapCause) @@ "00") ) memory.arbitration.flushAll := True From 4ed4af6a3e0089eadc980fae615102ac9665432c Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 24 Oct 2018 01:28:37 +0200 Subject: [PATCH 39/56] SrcPlugin add decodeAddSub option --- src/main/scala/vexriscv/plugin/SrcPlugin.scala | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/SrcPlugin.scala b/src/main/scala/vexriscv/plugin/SrcPlugin.scala index d319b9b..395c0a7 100644 --- a/src/main/scala/vexriscv/plugin/SrcPlugin.scala +++ b/src/main/scala/vexriscv/plugin/SrcPlugin.scala @@ -4,7 +4,7 @@ import vexriscv.{RVC_GEN, Riscv, VexRiscv} import spinal.core._ -class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{ +class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false, decodeAddSub : Boolean = false) extends Plugin[VexRiscv]{ override def build(pipeline: VexRiscv): Unit = { import pipeline._ import pipeline.config._ @@ -27,9 +27,10 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = ) } + val addSubStage = if(decodeAddSub) decode else execute if(separatedAddSub) { - execute plug new Area { - import execute._ + addSubStage plug new Area { + import addSubStage._ // ADD, SUB val add = (input(SRC1).asUInt + input(SRC2).asUInt).asBits.addAttribute("keep") @@ -45,8 +46,8 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = insert(SRC_LESS) := less } }else{ - execute plug new Area { - import execute._ + addSubStage plug new Area { + import addSubStage._ // ADD, SUB val addSub = (input(SRC1).asSInt + Mux(input(SRC_USE_SUB_LESS), ~input(SRC2), input(SRC2)).asSInt + Mux(input(SRC_USE_SUB_LESS), S(1), S(0))).asBits From 00bf84b7f8e26b1d696329f0250e07b55d452701 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 25 Oct 2018 23:47:05 +0200 Subject: [PATCH 40/56] Add SimpleBusInterconnect --- .../scala/vexriscv/demo/MuraxUtiles.scala | 62 ---- src/main/scala/vexriscv/demo/SimpleBus.scala | 280 ++++++++++++++++++ 2 files changed, 280 insertions(+), 62 deletions(-) create mode 100644 src/main/scala/vexriscv/demo/SimpleBus.scala diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala index 2827d85..e9be653 100644 --- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala +++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala @@ -9,68 +9,6 @@ import spinal.lib.misc.{HexTools, InterruptCtrl, Prescaler, Timer} import spinal.lib._ import vexriscv.plugin.{DBusSimpleBus, IBusSimpleBus} -case class SimpleBusConfig(addressWidth : Int, dataWidth : Int) - -case class SimpleBusCmd(config : SimpleBusConfig) extends Bundle{ - val wr = Bool - val address = UInt(config.addressWidth bits) - val data = Bits(config.dataWidth bits) - val mask = Bits(4 bit) -} - -case class SimpleBusRsp(config : SimpleBusConfig) extends Bundle{ - val data = Bits(config.dataWidth bits) -} - -object SimpleBus{ - def apply(addressWidth : Int, dataWidth : Int) = new SimpleBus(SimpleBusConfig(addressWidth, dataWidth)) -} -case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave { - val cmd = Stream(SimpleBusCmd(config)) - val rsp = Flow(SimpleBusRsp(config)) - - override def asMaster(): Unit = { - master(cmd) - slave(rsp) - } - - def <<(m : SimpleBus) : Unit = { - val s = this - assert(m.config.addressWidth >= s.config.addressWidth) - assert(m.config.dataWidth == s.config.dataWidth) - s.cmd.valid := m.cmd.valid - s.cmd.wr := m.cmd.wr - s.cmd.address := m.cmd.address.resized - s.cmd.data := m.cmd.data - s.cmd.mask := m.cmd.mask - m.cmd.ready := s.cmd.ready - m.rsp.valid := s.rsp.valid - m.rsp.data := s.rsp.data - } - def >>(s : SimpleBus) : Unit = s << this - - def cmdM2sPipe(): SimpleBus = { - val ret = cloneOf(this) - this.cmd.m2sPipe() >> ret.cmd - this.rsp << ret.rsp - ret - } - - def cmdS2mPipe(): SimpleBus = { - val ret = cloneOf(this) - this.cmd.s2mPipe() >> ret.cmd - this.rsp << ret.rsp - ret - } - - def rspPipe(): SimpleBus = { - val ret = cloneOf(this) - this.cmd >> ret.cmd - this.rsp << ret.rsp.stage() - ret - } -} - class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{ val io = new Bundle{ val iBus = slave(IBusSimpleBus(false)) diff --git a/src/main/scala/vexriscv/demo/SimpleBus.scala b/src/main/scala/vexriscv/demo/SimpleBus.scala new file mode 100644 index 0000000..923259c --- /dev/null +++ b/src/main/scala/vexriscv/demo/SimpleBus.scala @@ -0,0 +1,280 @@ +package vexriscv.demo + + +import spinal.core._ +import spinal.lib.bus.misc._ +import spinal.lib._ + +import scala.collection.mutable +import scala.collection.mutable.ArrayBuffer + +case class SimpleBusConfig(addressWidth : Int, dataWidth : Int) + +case class SimpleBusCmd(config : SimpleBusConfig) extends Bundle{ + val wr = Bool + val address = UInt(config.addressWidth bits) + val data = Bits(config.dataWidth bits) + val mask = Bits(4 bit) +} + +case class SimpleBusRsp(config : SimpleBusConfig) extends Bundle{ + val data = Bits(config.dataWidth bits) +} + +object SimpleBus{ + def apply(addressWidth : Int, dataWidth : Int) = new SimpleBus(SimpleBusConfig(addressWidth, dataWidth)) +} +case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave { + val cmd = Stream(SimpleBusCmd(config)) + val rsp = Flow(SimpleBusRsp(config)) + + override def asMaster(): Unit = { + master(cmd) + slave(rsp) + } + + def <<(m : SimpleBus) : Unit = { + val s = this + assert(m.config.addressWidth >= s.config.addressWidth) + assert(m.config.dataWidth == s.config.dataWidth) + s.cmd.valid := m.cmd.valid + s.cmd.wr := m.cmd.wr + s.cmd.address := m.cmd.address.resized + s.cmd.data := m.cmd.data + s.cmd.mask := m.cmd.mask + m.cmd.ready := s.cmd.ready + m.rsp.valid := s.rsp.valid + m.rsp.data := s.rsp.data + } + def >>(s : SimpleBus) : Unit = s << this + + def cmdM2sPipe(): SimpleBus = { + val ret = cloneOf(this) + this.cmd.m2sPipe() >> ret.cmd + this.rsp << ret.rsp + ret + } + + def cmdS2mPipe(): SimpleBus = { + val ret = cloneOf(this) + this.cmd.s2mPipe() >> ret.cmd + this.rsp << ret.rsp + ret + } + + def rspPipe(): SimpleBus = { + val ret = cloneOf(this) + this.cmd >> ret.cmd + this.rsp << ret.rsp.stage() + ret + } +} + + + + + +object SimpleBusArbiter{ + def apply(inputs : Seq[SimpleBus], pendingRspMax : Int): SimpleBus = { + val c = SimpleBusArbiter(inputs.head.config, inputs.size, pendingRspMax) + (inputs, c.io.inputs).zipped.foreach(_ <> _) + c.io.output + } +} + +case class SimpleBusArbiter(simpleBusConfig : SimpleBusConfig, portCount : Int, pendingRspMax : Int) extends Component{ + val io = new Bundle{ + val inputs = Vec(slave(SimpleBus(simpleBusConfig)), portCount) + val output = master(SimpleBus(simpleBusConfig)) + } + val logic = if(portCount == 1) new Area{ + io.output << io.inputs(0) + } else new Area { + val arbiter = StreamArbiterFactory.lowerFirst.transactionLock.build(SimpleBusCmd(simpleBusConfig), portCount) + (arbiter.io.inputs, io.inputs).zipped.foreach(_ <> _.cmd) + + val (outputCmdFork, routeCmdFork) = StreamFork2(arbiter.io.output) + io.output.cmd << outputCmdFork + + val rspRoute = routeCmdFork.translateWith(arbiter.io.chosen).throwWhen(routeCmdFork.wr).queueLowLatency(size = pendingRspMax, latency = 1) + rspRoute.ready := io.output.rsp.valid + + for ((input, id) <- io.inputs.zipWithIndex) { + input.rsp.valid := io.output.rsp.valid && rspRoute.payload === id + input.rsp.payload := io.output.rsp.payload + } + } +} + +class SimpleBusSlaveFactory(bus: SimpleBus) extends BusSlaveFactoryDelayed{ + bus.cmd.ready := True + + val readAtCmd = Flow(Bits(bus.config.dataWidth bits)) + val readAtRsp = readAtCmd.stage() + + val askWrite = (bus.cmd.valid && bus.cmd.wr).allowPruning() + val askRead = (bus.cmd.valid && !bus.cmd.wr).allowPruning() + val doWrite = (askWrite && bus.cmd.ready).allowPruning() + val doRead = (askRead && bus.cmd.ready).allowPruning() + + bus.rsp.valid := readAtRsp.valid + bus.rsp.data := readAtRsp.payload + + readAtCmd.valid := doRead + readAtCmd.payload := 0 + + def readAddress() : UInt = bus.cmd.address + def writeAddress() : UInt = bus.cmd.address + + override def readHalt(): Unit = bus.cmd.ready := False + override def writeHalt(): Unit = bus.cmd.ready := False + + override def build(): Unit = { + super.doNonStopWrite(bus.cmd.data) + + def doMappedElements(jobs : Seq[BusSlaveFactoryElement]) = super.doMappedElements( + jobs = jobs, + askWrite = askWrite, + askRead = askRead, + doWrite = doWrite, + doRead = doRead, + writeData = bus.cmd.data, + readData = readAtCmd.payload + ) + + switch(bus.cmd.address) { + for ((address, jobs) <- elementsPerAddress if address.isInstanceOf[SingleMapping]) { + is(address.asInstanceOf[SingleMapping].address) { + doMappedElements(jobs) + } + } + } + + for ((address, jobs) <- elementsPerAddress if !address.isInstanceOf[SingleMapping]) { + when(address.hit(bus.cmd.address)){ + doMappedElements(jobs) + } + } + } + + override def busDataWidth: Int = bus.config.dataWidth + override def wordAddressInc: Int = busDataWidth / 8 +} + +case class SimpleBusDecoder(busConfig : SimpleBusConfig, mappings : Seq[AddressMapping], pendingMax : Int = 7) extends Component{ + val io = new Bundle { + val input = slave(SimpleBus(busConfig)) + val outputs = Vec(master(SimpleBus(busConfig)), mappings.size) + } + val hits = Vec(Bool, mappings.size) + for((slaveBus, memorySpace, hit) <- (io.outputs, mappings, hits).zipped) yield { + hit := (memorySpace match { + case DefaultMapping => !hits.filterNot(_ == hit).orR + case _ => memorySpace.hit(io.input.cmd.address) + }) + slaveBus.cmd.valid := io.input.cmd.valid && hit + slaveBus.cmd.payload := io.input.cmd.payload.resized + } + val noHit = !hits.orR + io.input.cmd.ready := (hits,io.outputs).zipped.map(_ && _.cmd.ready).orR || noHit + + val rspPendingCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init(0) + rspPendingCounter := rspPendingCounter + U(io.input.cmd.fire && !io.input.cmd.wr) - U(io.input.rsp.valid) + val rspHits = RegNextWhen(hits, io.input.cmd.fire) + val rspPending = rspPendingCounter =/= 0 + val rspNoHit = !rspHits.orR + io.input.rsp.valid := io.outputs.map(_.rsp.valid).orR || (rspPending && rspNoHit) + io.input.rsp.payload := io.outputs.map(_.rsp.payload).read(OHToUInt(rspHits)) + + val cmdWait = (io.input.cmd.valid && rspPending && hits =/= rspHits) || rspPendingCounter === pendingMax + when(cmdWait){ + io.input.cmd.ready := False + io.outputs.foreach(_.cmd.valid := False) + } +} + +object SimpleBusConnectors{ + def direct(m : SimpleBus, s : SimpleBus) : Unit = m >> s +} + +case class SimpleBusInterconnect(){ + case class MasterModel(var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct) + case class SlaveModel(mapping : AddressMapping, var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct) + case class ConnectionModel(m : SimpleBus, s : SimpleBus, var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct) + + val masters = mutable.LinkedHashMap[SimpleBus, MasterModel]() + val slaves = mutable.LinkedHashMap[SimpleBus, SlaveModel]() + val connections = ArrayBuffer[ConnectionModel]() + var pendingRspMax = 2 + + + def setConnector(bus : SimpleBus)( connector : (SimpleBus,SimpleBus) => Unit): Unit = (masters.get(bus), slaves.get(bus)) match { + case (Some(m), _) => m.connector = connector + case (None, Some(s)) => s.connector = connector + } + + def setConnector(m : SimpleBus, s : SimpleBus)(connector : (SimpleBus,SimpleBus) => Unit): Unit = connections.find(e => e.m == m && e.s == s) match { + case Some(c) => c.connector = connector + } + + def addSlave(bus: SimpleBus,mapping: AddressMapping) : this.type = { + slaves(bus) = SlaveModel(mapping) + this + } + + def addSlaves(orders : (SimpleBus,AddressMapping)*) : this.type = { + orders.foreach(order => addSlave(order._1,order._2)) + this + } + + def addMaster(bus : SimpleBus, accesses : Seq[SimpleBus]) : this.type = { + masters(bus) = MasterModel() + for(s <- accesses) connections += ConnectionModel(bus, s) + this + } + + def addMasters(specs : (SimpleBus,Seq[SimpleBus])*) : this.type = { + specs.foreach(spec => addMaster(spec._1,spec._2)) + this + } + + def build(): Unit ={ + def applyName(bus : Bundle,name : String, onThat : Nameable) : Unit = { + if(bus.component == Component.current) + onThat.setCompositeName(bus,name) + else if(bus.isNamed) + onThat.setCompositeName(bus.component,bus.getName() + "_" + name) + } + + val connectionsInput = mutable.HashMap[ConnectionModel,SimpleBus]() + val connectionsOutput = mutable.HashMap[ConnectionModel,SimpleBus]() + for((bus, model) <- masters){ + val busConnections = connections.filter(_.m == bus) + val busSlaves = busConnections.map(c => slaves(c.s)) + val decoder = new SimpleBusDecoder(bus.config, busSlaves.map(_.mapping)) + applyName(bus,"decoder",decoder) + model.connector(bus, decoder.io.input) + for((connection, decoderOutput) <- (busConnections, decoder.io.outputs).zipped) { + connectionsInput(connection) = decoderOutput + } + } + + for((bus, model) <- slaves){ + val busConnections = connections.filter(_.s == bus) + val busMasters = busConnections.map(c => masters(c.m)) + val arbiter = new SimpleBusArbiter(bus.config, busMasters.size, pendingRspMax) + applyName(bus,"arbiter",arbiter) + model.connector(arbiter.io.output, bus) + for((connection, arbiterInput) <- (busConnections, arbiter.io.inputs).zipped) { + connectionsOutput(connection) = arbiterInput + } + } + + for(connection <- connections){ + connection.connector(connectionsInput(connection), connectionsOutput(connection)) + } + } + + //Will make SpinalHDL calling the build function at the end of the current component elaboration + Component.current.addPrePopTask(build) +} From 51de2b58208c94321e92244fe88245687314657b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 28 Oct 2018 02:18:08 +0200 Subject: [PATCH 41/56] SimpleBusInterconnect now adapte address width --- src/main/scala/vexriscv/demo/MuraxUtiles.scala | 2 +- src/main/scala/vexriscv/demo/SimpleBus.scala | 10 +++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala index e9be653..b940e8c 100644 --- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala +++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala @@ -52,7 +52,7 @@ class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{ } -class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{ +case class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{ val io = new Bundle{ val bus = slave(SimpleBus(simpleBusConfig)) } diff --git a/src/main/scala/vexriscv/demo/SimpleBus.scala b/src/main/scala/vexriscv/demo/SimpleBus.scala index 923259c..73eee31 100644 --- a/src/main/scala/vexriscv/demo/SimpleBus.scala +++ b/src/main/scala/vexriscv/demo/SimpleBus.scala @@ -271,7 +271,15 @@ case class SimpleBusInterconnect(){ } for(connection <- connections){ - connection.connector(connectionsInput(connection), connectionsOutput(connection)) + val m = connectionsInput(connection) + val s = connectionsOutput(connection) + if(m.config == s.config) { + connection.connector(m, s) + }else{ + val tmp = cloneOf(s) + m >> tmp //Adapte the bus kind. + connection.connector(tmp,s) + } } } From c8ac2140976ba95cc7cb1ba43f447ce0cc57d5e7 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 28 Oct 2018 02:18:27 +0200 Subject: [PATCH 42/56] Optimize CSR --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index ad804d1..37f45b9 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -593,9 +593,9 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception } } - when(exceptionValids.orR){ + when(exceptionValidsRegs.orR){ fetcher.haltIt() - fetcher.flushIt() +// fetcher.flushIt() } } else null From 978232fd63ba339a451e0451d393bfaee82e8230 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 3 Nov 2018 11:12:37 +0100 Subject: [PATCH 43/56] Optimise div iterative plugin done signal --- src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala index 3dd668b..717ad7f 100644 --- a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala @@ -95,7 +95,7 @@ class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mu val needRevert = Reg(Bool) val counter = Counter(32 / divUnrollFactor + 2) - val done = counter.willOverflowIfInc + val done = Reg(Bool) setWhen(counter === counter.end-1) clearWhen(!arbitration.isStuck) val result = Reg(Bits(32 bits)) when(arbitration.isValid && input(IS_DIV)){ when(!done){ From 662d76e3aa99e21e1c6029bd888b2931332057cf Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 3 Nov 2018 11:29:30 +0100 Subject: [PATCH 44/56] csrPlugin : avoid using ALU to get SRC1 (which was useless) --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 37f45b9..fda8474 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -282,8 +282,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception val defaultCsrActions = List[(Stageable[_ <: BaseType],Any)]( IS_CSR -> True, REGFILE_WRITE_VALID -> True, - ALU_BITWISE_CTRL -> AluBitwiseCtrlEnum.SRC1, - ALU_CTRL -> AluCtrlEnum.BITWISE + BYPASSABLE_MEMORY_STAGE -> True ) ++ (if(catchIllegalAccess) List(HAS_SIDE_EFFECT -> True) else Nil) val nonImmediatActions = defaultCsrActions ++ List( @@ -786,7 +785,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception val imm = IMM(input(INSTRUCTION)) - val writeSrc = input(REGFILE_WRITE_DATA) + val writeSrc = input(SRC1) val readData = B(0, 32 bits) // def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT // val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck) From b7f3ee5e06c97345473fe6a83b1650104ec0910f Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 5 Nov 2018 16:22:41 +0100 Subject: [PATCH 45/56] Fix CsrPlugin pipelined option --- src/main/scala/vexriscv/demo/SimpleBus.scala | 7 ++-- .../scala/vexriscv/plugin/CsrPlugin.scala | 40 +++++++++++++++---- 2 files changed, 37 insertions(+), 10 deletions(-) diff --git a/src/main/scala/vexriscv/demo/SimpleBus.scala b/src/main/scala/vexriscv/demo/SimpleBus.scala index 73eee31..4282376 100644 --- a/src/main/scala/vexriscv/demo/SimpleBus.scala +++ b/src/main/scala/vexriscv/demo/SimpleBus.scala @@ -161,11 +161,12 @@ class SimpleBusSlaveFactory(bus: SimpleBus) extends BusSlaveFactoryDelayed{ override def wordAddressInc: Int = busDataWidth / 8 } -case class SimpleBusDecoder(busConfig : SimpleBusConfig, mappings : Seq[AddressMapping], pendingMax : Int = 7) extends Component{ +case class SimpleBusDecoder(busConfig : SimpleBusConfig, mappings : Seq[AddressMapping], pendingMax : Int = 3) extends Component{ val io = new Bundle { val input = slave(SimpleBus(busConfig)) val outputs = Vec(master(SimpleBus(busConfig)), mappings.size) } + val hasDefault = mappings.contains(DefaultMapping) val hits = Vec(Bool, mappings.size) for((slaveBus, memorySpace, hit) <- (io.outputs, mappings, hits).zipped) yield { hit := (memorySpace match { @@ -175,14 +176,14 @@ case class SimpleBusDecoder(busConfig : SimpleBusConfig, mappings : Seq[AddressM slaveBus.cmd.valid := io.input.cmd.valid && hit slaveBus.cmd.payload := io.input.cmd.payload.resized } - val noHit = !hits.orR + val noHit = if(!hasDefault) !hits.orR else False io.input.cmd.ready := (hits,io.outputs).zipped.map(_ && _.cmd.ready).orR || noHit val rspPendingCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init(0) rspPendingCounter := rspPendingCounter + U(io.input.cmd.fire && !io.input.cmd.wr) - U(io.input.rsp.valid) val rspHits = RegNextWhen(hits, io.input.cmd.fire) val rspPending = rspPendingCounter =/= 0 - val rspNoHit = !rspHits.orR + val rspNoHit = if(!hasDefault) !rspHits.orR else False io.input.rsp.valid := io.outputs.map(_.rsp.valid).orR || (rspPending && rspNoHit) io.input.rsp.payload := io.outputs.map(_.rsp.payload).read(OHToUInt(rspHits)) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index fda8474..9cd99e6 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -66,6 +66,7 @@ case class CsrPluginConfig( satpAccess : CsrAccess = CsrAccess.NONE, medelegAccess : CsrAccess = CsrAccess.NONE, midelegAccess : CsrAccess = CsrAccess.NONE, + pipelineCsrRead : Boolean = false, deterministicInteruptionEntry : Boolean = false //Only used for simulatation purposes ){ assert(!ucycleAccess.canWrite) @@ -261,6 +262,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception object IS_CSR extends Stageable(Bool) object CSR_WRITE_OPCODE extends Stageable(Bool) object CSR_READ_OPCODE extends Stageable(Bool) + object PIPELINED_CSR_READ extends Stageable(Bits(32 bits)) var allowInterrupts : Bool = null var allowException : Bool = null @@ -282,7 +284,8 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception val defaultCsrActions = List[(Stageable[_ <: BaseType],Any)]( IS_CSR -> True, REGFILE_WRITE_VALID -> True, - BYPASSABLE_MEMORY_STAGE -> True + BYPASSABLE_EXECUTE_STAGE -> False, + BYPASSABLE_MEMORY_STAGE -> True ) ++ (if(catchIllegalAccess) List(HAS_SIDE_EFFECT -> True) else Nil) val nonImmediatActions = defaultCsrActions ++ List( @@ -785,26 +788,49 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception val imm = IMM(input(INSTRUCTION)) - val writeSrc = input(SRC1) + def writeSrc = input(SRC1) + // val readDataValid = True val readData = B(0, 32 bits) + val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) + val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) + val writeEnable = writeInstruction && ! arbitration.isStuck // && readDataRegValid + val readEnable = readInstruction && ! arbitration.isStuck // && !readDataRegValid + + + // def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT // val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck) +// val writeDataEnable = input(INSTRUCTION)(13) ? writeSrc | B"xFFFFFFFF" +// val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux( +// False -> writeSrc, +// True -> Mux(input(INSTRUCTION)(12), ~writeSrc, writeSrc) +// ) val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux( False -> writeSrc, True -> Mux(input(INSTRUCTION)(12), readData & ~writeSrc, readData | writeSrc) ) - val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) - val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) + // arbitration.haltItself setWhen(writeInstruction && !readDataRegValid) - val writeEnable = writeInstruction && ! arbitration.isStuck// && readDataRegValid - val readEnable = readInstruction && ! arbitration.isStuck// && !readDataRegValid + when(arbitration.isValid && input(IS_CSR)) { - output(REGFILE_WRITE_DATA) := readData + if(!pipelineCsrRead) output(REGFILE_WRITE_DATA) := readData arbitration.haltItself setWhen(blockedBySideEffects) } + if(pipelineCsrRead){ + insert(PIPELINED_CSR_READ) := readData + when(memory.arbitration.isValid && memory.input(IS_CSR)) { + memory.output(REGFILE_WRITE_DATA) := memory.input(PIPELINED_CSR_READ) + } + } +// +// Component.current.rework{ +// when(arbitration.isFiring && input(IS_CSR)) { +// memory.input(REGFILE_WRITE_DATA).getDrivingReg := readData +// } +// } //Translation of the csrMapping into real logic val csrAddress = input(INSTRUCTION)(csrRange) From b12e15b1121a99cce1c3444b59ccecc413d9d8b3 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 7 Nov 2018 19:27:49 +0100 Subject: [PATCH 46/56] branch/csr/muldiv minor improvments --- src/main/scala/vexriscv/TestsWorkspace.scala | 153 +++++++++--------- src/main/scala/vexriscv/demo/SimpleBus.scala | 94 +++++++---- .../scala/vexriscv/plugin/BranchPlugin.scala | 4 +- .../scala/vexriscv/plugin/CsrPlugin.scala | 4 +- .../vexriscv/plugin/DBusSimplePlugin.scala | 23 +-- .../plugin/MulDivIterativePlugin.scala | 11 +- 6 files changed, 164 insertions(+), 125 deletions(-) diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index f421c46..93d494f 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -31,64 +31,64 @@ object TestsWorkspace { SpinalConfig(mergeAsyncProcess = false, anonymSignalPrefix = "zz_").generateVerilog { val configFull = VexRiscvConfig( plugins = List( - new IBusSimplePlugin( - resetVector = 0x80000000l, - cmdForkOnSecondStage = false, - cmdForkPersistence = false, - prediction = NONE, - historyRamSizeLog2 = 10, - catchAccessFault = false, - compressedGen = false, - busLatencyMin = 1, - injectorStage = true - ), -// new IBusCachedPlugin( +// new IBusSimplePlugin( // resetVector = 0x80000000l, -// compressedGen = false, +// cmdForkOnSecondStage = false, +// cmdForkPersistence = false, // prediction = NONE, -// injectorStage = true, -// config = InstructionCacheConfig( -// cacheSize = 4096, -// bytePerLine = 32, -// wayCount = 1, -// addressWidth = 32, -// cpuDataWidth = 32, -// memDataWidth = 32, -// catchIllegalAccess = true, -// catchAccessFault = true, -// catchMemoryTranslationMiss = true, -// asyncTagMemory = false, -// twoCycleRam = false, -// twoCycleCache = true -// ), -// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( -// portTlbSize = 4 -// ) +// historyRamSizeLog2 = 10, +// catchAccessFault = false, +// compressedGen = false, +// busLatencyMin = 1, +// injectorStage = true // ), - new DBusSimplePlugin( - catchAddressMisaligned = true, - catchAccessFault = false, - earlyInjection = false + new IBusCachedPlugin( + resetVector = 0x80000000l, + compressedGen = false, + prediction = NONE, + injectorStage = true, + config = InstructionCacheConfig( + cacheSize = 4096, + bytePerLine = 32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchIllegalAccess = true, + catchAccessFault = true, + catchMemoryTranslationMiss = true, + asyncTagMemory = false, + twoCycleRam = false, + twoCycleCache = true + ), + memoryTranslatorPortConfig = MemoryTranslatorPortConfig( + portTlbSize = 4 + ) ), -// new DBusCachedPlugin( -// config = new DataCacheConfig( -// cacheSize = 4096, -// bytePerLine = 32, -// wayCount = 1, -// addressWidth = 32, -// cpuDataWidth = 32, -// memDataWidth = 32, -// catchAccessError = true, -// catchIllegal = true, -// catchUnaligned = true, -// catchMemoryTranslationMiss = true, -// atomicEntriesCount = 2 -// ), -//// memoryTranslatorPortConfig = null -// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( -// portTlbSize = 6 -// ) +// new DBusSimplePlugin( +// catchAddressMisaligned = true, +// catchAccessFault = false, +// earlyInjection = false // ), + new DBusCachedPlugin( + config = new DataCacheConfig( + cacheSize = 4096, + bytePerLine = 32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchAccessError = true, + catchIllegal = true, + catchUnaligned = true, + catchMemoryTranslationMiss = true, + atomicEntriesCount = 2 + ), +// memoryTranslatorPortConfig = null + memoryTranslatorPortConfig = MemoryTranslatorPortConfig( + portTlbSize = 6 + ) + ), // new StaticMemoryTranslatorPlugin( // ioRange = _(31 downto 28) === 0xF // ), @@ -129,29 +129,30 @@ object TestsWorkspace { divUnrollFactor = 1 ), // new DivPlugin, - new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/* - CsrPluginConfig( - catchIllegalAccess = false, - mvendorid = null, - marchid = null, - mimpid = null, - mhartid = null, - misaExtensionsInit = 0, - misaAccess = CsrAccess.READ_ONLY, - mtvecAccess = CsrAccess.WRITE_ONLY, - mtvecInit = 0x80000020l, - mepcAccess = CsrAccess.READ_WRITE, - mscratchGen = true, - mcauseAccess = CsrAccess.READ_ONLY, - mbadaddrAccess = CsrAccess.READ_ONLY, - mcycleAccess = CsrAccess.NONE, - minstretAccess = CsrAccess.NONE, - ecallGen = true, - ebreakGen = true, - wfiGenAsWait = false, - wfiGenAsNop = true, - ucycleAccess = CsrAccess.NONE - )), + new CsrPlugin(CsrPluginConfig.all(0x80000020l)), +// new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/* +// CsrPluginConfig( +// catchIllegalAccess = false, +// mvendorid = null, +// marchid = null, +// mimpid = null, +// mhartid = null, +// misaExtensionsInit = 0, +// misaAccess = CsrAccess.READ_ONLY, +// mtvecAccess = CsrAccess.WRITE_ONLY, +// mtvecInit = 0x80000020l, +// mepcAccess = CsrAccess.READ_WRITE, +// mscratchGen = true, +// mcauseAccess = CsrAccess.READ_ONLY, +// mbadaddrAccess = CsrAccess.READ_ONLY, +// mcycleAccess = CsrAccess.NONE, +// minstretAccess = CsrAccess.NONE, +// ecallGen = true, +// ebreakGen = true, +// wfiGenAsWait = false, +// wfiGenAsNop = true, +// ucycleAccess = CsrAccess.NONE +// )), // new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( earlyBranch = true, diff --git a/src/main/scala/vexriscv/demo/SimpleBus.scala b/src/main/scala/vexriscv/demo/SimpleBus.scala index 4282376..4239b67 100644 --- a/src/main/scala/vexriscv/demo/SimpleBus.scala +++ b/src/main/scala/vexriscv/demo/SimpleBus.scala @@ -75,14 +75,14 @@ case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave object SimpleBusArbiter{ - def apply(inputs : Seq[SimpleBus], pendingRspMax : Int): SimpleBus = { - val c = SimpleBusArbiter(inputs.head.config, inputs.size, pendingRspMax) + def apply(inputs : Seq[SimpleBus], pendingRspMax : Int, rspRouteQueue : Boolean, transactionLock : Boolean): SimpleBus = { + val c = SimpleBusArbiter(inputs.head.config, inputs.size, pendingRspMax, rspRouteQueue, transactionLock) (inputs, c.io.inputs).zipped.foreach(_ <> _) c.io.output } } -case class SimpleBusArbiter(simpleBusConfig : SimpleBusConfig, portCount : Int, pendingRspMax : Int) extends Component{ +case class SimpleBusArbiter(simpleBusConfig : SimpleBusConfig, portCount : Int, pendingRspMax : Int, rspRouteQueue : Boolean, transactionLock : Boolean = true) extends Component{ val io = new Bundle{ val inputs = Vec(slave(SimpleBus(simpleBusConfig)), portCount) val output = master(SimpleBus(simpleBusConfig)) @@ -90,17 +90,34 @@ case class SimpleBusArbiter(simpleBusConfig : SimpleBusConfig, portCount : Int, val logic = if(portCount == 1) new Area{ io.output << io.inputs(0) } else new Area { - val arbiter = StreamArbiterFactory.lowerFirst.transactionLock.build(SimpleBusCmd(simpleBusConfig), portCount) + val arbiterFactory = StreamArbiterFactory.lowerFirst + if(transactionLock) arbiterFactory.transactionLock else arbiterFactory.noLock + val arbiter = arbiterFactory.build(SimpleBusCmd(simpleBusConfig), portCount) (arbiter.io.inputs, io.inputs).zipped.foreach(_ <> _.cmd) - val (outputCmdFork, routeCmdFork) = StreamFork2(arbiter.io.output) - io.output.cmd << outputCmdFork + val rspRouteOh = Bits(portCount bits) - val rspRoute = routeCmdFork.translateWith(arbiter.io.chosen).throwWhen(routeCmdFork.wr).queueLowLatency(size = pendingRspMax, latency = 1) - rspRoute.ready := io.output.rsp.valid + val rsp = if(!rspRouteQueue) new Area{ + assert(pendingRspMax == 1) + val pending = RegInit(False) clearWhen(io.output.rsp.valid) + val target = Reg(Bits(portCount bits)) + rspRouteOh := target + when(io.output.cmd.fire && !io.output.cmd.wr){ + target := arbiter.io.chosenOH + pending := True + } + io.output.cmd << arbiter.io.output.haltWhen(pending && !io.output.rsp.valid) + } else new Area{ + val (outputCmdFork, routeCmdFork) = StreamFork2(arbiter.io.output) + io.output.cmd << outputCmdFork + + val rspRoute = routeCmdFork.translateWith(arbiter.io.chosenOH).throwWhen(routeCmdFork.wr).queueLowLatency(size = pendingRspMax, latency = 1) + rspRoute.ready := io.output.rsp.valid + rspRouteOh := rspRoute.payload + } for ((input, id) <- io.inputs.zipWithIndex) { - input.rsp.valid := io.output.rsp.valid && rspRoute.payload === id + input.rsp.valid := io.output.rsp.valid && rspRouteOh(id) input.rsp.payload := io.output.rsp.payload } } @@ -167,30 +184,34 @@ case class SimpleBusDecoder(busConfig : SimpleBusConfig, mappings : Seq[AddressM val outputs = Vec(master(SimpleBus(busConfig)), mappings.size) } val hasDefault = mappings.contains(DefaultMapping) - val hits = Vec(Bool, mappings.size) - for((slaveBus, memorySpace, hit) <- (io.outputs, mappings, hits).zipped) yield { - hit := (memorySpace match { - case DefaultMapping => !hits.filterNot(_ == hit).orR - case _ => memorySpace.hit(io.input.cmd.address) - }) - slaveBus.cmd.valid := io.input.cmd.valid && hit - slaveBus.cmd.payload := io.input.cmd.payload.resized - } - val noHit = if(!hasDefault) !hits.orR else False - io.input.cmd.ready := (hits,io.outputs).zipped.map(_ && _.cmd.ready).orR || noHit + val logic = if(hasDefault && mappings.size == 1){ + io.outputs(0) <> io.input + } else new Area { + val hits = Vec(Bool, mappings.size) + for ((slaveBus, memorySpace, hit) <- (io.outputs, mappings, hits).zipped) yield { + hit := (memorySpace match { + case DefaultMapping => !hits.filterNot(_ == hit).orR + case _ => memorySpace.hit(io.input.cmd.address) + }) + slaveBus.cmd.valid := io.input.cmd.valid && hit + slaveBus.cmd.payload := io.input.cmd.payload.resized + } + val noHit = if (!hasDefault) !hits.orR else False + io.input.cmd.ready := (hits, io.outputs).zipped.map(_ && _.cmd.ready).orR || noHit - val rspPendingCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init(0) - rspPendingCounter := rspPendingCounter + U(io.input.cmd.fire && !io.input.cmd.wr) - U(io.input.rsp.valid) - val rspHits = RegNextWhen(hits, io.input.cmd.fire) - val rspPending = rspPendingCounter =/= 0 - val rspNoHit = if(!hasDefault) !rspHits.orR else False - io.input.rsp.valid := io.outputs.map(_.rsp.valid).orR || (rspPending && rspNoHit) - io.input.rsp.payload := io.outputs.map(_.rsp.payload).read(OHToUInt(rspHits)) + val rspPendingCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0) + rspPendingCounter := rspPendingCounter + U(io.input.cmd.fire && !io.input.cmd.wr) - U(io.input.rsp.valid) + val rspHits = RegNextWhen(hits, io.input.cmd.fire) + val rspPending = rspPendingCounter =/= 0 + val rspNoHit = if (!hasDefault) !rspHits.orR else False + io.input.rsp.valid := io.outputs.map(_.rsp.valid).orR || (rspPending && rspNoHit) + io.input.rsp.payload := io.outputs.map(_.rsp.payload).read(OHToUInt(rspHits)) - val cmdWait = (io.input.cmd.valid && rspPending && hits =/= rspHits) || rspPendingCounter === pendingMax - when(cmdWait){ - io.input.cmd.ready := False - io.outputs.foreach(_.cmd.valid := False) + val cmdWait = (io.input.cmd.valid && rspPending && hits =/= rspHits) || rspPendingCounter === pendingMax + when(cmdWait) { + io.input.cmd.ready := False + io.outputs.foreach(_.cmd.valid := False) + } } } @@ -200,13 +221,14 @@ object SimpleBusConnectors{ case class SimpleBusInterconnect(){ case class MasterModel(var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct) - case class SlaveModel(mapping : AddressMapping, var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct) + case class SlaveModel(mapping : AddressMapping, var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct, var transactionLock : Boolean = true) case class ConnectionModel(m : SimpleBus, s : SimpleBus, var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct) val masters = mutable.LinkedHashMap[SimpleBus, MasterModel]() val slaves = mutable.LinkedHashMap[SimpleBus, SlaveModel]() val connections = ArrayBuffer[ConnectionModel]() - var pendingRspMax = 2 + var arbitrationPendingRspMaxDefault = 1 + val arbitrationRspRouteQueueDefault = false def setConnector(bus : SimpleBus)( connector : (SimpleBus,SimpleBus) => Unit): Unit = (masters.get(bus), slaves.get(bus)) match { @@ -228,6 +250,10 @@ case class SimpleBusInterconnect(){ this } + def noTransactionLockOn(slave : SimpleBus) : Unit = slaves(slave).transactionLock = false + def noTransactionLockOn(slaves : Seq[SimpleBus]) : Unit = slaves.foreach(noTransactionLockOn(_)) + + def addMaster(bus : SimpleBus, accesses : Seq[SimpleBus]) : this.type = { masters(bus) = MasterModel() for(s <- accesses) connections += ConnectionModel(bus, s) @@ -263,7 +289,7 @@ case class SimpleBusInterconnect(){ for((bus, model) <- slaves){ val busConnections = connections.filter(_.s == bus) val busMasters = busConnections.map(c => masters(c.m)) - val arbiter = new SimpleBusArbiter(bus.config, busMasters.size, pendingRspMax) + val arbiter = new SimpleBusArbiter(bus.config, busMasters.size, arbitrationPendingRspMaxDefault, arbitrationRspRouteQueueDefault, model.transactionLock) applyName(bus,"arbiter",arbiter) model.connector(arbiter.io.output, bus) for((connection, arbiterInput) <- (busConnections, arbiter.io.inputs).zipped) { diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index 3d01821..6cb4649 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -301,6 +301,7 @@ class BranchPlugin(earlyBranch : Boolean, //Do branch calculations (conditions + target PC) object NEXT_PC extends Stageable(UInt(32 bits)) + object TARGET_MISSMATCH extends Stageable(Bool) execute plug new Area { import execute._ @@ -330,6 +331,7 @@ class BranchPlugin(earlyBranch : Boolean, val branchAdder = branch_src1 + branch_src2 insert(BRANCH_CALC) := branchAdder(31 downto 1) @@ "0" insert(NEXT_PC) := input(PC) + (if(pipeline(RVC_GEN)) ((input(IS_RVC)) ? U(2) | U(4)) else 4) + insert(TARGET_MISSMATCH) := decode.input(PC) =/= input(BRANCH_CALC) } //Apply branchs (JAL,JALR, Bxx) @@ -337,7 +339,7 @@ class BranchPlugin(earlyBranch : Boolean, branchStage plug new Area { import branchStage._ - val predictionMissmatch = fetchPrediction.cmd.hadBranch =/= input(BRANCH_DO) || (input(BRANCH_DO) && fetchPrediction.cmd.targetPc =/= input(BRANCH_CALC)) + val predictionMissmatch = fetchPrediction.cmd.hadBranch =/= input(BRANCH_DO) || (input(BRANCH_DO) && input(TARGET_MISSMATCH)) fetchPrediction.rsp.wasRight := ! predictionMissmatch fetchPrediction.rsp.finalPc := input(BRANCH_CALC) fetchPrediction.rsp.sourceLastWord := { diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 9cd99e6..c003c01 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -793,8 +793,8 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception val readData = B(0, 32 bits) val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) - val writeEnable = writeInstruction && ! arbitration.isStuck // && readDataRegValid - val readEnable = readInstruction && ! arbitration.isStuck // && !readDataRegValid + val writeEnable = writeInstruction && ! blockedBySideEffects // && readDataRegValid + val readEnable = readInstruction && ! blockedBySideEffects // && !readDataRegValid diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 1df4272..a388287 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -184,11 +184,12 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, - earlyInjection : Boolean = false,/*, idempotentRegions : (UInt) => Bool = (x) => False*/ + earlyInjection : Boolean = false, /*, idempotentRegions : (UInt) => Bool = (x) => False*/ + emitCmdInMemoryStage : Boolean = false, onlyLoadWords : Boolean = false) extends Plugin[VexRiscv]{ var dBus : DBusSimpleBus = null - + assert(!(emitCmdInMemoryStage && earlyInjection)) object MEMORY_ENABLE extends Stageable(Bool) object MEMORY_READ_DATA extends Stageable(Bits(32 bits)) @@ -228,9 +229,11 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, ) + + val rspStage = if(emitCmdInMemoryStage) pipeline.writeBack else pipeline.memory if(catchAccessFault || catchAddressMisaligned) { val exceptionService = pipeline.service(classOf[ExceptionService]) - memoryExceptionPort = exceptionService.newExceptionPort(pipeline.memory) + memoryExceptionPort = exceptionService.newExceptionPort(rspStage) } } @@ -241,8 +244,9 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, dBus = master(DBusSimpleBus()).setName("dBus") //Emit dBus.cmd request - execute plug new Area{ - import execute._ + val cmdStage = if(emitCmdInMemoryStage) memory else execute + cmdStage plug new Area{ + import cmdStage._ insert(ALIGNEMENT_FAULT) := { if (catchAddressMisaligned) @@ -251,7 +255,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, False } - dBus.cmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.removeIt && !input(ALIGNEMENT_FAULT) + dBus.cmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.isFlushed && !input(ALIGNEMENT_FAULT) dBus.cmd.wr := input(INSTRUCTION)(5) dBus.cmd.address := input(SRC_ADD).asUInt dBus.cmd.size := input(INSTRUCTION)(13 downto 12).asUInt @@ -279,8 +283,9 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, } //Collect dBus.rsp read responses - memory plug new Area { - import memory._ + val rspStage = if(emitCmdInMemoryStage) writeBack else memory + rspStage plug new Area { + import rspStage._ insert(MEMORY_READ_DATA) := dBus.rsp.data @@ -335,7 +340,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, output(REGFILE_WRITE_DATA) := (if(!onlyLoadWords) rspFormated else input(MEMORY_READ_DATA)) } - if(!earlyInjection) + if(!earlyInjection && !emitCmdInMemoryStage) assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend") //formal diff --git a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala index 717ad7f..0619a27 100644 --- a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala @@ -4,12 +4,15 @@ import spinal.core._ import spinal.lib._ import vexriscv.{VexRiscv, _} -class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mulUnrollFactor : Int = 1, divUnrollFactor : Int = 1) extends Plugin[VexRiscv]{ +object MulDivIterativePlugin{ object IS_MUL extends Stageable(Bool) object IS_DIV extends Stageable(Bool) object IS_REM extends Stageable(Bool) object IS_RS1_SIGNED extends Stageable(Bool) object IS_RS2_SIGNED extends Stageable(Bool) +} +class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mulUnrollFactor : Int = 1, divUnrollFactor : Int = 1, customMul : (UInt, UInt, Stage, VexRiscv) => Area = null) extends Plugin[VexRiscv]{ + import MulDivIterativePlugin._ override def setup(pipeline: VexRiscv): Unit = { import Riscv._ @@ -67,7 +70,7 @@ class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mu val accumulator = Reg(UInt(65 bits)) - val mul = ifGen(genMul) (new Area{ + val mul = ifGen(genMul) (if(customMul != null) customMul(rs1,rs2,memory,pipeline) else new Area{ assert(isPow2(mulUnrollFactor)) val counter = Counter(32 / mulUnrollFactor + 1) val done = counter.willOverflowIfInc @@ -82,6 +85,9 @@ class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mu } output(REGFILE_WRITE_DATA) := ((input(INSTRUCTION)(13 downto 12) === B"00") ? accumulator(31 downto 0) | accumulator(63 downto 32)).asBits } + when(!arbitration.isStuck) { + counter.clear() + } }) @@ -139,7 +145,6 @@ class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mu rs1 := twoComplement(rs1Extended, rs1NeedRevert).resized rs2 := twoComplement(execute.input(RS2), rs2NeedRevert) - if(genMul) mul.counter.clear() if(genDiv) div.needRevert := (rs1NeedRevert ^ (rs2NeedRevert && !execute.input(INSTRUCTION)(13))) && !(execute.input(RS2) === 0 && execute.input(IS_RS2_SIGNED) && !execute.input(INSTRUCTION)(13)) if(genDiv) div.counter.clear() } From fb9ea11a5eda3da3b0688aeb0c426d829ad3074c Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 9 Nov 2018 05:41:43 +0100 Subject: [PATCH 47/56] Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE) --- src/main/scala/vexriscv/VexRiscv.scala | 32 ++++++++++++++----- .../scala/vexriscv/plugin/BranchPlugin.scala | 2 +- .../scala/vexriscv/plugin/CsrPlugin.scala | 27 +++++++++------- .../vexriscv/plugin/DBusSimplePlugin.scala | 4 +-- src/main/scala/vexriscv/plugin/Fetcher.scala | 14 +++++--- .../plugin/HazardPessimisticPlugin.scala | 2 +- .../vexriscv/plugin/HazardSimplePlugin.scala | 12 +++---- .../scala/vexriscv/plugin/RegFilePlugin.scala | 2 +- 8 files changed, 59 insertions(+), 36 deletions(-) diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index 7077096..6698586 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -6,14 +6,20 @@ import spinal.core._ import scala.collection.mutable.ArrayBuffer object VexRiscvConfig{ - def apply(plugins : Seq[Plugin[VexRiscv]] = ArrayBuffer()) : VexRiscvConfig = { + def apply(withMemoryStage : Boolean, withWriteBackStage : Boolean, plugins : Seq[Plugin[VexRiscv]]): VexRiscvConfig = { val config = VexRiscvConfig() config.plugins ++= plugins + config.withMemoryStage = withMemoryStage + config.withWriteBackStage = withWriteBackStage config } + + def apply(plugins : Seq[Plugin[VexRiscv]] = ArrayBuffer()) : VexRiscvConfig = apply(true,true,plugins) } case class VexRiscvConfig(){ + var withMemoryStage = true + var withWriteBackStage = true val plugins = ArrayBuffer[Plugin[VexRiscv]]() //Default Stageables @@ -76,8 +82,14 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ type T = VexRiscv import config._ - stages ++= List.fill(4)(new Stage()) - val /*prefetch :: fetch :: */decode :: execute :: memory :: writeBack :: Nil = stages.toList + stages ++= List.fill(2 + (if(withMemoryStage) 1 else 0) + (if(withWriteBackStage) 1 else 0))(new Stage()) + val decode = stages(0) + val execute = stages(1) + val memory = ifGen(withMemoryStage) (stages(2)) + val writeBack = ifGen(withWriteBackStage) (stages(3)) + + def stagesFromExecute = stages.dropWhile(_ != execute) + plugins ++= config.plugins //regression usage @@ -86,12 +98,16 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ decode.arbitration.isValid.addAttribute(Verilator.public) decode.arbitration.flushAll.addAttribute(Verilator.public) decode.arbitration.haltItself.addAttribute(Verilator.public) - writeBack.input(config.INSTRUCTION) keep() addAttribute(Verilator.public) - writeBack.input(config.PC) keep() addAttribute(Verilator.public) - writeBack.arbitration.isValid keep() addAttribute(Verilator.public) - writeBack.arbitration.isFiring keep() addAttribute(Verilator.public) + if(withWriteBackStage) { + writeBack.input(config.INSTRUCTION) keep() addAttribute (Verilator.public) + writeBack.input(config.PC) keep() addAttribute (Verilator.public) + writeBack.arbitration.isValid keep() addAttribute (Verilator.public) + writeBack.arbitration.isFiring keep() addAttribute (Verilator.public) + } decode.arbitration.removeIt.noBackendCombMerge //Verilator perf - memory.arbitration.removeIt.noBackendCombMerge + if(withMemoryStage){ + memory.arbitration.removeIt.noBackendCombMerge + } execute.arbitration.flushAll.noBackendCombMerge this(RVC_GEN) = false diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index 6cb4649..287e0e2 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -150,7 +150,7 @@ class BranchPlugin(earlyBranch : Boolean, decode.output(INSTRUCTION)(12) := False decode.output(INSTRUCTION)(22) := True } - execute.arbitration.haltByOther setWhen(execute.arbitration.isValid && execute.input(IS_FENCEI) && List(memory,writeBack).map(_.arbitration.isValid).orR) + execute.arbitration.haltByOther setWhen(execute.arbitration.isValid && execute.input(IS_FENCEI) && stagesFromExecute.tail.map(_.arbitration.isValid).asBits.orR) } } diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index c003c01..8bd32ae 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -317,7 +317,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception if(ebreakGen) decoderService.add(EBREAK, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.EBREAK, HAS_SIDE_EFFECT -> True)) val pcManagerService = pipeline.service(classOf[JumpService]) - jumpInterface = pcManagerService.createJumpInterface(pipeline.writeBack) + jumpInterface = pcManagerService.createJumpInterface(pipeline.stages.last) jumpInterface.valid := False jumpInterface.payload.assignDontCare() @@ -489,10 +489,13 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception import machineCsr._ import supervisorCsr._ + val lastStage = pipeline.stages.last + val beforeLastStage = pipeline.stages(pipeline.stages.size-2) + val stagesFromExecute = pipeline.stages.dropWhile(_ != execute) //Manage counters mcycle := mcycle + 1 - when(writeBack.arbitration.isFiring) { + when(lastStage.arbitration.isFiring) { minstret := minstret + 1 } @@ -541,7 +544,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception if(medelegAccess.canWrite) exceptionDelegators += DelegatorModel(medeleg,3, 1) - val mepcCaptureStage = if(exceptionPortsInfos.nonEmpty) writeBack else decode + val mepcCaptureStage = if(exceptionPortsInfos.nonEmpty) lastStage else decode //Aggregate all exception port and remove required instructions @@ -626,7 +629,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception interrupt.clearWhen(!allowInterrupts) val exception = if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionValids.last && allowException else False - val writeBackWasWfi = if(wfiGenAsWait) RegNext(writeBack.arbitration.isFiring && writeBack.input(ENV_CTRL) === EnvCtrlEnum.WFI) init(False) else False + val lastStageWasWfi = if(wfiGenAsWait) RegNext(lastStage.arbitration.isFiring && lastStage.input(ENV_CTRL) === EnvCtrlEnum.WFI) init(False) else False @@ -636,7 +639,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception decode.arbitration.haltByOther := True } - val done = !List(execute, memory, writeBack).map(_.arbitration.isValid).orR && fetcher.pcValid(mepcCaptureStage) + val done = !stagesFromExecute.map(_.arbitration.isValid).orR && fetcher.pcValid(mepcCaptureStage) if(exceptionPortCtrl != null) done.clearWhen(exceptionPortCtrl.exceptionValidsRegs.tail.orR) } @@ -672,7 +675,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception when(hadException || interruptJump){ jumpInterface.valid := True jumpInterface.payload := (if(!mtvecModeGen) mtvec.base @@ "00" else (mtvec.mode === 0 || hadException) ? (mtvec.base @@ "00") | ((mtvec.base + trapCause) @@ "00") ) - memory.arbitration.flushAll := True + beforeLastStage.arbitration.flushAll := True switch(targetPrivilege){ if(supervisorGen) is(1) { @@ -699,14 +702,14 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception } } - writeBack plug new Area{ - import writeBack._ - def previousStage = memory + lastStage plug new Area{ + import lastStage._ + //Manage MRET / SRET instructions when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.XRET) { jumpInterface.payload := mepc jumpInterface.valid := True - previousStage.arbitration.flushAll := True + beforeLastStage.arbitration.flushAll := True switch(input(INSTRUCTION)(29 downto 28)){ is(3){ mstatus.MIE := mstatus.MPIE @@ -750,12 +753,12 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception } } - decode.arbitration.haltByOther setWhen(List(execute,memory).map(s => s.arbitration.isValid && s.input(ENV_CTRL) === EnvCtrlEnum.XRET).orR) + decode.arbitration.haltByOther setWhen(stagesFromExecute.dropRight(1).map(s => s.arbitration.isValid && s.input(ENV_CTRL) === EnvCtrlEnum.XRET).asBits.orR) execute plug new Area { import execute._ def previousStage = decode - val blockedBySideEffects = List(memory, writeBack).map(s => s.arbitration.isValid).orR // && s.input(HAS_SIDE_EFFECT) to improve be less pessimistic + val blockedBySideEffects = stagesFromExecute.tail.map(s => s.arbitration.isValid).asBits().orR // && s.input(HAS_SIDE_EFFECT) to improve be less pessimistic val illegalAccess = arbitration.isValid && input(IS_CSR) val illegalInstruction = False diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index a388287..fd8bc3d 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -317,7 +317,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, } //Reformat read responses, REGFILE_WRITE_DATA overriding - val injectionStage = if(earlyInjection) memory else writeBack + val injectionStage = if(earlyInjection) memory else stages.last injectionStage plug new Area { import injectionStage._ @@ -340,7 +340,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, output(REGFILE_WRITE_DATA) := (if(!onlyLoadWords) rspFormated else input(MEMORY_READ_DATA)) } - if(!earlyInjection && !emitCmdInMemoryStage) + if(!earlyInjection && !emitCmdInMemoryStage && config.withWriteBackStage) assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend") //formal diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 5aac4e7..27a22e0 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -31,7 +31,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, assert(!(compressedGen && !decodePcGen)) var fetcherHalt : Bool = null var fetcherflushIt : Bool = null - lazy val pcValids = Vec(Bool, 4) + var pcValids : Vec[Bool] = null def pcValid(stage : Stage) = pcValids(pipeline.indexOf(stage)) var incomingInstruction : Bool = null override def incoming() = incomingInstruction @@ -50,6 +50,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, case class JumpInfo(interface : Flow[UInt], stage: Stage, priority : Int) val jumpInfos = ArrayBuffer[JumpInfo]() override def createJumpInterface(stage: Stage, priority : Int = 0): Flow[UInt] = { + assert(stage != null) val interface = Flow(UInt(32 bits)) jumpInfos += JumpInfo(interface,stage, priority) interface @@ -78,6 +79,8 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, } } } + + pcValids = Vec(Bool, pipeline.stages.size) } @@ -320,12 +323,13 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, }).tail } + val stagesFromExecute = stages.dropWhile(_ != execute).toList val nextPcCalc = if (decodePcGen) new Area{ - val valids = pcUpdatedGen(True, False :: List(execute, memory, writeBack).map(_.arbitration.isStuck), true) - pcValids := Vec(valids.takeRight(4)) + val valids = pcUpdatedGen(True, False :: stagesFromExecute.map(_.arbitration.isStuck), true) + pcValids := Vec(valids.takeRight(stages.size)) } else new Area{ - val valids = pcUpdatedGen(True, iBusRsp.stages.tail.map(!_.input.ready) ++ (if (injectorStage) List(!decodeInput.ready) else Nil) ++ List(execute, memory, writeBack).map(_.arbitration.isStuck), false) - pcValids := Vec(valids.takeRight(4)) + val valids = pcUpdatedGen(True, iBusRsp.stages.tail.map(!_.input.ready) ++ (if (injectorStage) List(!decodeInput.ready) else Nil) ++ stagesFromExecute.map(_.arbitration.isStuck), false) + pcValids := Vec(valids.takeRight(stages.size)) } val decodeRemoved = RegInit(False) setWhen(decode.arbitration.isRemoved) clearWhen(flush) //!decode.arbitration.isStuck || decode.arbitration.isFlushed diff --git a/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala b/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala index 9fb11a6..a16324f 100644 --- a/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala @@ -18,7 +18,7 @@ class HazardPessimisticPlugin() extends Plugin[VexRiscv] { import pipeline._ import pipeline.config._ - val writesInPipeline = List(execute,memory,writeBack).map(s => s.arbitration.isValid && s.input(REGFILE_WRITE_VALID)) :+ RegNext(writeBack.arbitration.isValid && writeBack.input(REGFILE_WRITE_VALID)) + val writesInPipeline = stages.dropWhile(_ != execute).map(s => s.arbitration.isValid && s.input(REGFILE_WRITE_VALID)) :+ RegNext(stages.last.arbitration.isValid && stages.last.input(REGFILE_WRITE_VALID)) decode.arbitration.haltItself.setWhen(decode.arbitration.isValid && writesInPipeline.orR) } } diff --git a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala index b18ae8e..51d059d 100644 --- a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala @@ -59,9 +59,9 @@ class HazardSimplePlugin(bypassExecute : Boolean = false, val address = Bits(5 bits) val data = Bits(32 bits) })) - writeBackWrites.valid := writeBack.output(REGFILE_WRITE_VALID) && writeBack.arbitration.isFiring - writeBackWrites.address := writeBack.output(INSTRUCTION)(rdRange) - writeBackWrites.data := writeBack.output(REGFILE_WRITE_DATA) + writeBackWrites.valid := stages.last.output(REGFILE_WRITE_VALID) && stages.last.arbitration.isFiring + writeBackWrites.address := stages.last.output(INSTRUCTION)(rdRange) + writeBackWrites.data := stages.last.output(REGFILE_WRITE_DATA) val writeBackBuffer = writeBackWrites.stage() val addr0Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === decode.input(INSTRUCTION)(rs1Range) @@ -84,9 +84,9 @@ class HazardSimplePlugin(bypassExecute : Boolean = false, } } - trackHazardWithStage(writeBack,bypassWriteBack,null) - trackHazardWithStage(memory ,bypassMemory ,BYPASSABLE_MEMORY_STAGE) - trackHazardWithStage(execute ,bypassExecute ,BYPASSABLE_EXECUTE_STAGE) + if(withWriteBackStage) trackHazardWithStage(writeBack,bypassWriteBack,null) + if(withMemoryStage) trackHazardWithStage(memory ,bypassMemory ,BYPASSABLE_MEMORY_STAGE) + trackHazardWithStage(execute ,bypassExecute , if(stages.last == execute) null else BYPASSABLE_EXECUTE_STAGE) if(!pessimisticUseSrc) { diff --git a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala index 568b100..74d0050 100644 --- a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala +++ b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala @@ -67,7 +67,7 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind, } //Write register file - val writeStage = if(writeRfInMemoryStage) memory else writeBack + val writeStage = if(writeRfInMemoryStage) memory else stages.last writeStage plug new Area { import writeStage._ From 0d92a5e5cddee85255673fa742db7bc558c97fca Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 12 Nov 2018 14:14:34 +0100 Subject: [PATCH 48/56] Add many little options to reduce area --- src/main/scala/vexriscv/Services.scala | 5 ++++ .../scala/vexriscv/plugin/BranchPlugin.scala | 6 ++-- .../scala/vexriscv/plugin/CsrPlugin.scala | 14 +++++---- .../vexriscv/plugin/DBusSimplePlugin.scala | 17 +++++++---- .../plugin/HazardPessimisticPlugin.scala | 2 +- .../vexriscv/plugin/HazardSimplePlugin.scala | 28 +++++++++--------- .../vexriscv/plugin/IBusSimplePlugin.scala | 17 ++++++++--- .../vexriscv/plugin/NoPipeliningPlugin.scala | 23 +++++++++++++++ .../scala/vexriscv/plugin/RegFilePlugin.scala | 29 ++++++++++++++----- .../scala/vexriscv/plugin/ShiftPlugins.scala | 3 +- src/test/python/gcloud/run.sh | 2 +- 11 files changed, 105 insertions(+), 41 deletions(-) create mode 100644 src/main/scala/vexriscv/plugin/NoPipeliningPlugin.scala diff --git a/src/main/scala/vexriscv/Services.scala b/src/main/scala/vexriscv/Services.scala index 5a6dba2..33adf07 100644 --- a/src/main/scala/vexriscv/Services.scala +++ b/src/main/scala/vexriscv/Services.scala @@ -47,6 +47,11 @@ trait ExceptionInhibitor{ def inhibateException() : Unit } +trait RegFileService{ + def readStage() : Stage +} + + case class MemoryTranslatorCmd() extends Bundle{ val isValid = Bool val virtualAddress = UInt(32 bits) diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index 287e0e2..876a07e 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -192,7 +192,7 @@ class BranchPlugin(earlyBranch : Boolean, //Apply branchs (JAL,JALR, Bxx) branchStage plug new Area { import branchStage._ - jumpInterface.valid := arbitration.isFiring && input(BRANCH_DO) + jumpInterface.valid := arbitration.isValid && !arbitration.isStuckByOthers && input(BRANCH_DO) jumpInterface.payload := input(BRANCH_CALC) when(jumpInterface.valid) { @@ -272,7 +272,7 @@ class BranchPlugin(earlyBranch : Boolean, val branchStage = if(earlyBranch) execute else memory branchStage plug new Area { import branchStage._ - jumpInterface.valid := input(BRANCH_DO) && arbitration.isFiring + jumpInterface.valid := arbitration.isValid && !arbitration.isStuckByOthers && input(BRANCH_DO) jumpInterface.payload := input(BRANCH_CALC) when(jumpInterface.valid) { @@ -349,7 +349,7 @@ class BranchPlugin(earlyBranch : Boolean, input(PC) } - jumpInterface.valid := arbitration.isFiring && predictionMissmatch //Probably just isValid instead of isFiring is better + jumpInterface.valid := arbitration.isValid && !arbitration.isStuckByOthers && predictionMissmatch //Probably just isValid instead of isFiring is better jumpInterface.payload := (input(BRANCH_DO) ? input(BRANCH_CALC) | input(NEXT_PC)) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 8bd32ae..7a68af6 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -763,9 +763,13 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception val illegalAccess = arbitration.isValid && input(IS_CSR) val illegalInstruction = False if(selfException != null) { - selfException.valid := illegalAccess || illegalInstruction - selfException.code := 2 + selfException.valid := False + selfException.code.assignDontCare() selfException.badAddr.assignDontCare() + if(catchIllegalAccess) when(illegalAccess || illegalInstruction){ + selfException.valid := True + selfException.code := 2 + } } //Manage MRET / SRET instructions @@ -796,9 +800,9 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception val readData = B(0, 32 bits) val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) - val writeEnable = writeInstruction && ! blockedBySideEffects // && readDataRegValid - val readEnable = readInstruction && ! blockedBySideEffects // && !readDataRegValid - + val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && readDataRegValid + val readEnable = readInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && !readDataRegValid + //arbitration.isStuckByOthers, in case of the hazardPlugin is in the executeStage // def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index fd8bc3d..4c9ad88 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -197,9 +197,12 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, object ALIGNEMENT_FAULT extends Stageable(Bool) var memoryExceptionPort : Flow[ExceptionCause] = null + var rspStage : Stage = null + override def setup(pipeline: VexRiscv): Unit = { import Riscv._ import pipeline.config._ + import pipeline._ val decoderService = pipeline.service(classOf[DecoderService]) @@ -230,7 +233,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, - val rspStage = if(emitCmdInMemoryStage) pipeline.writeBack else pipeline.memory + rspStage = if(stages.last == execute) execute else (if(emitCmdInMemoryStage) writeBack else memory) if(catchAccessFault || catchAddressMisaligned) { val exceptionService = pipeline.service(classOf[ExceptionService]) memoryExceptionPort = exceptionService.newExceptionPort(rspStage) @@ -243,11 +246,14 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, dBus = master(DBusSimpleBus()).setName("dBus") + //Emit dBus.cmd request val cmdStage = if(emitCmdInMemoryStage) memory else execute cmdStage plug new Area{ import cmdStage._ + val cmdSent = if(rspStage == execute) RegInit(False) setWhen(dBus.cmd.fire) clearWhen(!execute.arbitration.isStuck) else False + insert(ALIGNEMENT_FAULT) := { if (catchAddressMisaligned) (dBus.cmd.size === 2 && dBus.cmd.address(1 downto 0) =/= 0) || (dBus.cmd.size === 1 && dBus.cmd.address(0 downto 0) =/= 0) @@ -255,7 +261,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, False } - dBus.cmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.isFlushed && !input(ALIGNEMENT_FAULT) + dBus.cmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.isFlushed && !input(ALIGNEMENT_FAULT) && !cmdSent dBus.cmd.wr := input(INSTRUCTION)(5) dBus.cmd.address := input(SRC_ADD).asUInt dBus.cmd.size := input(INSTRUCTION)(13 downto 12).asUInt @@ -264,7 +270,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, U(1) -> input(RS2)(15 downto 0) ## input(RS2)(15 downto 0), default -> input(RS2)(31 downto 0) ) - when(arbitration.isValid && input(MEMORY_ENABLE) && !dBus.cmd.ready && !input(ALIGNEMENT_FAULT)){ + when(arbitration.isValid && input(MEMORY_ENABLE) && !dBus.cmd.ready && !input(ALIGNEMENT_FAULT) && !cmdSent){ arbitration.haltItself := True } @@ -283,9 +289,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, } //Collect dBus.rsp read responses - val rspStage = if(emitCmdInMemoryStage) writeBack else memory rspStage plug new Area { - import rspStage._ + val s = rspStage; import s._ insert(MEMORY_READ_DATA) := dBus.rsp.data @@ -313,7 +318,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, } - assert(!(dBus.rsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend") + if(rspStage != execute) assert(!(dBus.rsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend") } //Reformat read responses, REGFILE_WRITE_DATA overriding diff --git a/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala b/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala index a16324f..5a8f4d3 100644 --- a/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala @@ -19,6 +19,6 @@ class HazardPessimisticPlugin() extends Plugin[VexRiscv] { import pipeline.config._ val writesInPipeline = stages.dropWhile(_ != execute).map(s => s.arbitration.isValid && s.input(REGFILE_WRITE_VALID)) :+ RegNext(stages.last.arbitration.isValid && stages.last.input(REGFILE_WRITE_VALID)) - decode.arbitration.haltItself.setWhen(decode.arbitration.isValid && writesInPipeline.orR) + decode.arbitration.haltByOther.setWhen(decode.arbitration.isValid && writesInPipeline.orR) } } diff --git a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala index 51d059d..fecdcca 100644 --- a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala @@ -26,18 +26,20 @@ class HazardSimplePlugin(bypassExecute : Boolean = false, val src0Hazard = False val src1Hazard = False + val readStage = service(classOf[RegFileService]).readStage() + def trackHazardWithStage(stage : Stage,bypassable : Boolean, runtimeBypassable : Stageable[Bool]): Unit ={ val runtimeBypassableValue = if(runtimeBypassable != null) stage.input(runtimeBypassable) else True - val addr0Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === decode.input(INSTRUCTION)(rs1Range) - val addr1Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === decode.input(INSTRUCTION)(rs2Range) + val addr0Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === readStage.input(INSTRUCTION)(rs1Range) + val addr1Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === readStage.input(INSTRUCTION)(rs2Range) when(stage.arbitration.isValid && stage.input(REGFILE_WRITE_VALID)) { if (bypassable) { when(runtimeBypassableValue) { when(addr0Match) { - decode.input(RS1) := stage.output(REGFILE_WRITE_DATA) + readStage.input(RS1) := stage.output(REGFILE_WRITE_DATA) } when(addr1Match) { - decode.input(RS2) := stage.output(REGFILE_WRITE_DATA) + readStage.input(RS2) := stage.output(REGFILE_WRITE_DATA) } } } @@ -64,15 +66,15 @@ class HazardSimplePlugin(bypassExecute : Boolean = false, writeBackWrites.data := stages.last.output(REGFILE_WRITE_DATA) val writeBackBuffer = writeBackWrites.stage() - val addr0Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === decode.input(INSTRUCTION)(rs1Range) - val addr1Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === decode.input(INSTRUCTION)(rs2Range) + val addr0Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === readStage.input(INSTRUCTION)(rs1Range) + val addr1Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === readStage.input(INSTRUCTION)(rs2Range) when(writeBackBuffer.valid) { if (bypassWriteBackBuffer) { when(addr0Match) { - decode.input(RS1) := writeBackBuffer.data + readStage.input(RS1) := writeBackBuffer.data } when(addr1Match) { - decode.input(RS2) := writeBackBuffer.data + readStage.input(RS2) := writeBackBuffer.data } } else { when(addr0Match) { @@ -86,20 +88,20 @@ class HazardSimplePlugin(bypassExecute : Boolean = false, if(withWriteBackStage) trackHazardWithStage(writeBack,bypassWriteBack,null) if(withMemoryStage) trackHazardWithStage(memory ,bypassMemory ,BYPASSABLE_MEMORY_STAGE) - trackHazardWithStage(execute ,bypassExecute , if(stages.last == execute) null else BYPASSABLE_EXECUTE_STAGE) + if(readStage != execute) trackHazardWithStage(execute ,bypassExecute , if(stages.last == execute) null else BYPASSABLE_EXECUTE_STAGE) if(!pessimisticUseSrc) { - when(!decode.input(RS1_USE)) { + when(!readStage.input(RS1_USE)) { src0Hazard := False } - when(!decode.input(RS2_USE)) { + when(!readStage.input(RS2_USE)) { src1Hazard := False } } - when(decode.arbitration.isValid && (src0Hazard || src1Hazard)){ - decode.arbitration.haltItself := True + when(readStage.arbitration.isValid && (src0Hazard || src1Hazard)){ + readStage.arbitration.haltByOther := True } } } diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 41b4de3..cffc86a 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -153,7 +153,8 @@ class IBusSimplePlugin(resetVector : BigInt, busLatencyMin : Int = 1, pendingMax : Int = 7, injectorStage : Boolean = true, - rspHoldValue : Boolean = false + rspHoldValue : Boolean = false, + singleInstructionPipeline : Boolean = false ) extends IBusFetcherImpl( resetVector = resetVector, keepPcPlus4 = keepPcPlus4, @@ -168,7 +169,7 @@ class IBusSimplePlugin(resetVector : BigInt, var iBus : IBusSimpleBus = null var decodeExceptionPort : Flow[ExceptionCause] = null - if(rspHoldValue) assert(busLatencyMin == 1) + if(rspHoldValue) assert(busLatencyMin <= 1) override def setup(pipeline: VexRiscv): Unit = { super.setup(pipeline) @@ -197,7 +198,12 @@ class IBusSimplePlugin(resetVector : BigInt, //This implementation keep the cmd on the bus until it's executed or the the pipeline is flushed def stage = iBusRsp.stages(if(cmdForkOnSecondStage) 1 else 0) stage.halt setWhen(stage.input.valid && (!cmd.valid || !cmd.ready)) - cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax + if(singleInstructionPipeline) { + cmd.valid := stage.input.valid && pendingCmd =/= pendingMax && !stages.map(_.arbitration.isValid).orR + assert(injectorStage == false) + assert(iBusRsp.stages.dropWhile(_ != stage).length <= 2) + }else + cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax cmd.pc := stage.input.payload(31 downto 2) @@ "00" } else new Area{ //This implementation keep the cmd on the bus until it's executed, even if the pipeline is flushed @@ -230,7 +236,10 @@ class IBusSimplePlugin(resetVector : BigInt, c.io.flush := flush rspBufferOutput << c.io.pop } else new Area{ - rspBufferOutput << iBus.rsp.throwWhen(discardCounter =/= 0).toStream + val rspStream = iBus.rsp.throwWhen(discardCounter =/= 0).toStream + val validReg = RegInit(False) setWhen(rspStream.valid) clearWhen(rspBufferOutput.ready) + rspBufferOutput << rspStream + rspBufferOutput.valid setWhen(validReg) } val fetchRsp = FetchRsp() diff --git a/src/main/scala/vexriscv/plugin/NoPipeliningPlugin.scala b/src/main/scala/vexriscv/plugin/NoPipeliningPlugin.scala new file mode 100644 index 0000000..b4ad22b --- /dev/null +++ b/src/main/scala/vexriscv/plugin/NoPipeliningPlugin.scala @@ -0,0 +1,23 @@ +package vexriscv.plugin + +import spinal.core._ +import spinal.lib._ +import vexriscv._ + + +class NoPipeliningPlugin() extends Plugin[VexRiscv] { + + override def setup(pipeline: VexRiscv): Unit = { + import pipeline.config._ + val decoderService = pipeline.service(classOf[DecoderService]) + decoderService.addDefault(HAS_SIDE_EFFECT, False) + } + + override def build(pipeline: VexRiscv): Unit = { + import pipeline._ + import pipeline.config._ + + val writesInPipeline = stages.dropWhile(_ != execute).map(s => s.arbitration.isValid && s.input(REGFILE_WRITE_VALID)) :+ RegNext(stages.last.arbitration.isValid && stages.last.input(REGFILE_WRITE_VALID)) + decode.arbitration.haltByOther.setWhen(stagesFromExecute.map(_.arbitration.isValid).orR) + } +} diff --git a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala index 74d0050..5f202b6 100644 --- a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala +++ b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala @@ -13,13 +13,17 @@ object SYNC extends RegFileReadKind class RegFilePlugin(regFileReadyKind : RegFileReadKind, zeroBoot : Boolean = false, + x0Init : Boolean = true, writeRfInMemoryStage : Boolean = false, - readInExecute : Boolean = false) extends Plugin[VexRiscv]{ + readInExecute : Boolean = false, + syncUpdateOnStall : Boolean = true) extends Plugin[VexRiscv] with RegFileService{ import Riscv._ // assert(!writeRfInMemoryStage) + override def readStage(): Stage = if(readInExecute) pipeline.execute else pipeline.decode + override def setup(pipeline: VexRiscv): Unit = { import pipeline.config._ val decoderService = pipeline.service(classOf[DecoderService]) @@ -51,7 +55,7 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind, val srcInstruction = regFileReadyKind match{ case `ASYNC` => input(INSTRUCTION) case `SYNC` if !readInExecute => input(INSTRUCTION_ANTICIPATED) - case `SYNC` if readInExecute => Mux(execute.arbitration.isStuck, execute.input(INSTRUCTION), decode.input(INSTRUCTION)) + case `SYNC` if readInExecute => if(syncUpdateOnStall) Mux(execute.arbitration.isStuck, execute.input(INSTRUCTION), decode.input(INSTRUCTION)) else decode.input(INSTRUCTION) } val regFileReadAddress1 = srcInstruction(Riscv.rs1Range).asUInt @@ -59,7 +63,9 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind, val (rs1Data,rs2Data) = regFileReadyKind match{ case `ASYNC` => (global.regFile.readAsync(regFileReadAddress1),global.regFile.readAsync(regFileReadAddress2)) - case `SYNC` => (global.regFile.readSync(regFileReadAddress1),global.regFile.readSync(regFileReadAddress2)) + case `SYNC` => + val enable = if(!syncUpdateOnStall) !readStage.arbitration.isStuck else null + (global.regFile.readSync(regFileReadAddress1, enable),global.regFile.readSync(regFileReadAddress2, enable)) } insert(RS1) := rs1Data @@ -77,10 +83,19 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind, regFileWrite.data := output(REGFILE_WRITE_DATA) //CPU will initialise constant register zero in the first cycle - regFileWrite.valid setWhen(RegNext(False) init(True)) - inputInit[Bits](REGFILE_WRITE_DATA, 0) - inputInit[Bits](INSTRUCTION, 0) + if(x0Init) { + val boot = RegNext(False) init (True) + regFileWrite.valid setWhen (boot) + if (writeStage != execute) { + inputInit[Bits](REGFILE_WRITE_DATA, 0) + inputInit[Bits](INSTRUCTION, 0) + } else { + when(boot) { + regFileWrite.address := 0 + regFileWrite.data := 0 + } + } + } } - } } \ No newline at end of file diff --git a/src/main/scala/vexriscv/plugin/ShiftPlugins.scala b/src/main/scala/vexriscv/plugin/ShiftPlugins.scala index 4f34847..563ba27 100644 --- a/src/main/scala/vexriscv/plugin/ShiftPlugins.scala +++ b/src/main/scala/vexriscv/plugin/ShiftPlugins.scala @@ -152,7 +152,8 @@ class LightShifterPlugin extends Plugin[VexRiscv]{ val isShift = input(SHIFT_CTRL) =/= ShiftCtrlEnum.DISABLE val amplitudeReg = Reg(UInt(5 bits)) val amplitude = isActive ? amplitudeReg | input(SRC2)(4 downto 0).asUInt - val shiftInput = isActive ? memory.input(REGFILE_WRITE_DATA) | input(SRC1) + val shiftReg = ifGen(!withMemoryStage) (RegNextWhen(execute.output(REGFILE_WRITE_DATA), !arbitration.isStuckByOthers)) + val shiftInput = isActive ? (if(withMemoryStage) memory.input(REGFILE_WRITE_DATA) else shiftReg) | input(SRC1) val done = amplitude(4 downto 1) === 0 diff --git a/src/test/python/gcloud/run.sh b/src/test/python/gcloud/run.sh index 0408d1d..cd16afb 100644 --- a/src/test/python/gcloud/run.sh +++ b/src/test/python/gcloud/run.sh @@ -10,7 +10,7 @@ cd VexRiscv sudo git init sudo git add * sudo git commit -m miaou -export VEXRISCV_REGRESSION_CONFIG_COUNT=16 +export VEXRISCV_REGRESSION_CONFIG_COUNT=64 export VEXRISCV_REGRESSION_FREERTOS_COUNT=yes sbt test cd .. From cc48fc740310973f35b92e497090993045d35ee2 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 13 Nov 2018 15:17:35 +0100 Subject: [PATCH 49/56] add fenceiGenAsANop --- src/main/scala/vexriscv/plugin/BranchPlugin.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index 876a07e..ad1c57f 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -52,7 +52,8 @@ trait PredictionInterface{ class BranchPlugin(earlyBranch : Boolean, catchAddressMisaligned : Boolean = false, - fenceiGenAsAJump : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{ + fenceiGenAsAJump : Boolean = false, + fenceiGenAsANop : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{ def catchAddressMisalignedForReal = catchAddressMisaligned && !pipeline(RVC_GEN) lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory @@ -127,6 +128,10 @@ class BranchPlugin(earlyBranch : Boolean, )) } + if(fenceiGenAsANop){ + decoderService.add(List(FENCEI -> List())) + } + val pcManagerService = pipeline.service(classOf[JumpService]) jumpInterface = pcManagerService.createJumpInterface(branchStage) From 75d4d049d7ebdf246013738eee75546638ad35c8 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 16 Nov 2018 17:06:11 +0100 Subject: [PATCH 50/56] Add shadow regfile various cleaning --- .../scala/vexriscv/ip/InstructionCache.scala | 24 +++++++++++++ .../scala/vexriscv/plugin/CsrPlugin.scala | 3 +- .../vexriscv/plugin/DBusSimplePlugin.scala | 29 +++++++++++---- .../vexriscv/plugin/IBusSimplePlugin.scala | 16 ++++++++- .../scala/vexriscv/plugin/IntAluPlugin.scala | 8 ++--- .../scala/vexriscv/plugin/RegFilePlugin.scala | 36 +++++++++++++------ .../scala/vexriscv/plugin/ShiftPlugins.scala | 6 ++-- 7 files changed, 96 insertions(+), 26 deletions(-) diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala index 508bf9f..8ba3ba4 100644 --- a/src/main/scala/vexriscv/ip/InstructionCache.scala +++ b/src/main/scala/vexriscv/ip/InstructionCache.scala @@ -6,6 +6,7 @@ import spinal.lib._ import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4ReadOnly} import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig} import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig} +import vexriscv.demo.{SimpleBus, SimpleBusConfig} case class InstructionCacheConfig( cacheSize : Int, @@ -45,6 +46,11 @@ case class InstructionCacheConfig( cacheSize : Int, constantBurstBehavior = true ) + def getSimpleBusConfig() = SimpleBusConfig( + addressWidth = 32, + dataWidth = 32 + ) + def getWishboneConfig() = WishboneConfig( addressWidth = 30, dataWidth = 32, @@ -178,6 +184,24 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit mm } + + def toSimpleBus(): SimpleBus = { + val simpleBusConfig = p.getSimpleBusConfig() + val bus = SimpleBus(simpleBusConfig) + val counter = Counter(p.burstSize, bus.cmd.fire) + bus.cmd.valid := cmd.valid + bus.cmd.address := cmd.address(31 downto widthOf(counter.value) + 2) @@ counter @@ U"00" + bus.cmd.wr := False + bus.cmd.mask.assignDontCare() + bus.cmd.data.assignDontCare() + cmd.ready := counter.willOverflow + rsp.valid := bus.rsp.valid + rsp.data := bus.rsp.payload.data + rsp.error := False + bus + } + + def toWishbone(): Wishbone = { val wishboneConfig = p.getWishboneConfig() val bus = Wishbone(wishboneConfig) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 7a68af6..e209e68 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -200,7 +200,8 @@ trait CsrInterface{ } def rw(csrAddress : Int, thats : (Int, Data)*) : Unit = for(that <- thats) rw(csrAddress,that._1, that._2) - def r [T <: Data](csrAddress : Int, thats : (Int, Data)*) : Unit = for(that <- thats) r(csrAddress,that._1, that._2) + def w(csrAddress : Int, thats : (Int, Data)*) : Unit = for(that <- thats) w(csrAddress,that._1, that._2) + def r(csrAddress : Int, thats : (Int, Data)*) : Unit = for(that <- thats) r(csrAddress,that._1, that._2) def rw[T <: Data](csrAddress : Int, that : T): Unit = rw(csrAddress,0,that) def w[T <: Data](csrAddress : Int, that : T): Unit = w(csrAddress,0,that) def r [T <: Data](csrAddress : Int, that : T): Unit = r(csrAddress,0,that) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 4c9ad88..3f4479c 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -6,6 +6,7 @@ import spinal.lib._ import spinal.lib.bus.amba4.axi._ import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig} import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig} +import vexriscv.demo.SimpleBus import vexriscv.ip.DataCacheMemCmd @@ -131,11 +132,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ mm.read := cmdStage.valid && !cmdStage.wr mm.write := cmdStage.valid && cmdStage.wr mm.address := (cmdStage.address >> 2) @@ U"00" - mm.writeData := cmdStage.size.mux ( - U(0) -> cmdStage.data(7 downto 0) ## cmdStage.data(7 downto 0) ## cmdStage.data(7 downto 0) ## cmdStage.data(7 downto 0), - U(1) -> cmdStage.data(15 downto 0) ## cmdStage.data(15 downto 0), - default -> cmdStage.data(31 downto 0) - ) + mm.writeData := cmdStage.data(31 downto 0) mm.byteEnable := (cmdStage.size.mux ( U(0) -> B"0001", U(1) -> B"0011", @@ -179,6 +176,25 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ rsp.error := False //TODO bus } + + def toSimpleBus() : SimpleBus = { + val bus = SimpleBus(32,32) + bus.cmd.valid := cmd.valid + bus.cmd.wr := cmd.wr + bus.cmd.address := cmd.address.resized + bus.cmd.data := cmd.data + bus.cmd.mask := cmd.size.mux( + 0 -> B"0001", + 1 -> B"0011", + default -> B"1111" + ) |<< cmd.address(1 downto 0) + cmd.ready := bus.cmd.ready + + rsp.ready := bus.rsp.valid + rsp.data := bus.rsp.data + + bus + } } @@ -311,9 +327,10 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, memoryExceptionPort.valid := True } } - when(!(arbitration.isValid && input(MEMORY_ENABLE))){ + when(!(arbitration.isValid && input(MEMORY_ENABLE) && (if(cmdStage == rspStage) !arbitration.isStuckByOthers else True))){ memoryExceptionPort.valid := False } + memoryExceptionPort.badAddr := input(REGFILE_WRITE_DATA).asUInt //Drived by IntAluPlugin } diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index cffc86a..756d372 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -6,6 +6,7 @@ import spinal.lib._ import spinal.lib.bus.amba4.axi._ import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig} import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig} +import vexriscv.demo.SimpleBus @@ -135,6 +136,18 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit bus } + def toSimpleBus(): SimpleBus = { + val bus = SimpleBus(32,32) + bus.cmd.arbitrationFrom(cmd) + bus.cmd.address := cmd.pc.resized + bus.cmd.wr := False + bus.cmd.mask.assignDontCare() + bus.cmd.data.assignDontCare() + rsp.valid := bus.rsp.valid + rsp.inst := bus.rsp.payload.data + rsp.error := False + bus + } } @@ -202,8 +215,9 @@ class IBusSimplePlugin(resetVector : BigInt, cmd.valid := stage.input.valid && pendingCmd =/= pendingMax && !stages.map(_.arbitration.isValid).orR assert(injectorStage == false) assert(iBusRsp.stages.dropWhile(_ != stage).length <= 2) - }else + }else { cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax + } cmd.pc := stage.input.payload(31 downto 2) @@ "00" } else new Area{ //This implementation keep the cmd on the bus until it's executed, even if the pipeline is flushed diff --git a/src/main/scala/vexriscv/plugin/IntAluPlugin.scala b/src/main/scala/vexriscv/plugin/IntAluPlugin.scala index 2610aac..1b7467e 100644 --- a/src/main/scala/vexriscv/plugin/IntAluPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IntAluPlugin.scala @@ -84,10 +84,10 @@ class IntAluPlugin extends Plugin[VexRiscv]{ import execute._ val bitwise = input(ALU_BITWISE_CTRL).mux( - AluBitwiseCtrlEnum.AND -> (input(SRC1) & input(SRC2)), - AluBitwiseCtrlEnum.OR -> (input(SRC1) | input(SRC2)), - AluBitwiseCtrlEnum.XOR -> (input(SRC1) ^ input(SRC2)), - AluBitwiseCtrlEnum.SRC1 -> input(SRC1) + AluBitwiseCtrlEnum.AND -> (input(SRC1) & input(SRC2)), + AluBitwiseCtrlEnum.OR -> (input(SRC1) | input(SRC2)), + AluBitwiseCtrlEnum.XOR -> (input(SRC1) ^ input(SRC2)), + AluBitwiseCtrlEnum.SRC1 -> input(SRC1) ) // mux results diff --git a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala index 5f202b6..8bc561d 100644 --- a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala +++ b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala @@ -11,17 +11,17 @@ trait RegFileReadKind object ASYNC extends RegFileReadKind object SYNC extends RegFileReadKind + class RegFilePlugin(regFileReadyKind : RegFileReadKind, zeroBoot : Boolean = false, x0Init : Boolean = true, writeRfInMemoryStage : Boolean = false, readInExecute : Boolean = false, - syncUpdateOnStall : Boolean = true) extends Plugin[VexRiscv] with RegFileService{ + syncUpdateOnStall : Boolean = true, + withShadow : Boolean = false //shadow registers aren't transition hazard free + ) extends Plugin[VexRiscv] with RegFileService{ import Riscv._ -// assert(!writeRfInMemoryStage) - - override def readStage(): Stage = if(readInExecute) pipeline.execute else pipeline.decode override def setup(pipeline: VexRiscv): Unit = { @@ -36,9 +36,23 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind, import pipeline._ import pipeline.config._ + val readStage = if(readInExecute) execute else decode + val writeStage = if(writeRfInMemoryStage) memory else stages.last + val global = pipeline plug new Area{ - val regFile = Mem(Bits(32 bits),32) addAttribute(Verilator.public) - if(zeroBoot) regFile.init(List.fill(32)(B(0, 32 bits))) + val regFileSize = if(withShadow) 64 else 32 + val regFile = Mem(Bits(32 bits),regFileSize) addAttribute(Verilator.public) + if(zeroBoot) regFile.init(List.fill(regFileSize)(B(0, 32 bits))) + + val shadow = ifGen(withShadow)(new Area{ + val write, read, clear = RegInit(False) + + read clearWhen(clear && !readStage.arbitration.isStuck) + write clearWhen(clear && !writeStage.arbitration.isStuck) + + val csrService = pipeline.service(classOf[CsrInterface]) + csrService.w(0x7C0,2 -> clear, 1 -> read, 0 -> write) + }) } //Disable rd0 write in decoding stage @@ -47,7 +61,6 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind, } //Read register file - val readStage = if(readInExecute) execute else decode readStage plug new Area{ import readStage._ @@ -58,8 +71,9 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind, case `SYNC` if readInExecute => if(syncUpdateOnStall) Mux(execute.arbitration.isStuck, execute.input(INSTRUCTION), decode.input(INSTRUCTION)) else decode.input(INSTRUCTION) } - val regFileReadAddress1 = srcInstruction(Riscv.rs1Range).asUInt - val regFileReadAddress2 = srcInstruction(Riscv.rs2Range).asUInt + def shadowPrefix(that : Bits) = if(withShadow) global.shadow.read ## that else that + val regFileReadAddress1 = U(shadowPrefix(srcInstruction(Riscv.rs1Range))) + val regFileReadAddress2 = U(shadowPrefix(srcInstruction(Riscv.rs2Range))) val (rs1Data,rs2Data) = regFileReadyKind match{ case `ASYNC` => (global.regFile.readAsync(regFileReadAddress1),global.regFile.readAsync(regFileReadAddress2)) @@ -73,13 +87,13 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind, } //Write register file - val writeStage = if(writeRfInMemoryStage) memory else stages.last writeStage plug new Area { import writeStage._ + def shadowPrefix(that : Bits) = if(withShadow) global.shadow.write ## that else that val regFileWrite = global.regFile.writePort.addAttribute(Verilator.public) regFileWrite.valid := output(REGFILE_WRITE_VALID) && arbitration.isFiring - regFileWrite.address := output(INSTRUCTION)(rdRange).asUInt + regFileWrite.address := U(shadowPrefix(output(INSTRUCTION)(rdRange))) regFileWrite.data := output(REGFILE_WRITE_DATA) //CPU will initialise constant register zero in the first cycle diff --git a/src/main/scala/vexriscv/plugin/ShiftPlugins.scala b/src/main/scala/vexriscv/plugin/ShiftPlugins.scala index 563ba27..086528d 100644 --- a/src/main/scala/vexriscv/plugin/ShiftPlugins.scala +++ b/src/main/scala/vexriscv/plugin/ShiftPlugins.scala @@ -26,7 +26,7 @@ class FullBarrelShifterPlugin(earlyInjection : Boolean = false) extends Plugin[V REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection), BYPASSABLE_MEMORY_STAGE -> True, - RS1_USE -> True + RS1_USE -> True ) val nonImmediateActions = List[(Stageable[_ <: BaseType],Any)]( @@ -35,8 +35,8 @@ class FullBarrelShifterPlugin(earlyInjection : Boolean = false) extends Plugin[V REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> Bool(earlyInjection), BYPASSABLE_MEMORY_STAGE -> True, - RS1_USE -> True, - RS2_USE -> True + RS1_USE -> True, + RS2_USE -> True ) val decoderService = pipeline.service(classOf[DecoderService]) From 0086de9e36ee07fadaceac9a40548769836e7aab Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 20 Nov 2018 19:39:17 +0100 Subject: [PATCH 51/56] Fix CsrPlugin catch illegalAccess Add dhrystone optimized divider cleaning --- README.md | 3 ++- src/main/scala/vexriscv/Stage.scala | 3 ++- src/main/scala/vexriscv/VexRiscv.scala | 11 ++++---- .../demo/GenNoCacheNoMmuMaxPerf.scala | 2 +- src/main/scala/vexriscv/ip/DataCache.scala | 23 ++++++++++++++++ .../scala/vexriscv/plugin/CsrPlugin.scala | 4 ++- .../plugin/MulDivIterativePlugin.scala | 26 ++++++++++++++++++- 7 files changed, 62 insertions(+), 10 deletions(-) diff --git a/README.md b/README.md index a5f64d8..043ab87 100644 --- a/README.md +++ b/README.md @@ -28,7 +28,7 @@ This repository hosts a RISC-V implementation written in SpinalHDL. Here are som - RV32I[M] instruction set - Pipelined with 5 stages (Fetch, Decode, Execute, Memory, WriteBack) -- 1.44 DMIPS/Mhz when all features are enabled +- 1.44 DMIPS/Mhz --no-inline when nearly all features are enabled (1.57 DMIPS/Mhz when the divider lookup table is enabled) - Optimized for FPGA, fully portable - AXI4 and Avalon ready - Optional MUL/DIV extensions @@ -38,6 +38,7 @@ This repository hosts a RISC-V implementation written in SpinalHDL. Here are som - Optional interrupts and exception handling with Machine and User modes as defined in the [RISC-V Privileged ISA Specification v1.9](https://riscv.org/specifications/privileged-isa/). - Two implementations of shift instructions: Single cycle and shiftNumber cycles - Each stage can have optional bypass or interlock hazard logic +- Zephyr RISC-V port compatible - [FreeRTOS port](https://github.com/Dolu1990/FreeRTOS-RISCV) - The data cache supports atomic LR/SC - Optional RV32 compressed instruction support in the reworkFetch branch for configurations without instruction cache (will be merge in master, WIP) diff --git a/src/main/scala/vexriscv/Stage.scala b/src/main/scala/vexriscv/Stage.scala index 22a7e9f..d54127c 100644 --- a/src/main/scala/vexriscv/Stage.scala +++ b/src/main/scala/vexriscv/Stage.scala @@ -6,7 +6,8 @@ import spinal.lib._ import scala.collection.mutable -class Stageable[T <: Data](val dataType : T) extends HardType[T](dataType) with Nameable{ +class Stageable[T <: Data](_dataType : => T) extends HardType[T](_dataType) with Nameable{ + def dataType = apply() setWeakName(this.getClass.getSimpleName.replace("$","")) } diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index 6698586..01ce0ca 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -82,11 +82,12 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ type T = VexRiscv import config._ - stages ++= List.fill(2 + (if(withMemoryStage) 1 else 0) + (if(withWriteBackStage) 1 else 0))(new Stage()) - val decode = stages(0) - val execute = stages(1) - val memory = ifGen(withMemoryStage) (stages(2)) - val writeBack = ifGen(withWriteBackStage) (stages(3)) + //Define stages + def newStage(): Stage = { val s = new Stage; stages += s; s } + val decode = newStage() + val execute = newStage() + val memory = ifGen(config.withMemoryStage) (newStage()) + val writeBack = ifGen(config.withWriteBackStage) (newStage()) def stagesFromExecute = stages.dropWhile(_ != execute) diff --git a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala index b727b37..89dffe0 100644 --- a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala +++ b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala @@ -52,7 +52,7 @@ object GenNoCacheNoMmuMaxPerf extends App{ pessimisticAddressMatch = false ), new MulPlugin, - new DivPlugin, + new MulDivIterativePlugin(genMul = false, genDiv = true, mulUnrollFactor = 1, divUnrollFactor = 1,dhrystoneOpt = false), new CsrPlugin(CsrPluginConfig.small), new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index 3ce2a8b..8853820 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -6,6 +6,7 @@ import spinal.lib._ import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4Shared} import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig} import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig} +import vexriscv.demo.SimpleBus case class DataCacheConfig( cacheSize : Int, bytePerLine : Int, @@ -342,6 +343,28 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave rsp.error := False //TODO bus } + + + + def toSimpleBus(): SimpleBus = { + val bus = SimpleBus(32,32) + + val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0) + when(bus.cmd.fire){ counter := counter + 1 } + when( cmd.fire && cmd.last){ counter := 0 } + + bus.cmd.valid := cmd.valid + bus.cmd.address := (cmd.address(31 downto 2) | counter.resized) @@ U"00" + bus.cmd.wr := cmd.wr + bus.cmd.mask := cmd.mask + bus.cmd.data := cmd.data + cmd.ready := bus.cmd.ready && (cmd.wr || counter === cmd.length) + rsp.valid := bus.rsp.valid + rsp.data := bus.rsp.payload.data + rsp.error := False + bus + } + } diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index e209e68..6ad56a6 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -761,7 +761,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception def previousStage = decode val blockedBySideEffects = stagesFromExecute.tail.map(s => s.arbitration.isValid).asBits().orR // && s.input(HAS_SIDE_EFFECT) to improve be less pessimistic - val illegalAccess = arbitration.isValid && input(IS_CSR) + val illegalAccess = True val illegalInstruction = False if(selfException != null) { selfException.valid := False @@ -879,7 +879,9 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception } } } + illegalAccess setWhen(privilege < csrAddress(9 downto 8).asUInt) + illegalAccess clearWhen(!arbitration.isValid || !input(IS_CSR)) }) } } diff --git a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala index 0619a27..f366854 100644 --- a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala @@ -10,8 +10,16 @@ object MulDivIterativePlugin{ object IS_REM extends Stageable(Bool) object IS_RS1_SIGNED extends Stageable(Bool) object IS_RS2_SIGNED extends Stageable(Bool) + object FAST_DIV_VALID extends Stageable(Bool) + object FAST_DIV_VALUE extends Stageable(UInt(4 bits)) } -class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mulUnrollFactor : Int = 1, divUnrollFactor : Int = 1, customMul : (UInt, UInt, Stage, VexRiscv) => Area = null) extends Plugin[VexRiscv]{ + +class MulDivIterativePlugin(genMul : Boolean = true, + genDiv : Boolean = true, + mulUnrollFactor : Int = 1, + divUnrollFactor : Int = 1, + dhrystoneOpt : Boolean = false, + customMul : (UInt, UInt, Stage, VexRiscv) => Area = null) extends Plugin[VexRiscv]{ import MulDivIterativePlugin._ override def setup(pipeline: VexRiscv): Unit = { @@ -131,6 +139,11 @@ class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mu } output(REGFILE_WRITE_DATA) := result +// when(input(INSTRUCTION)(13 downto 12) === "00" && counter === 0 && rs2 =/= 0 && rs1 < 16 && rs2 < 16 && !input(RS1).msb && !input(RS2).msb) { +// output(REGFILE_WRITE_DATA) := B(rs1(3 downto 0) / rs2(3 downto 0)).resized +// counter.willIncrement := False +// arbitration.haltItself := False +// } } }) @@ -148,6 +161,17 @@ class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mu if(genDiv) div.needRevert := (rs1NeedRevert ^ (rs2NeedRevert && !execute.input(INSTRUCTION)(13))) && !(execute.input(RS2) === 0 && execute.input(IS_RS2_SIGNED) && !execute.input(INSTRUCTION)(13)) if(genDiv) div.counter.clear() } + + if(dhrystoneOpt) { + execute.insert(FAST_DIV_VALID) := execute.input(IS_DIV) && execute.input(INSTRUCTION)(13 downto 12) === "00" && !execute.input(RS1).msb && !execute.input(RS2).msb && execute.input(RS1).asUInt < 16 && execute.input(RS2).asUInt < 16 && execute.input(RS2) =/= 0 + execute.insert(FAST_DIV_VALUE) := (0 to 15).flatMap(n => (0 to 15).map(d => U(if (d == 0) 0 else n / d, 4 bits))).read(U(execute.input(RS1)(3 downto 0)) @@ U(execute.input(RS2)(3 downto 0))) //(U(execute.input(RS1)(3 downto 0)) / U(execute.input(RS2)(3 downto 0)) + when(execute.input(FAST_DIV_VALID)) { + execute.output(IS_DIV) := False + } + when(input(FAST_DIV_VALID)) { + output(REGFILE_WRITE_DATA) := B(0, 28 bits) ## input(FAST_DIV_VALUE) + } + } } } } From f18696357f2987a578e16308151c40e5f61098bb Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 22 Nov 2018 22:45:07 +0100 Subject: [PATCH 52/56] SpinalHDL 1.2.2 --- build.sbt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 7569f96..d84c0a6 100644 --- a/build.sbt +++ b/build.sbt @@ -29,14 +29,16 @@ lazy val root = (project in file(".")). version := "1.0.0" )), libraryDependencies ++= Seq( + "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.2", + "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.2", "org.scalatest" % "scalatest_2.11" % "2.2.1", "org.yaml" % "snakeyaml" % "1.8" ), name := "VexRiscv" - ).dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib) + )/*.dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib) lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "SpinalHDL-sim") lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "SpinalHDL-core") -lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "SpinalHDL-lib") +lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "SpinalHDL-lib")*/ addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2") From 2d8d3d0566e3bb639a9e733ee68b1c9ef1c49c60 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 22 Nov 2018 22:49:16 +0100 Subject: [PATCH 53/56] Update readme --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index 043ab87..3cefb4a 100644 --- a/README.md +++ b/README.md @@ -120,6 +120,8 @@ The following configuration results in 1.44 DMIPS/MHz: - single cycle multiplication with bypassing in the WB stage (late result) - dynamic branch prediction done in the F stage with a direct mapped target buffer cache (no penalties on correct predictions) +Note that recently, the capability to remove the Fetch/Memory/WriteBack stage was added to reduce the area of the CPU, which end up with a smaller CPU and a better DMIPS/Mhz for the small configurations. + ## Dependencies On Ubuntu 14 : From c2b9544794945b1693b759323479bd21699079c0 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 24 Nov 2018 13:37:53 +0100 Subject: [PATCH 54/56] Allow iBusCached plugin to be used when no memory stage is present --- src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index e9623cf..66348f4 100644 --- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -182,15 +182,13 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, iBusRsp.output.pc := cacheRspArbitration.output.payload - - memory plug new Area { - - import memory._ + val flushStage = if(memory != null) memory else execute + flushStage plug new Area { + import flushStage._ cache.io.flush.cmd.valid := False when(arbitration.isValid && input(FLUSH_ALL)) { cache.io.flush.cmd.valid := True - decode.arbitration.flushAll := True when(!cache.io.flush.cmd.ready) { arbitration.haltItself := True From 7075e08d9faed1a51566e6b3bcdfee7794f5606b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 24 Nov 2018 13:38:54 +0100 Subject: [PATCH 55/56] Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage --- .../scala/vexriscv/plugin/BranchPlugin.scala | 8 +++++++- .../vexriscv/plugin/HazardSimplePlugin.scala | 17 ++++++++++++++++- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index ad1c57f..46e2897 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -205,9 +205,11 @@ class BranchPlugin(earlyBranch : Boolean, } if(catchAddressMisalignedForReal) { - branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1) + branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1) branchExceptionPort.code := 0 branchExceptionPort.badAddr := jumpInterface.payload + + if(branchStage == execute) branchExceptionPort.valid clearWhen(service(classOf[HazardService]).hazardOnExecuteRS) } } } @@ -289,6 +291,8 @@ class BranchPlugin(earlyBranch : Boolean, branchExceptionPort.valid := arbitration.isValid && unalignedJump branchExceptionPort.code := 0 branchExceptionPort.badAddr := input(BRANCH_CALC) //pipeline.stages(pipeline.indexOf(branchStage)-1).input + + if(branchStage == execute) branchExceptionPort.valid clearWhen(service(classOf[HazardService]).hazardOnExecuteRS) } } @@ -366,6 +370,8 @@ class BranchPlugin(earlyBranch : Boolean, branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && input(BRANCH_CALC)(1) branchExceptionPort.code := 0 branchExceptionPort.badAddr := input(BRANCH_CALC) + + if(branchStage == execute) branchExceptionPort.valid clearWhen(service(classOf[HazardService]).hazardOnExecuteRS) } } } diff --git a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala index fecdcca..c051aa0 100644 --- a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala @@ -4,16 +4,24 @@ import vexriscv._ import spinal.core._ import spinal.lib._ +trait HazardService{ + def hazardOnExecuteRS : Bool +} + class HazardSimplePlugin(bypassExecute : Boolean = false, bypassMemory: Boolean = false, bypassWriteBack: Boolean = false, bypassWriteBackBuffer : Boolean = false, pessimisticUseSrc : Boolean = false, pessimisticWriteRegFile : Boolean = false, - pessimisticAddressMatch : Boolean = false) extends Plugin[VexRiscv] { + pessimisticAddressMatch : Boolean = false) extends Plugin[VexRiscv] with HazardService{ import Riscv._ + def hazardOnExecuteRS = { + if(pipeline.service(classOf[RegFileService]).readStage() == pipeline.execute) pipeline.execute.arbitration.isStuckByOthers else False + } + override def setup(pipeline: VexRiscv): Unit = { import pipeline.config._ val decoderService = pipeline.service(classOf[DecoderService]) @@ -105,3 +113,10 @@ class HazardSimplePlugin(bypassExecute : Boolean = false, } } } + + +class NoHazardPlugin extends Plugin[VexRiscv] with HazardService { + override def build(pipeline: VexRiscv): Unit = {} + + def hazardOnExecuteRS = False +} \ No newline at end of file From 2f6a2dfccc38178e82b3d4eca789076c6c936f16 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 29 Nov 2018 16:14:41 +0100 Subject: [PATCH 56/56] Add configs setup in SimpleBusInterconnect --- src/main/scala/vexriscv/demo/SimpleBus.scala | 11 ++++++++++- src/test/cpp/regression/main.cpp | 4 +++- src/test/python/gcloud/run.sh | 4 ++-- src/test/scala/vexriscv/TestIndividualFeatures.scala | 4 ++-- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/src/main/scala/vexriscv/demo/SimpleBus.scala b/src/main/scala/vexriscv/demo/SimpleBus.scala index 4239b67..e8a7404 100644 --- a/src/main/scala/vexriscv/demo/SimpleBus.scala +++ b/src/main/scala/vexriscv/demo/SimpleBus.scala @@ -228,8 +228,17 @@ case class SimpleBusInterconnect(){ val slaves = mutable.LinkedHashMap[SimpleBus, SlaveModel]() val connections = ArrayBuffer[ConnectionModel]() var arbitrationPendingRspMaxDefault = 1 - val arbitrationRspRouteQueueDefault = false + var arbitrationRspRouteQueueDefault = false + def perfConfig(): Unit ={ + arbitrationPendingRspMaxDefault = 7 + arbitrationRspRouteQueueDefault = true + } + + def areaConfig(): Unit ={ + arbitrationPendingRspMaxDefault = 1 + arbitrationRspRouteQueueDefault = false + } def setConnector(bus : SimpleBus)( connector : (SimpleBus,SimpleBus) => Unit): Unit = (masters.get(bus), slaves.get(bus)) match { case (Some(m), _) => m.connector = connector diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 95e2511..ab9fab6 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -685,6 +685,7 @@ public: ws->iBusAccessPatch(address,data,&error); } virtual bool dRead(int32_t address, int32_t size, uint32_t *data){ + if(address & (size-1) != 0) cout << "Ref did a unaligned read" << endl; if((address & 0xF0000000) == 0xF0000000){ MemRead t = periphRead.front(); if(t.address != address || t.size != size){ @@ -697,6 +698,7 @@ public: } } virtual void dWrite(int32_t address, int32_t size, uint32_t data){ + if(address & (size-1) != 0) cout << "Ref did a unaligned write" << endl; if((address & 0xF0000000) == 0xF0000000){ MemWrite w; w.address = address; @@ -1023,7 +1025,7 @@ public: #endif if(top->VexRiscv->writeBack_arbitration_isFiring){ if(riscvRefEnable && top->VexRiscv->writeBack_PC != riscvRef.pc){ - cout << "pc missmatch" << endl; + cout << " pc missmatch " << top->VexRiscv->writeBack_PC << " should be " << riscvRef.pc << endl; fail(); } diff --git a/src/test/python/gcloud/run.sh b/src/test/python/gcloud/run.sh index cd16afb..02c17f9 100644 --- a/src/test/python/gcloud/run.sh +++ b/src/test/python/gcloud/run.sh @@ -10,8 +10,8 @@ cd VexRiscv sudo git init sudo git add * sudo git commit -m miaou -export VEXRISCV_REGRESSION_CONFIG_COUNT=64 -export VEXRISCV_REGRESSION_FREERTOS_COUNT=yes +export VEXRISCV_REGRESSION_CONFIG_COUNT=128 +export VEXRISCV_REGRESSION_FREERTOS_COUNT=30 sbt test cd .. diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala index 0c0dd7a..10f25c9 100644 --- a/src/test/scala/vexriscv/TestIndividualFeatures.scala +++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala @@ -523,8 +523,8 @@ class TestIndividualFeatures extends FunSuite { // val testId = Some(mutable.HashSet[Int](0,28,45,93)) -// val testId = Some(mutable.HashSet[Int](9)) -// val seed = -8173808854505304814l +// val testId = Some(mutable.HashSet[Int](5)) +// val seed = -2089952013329208578l