From f6f94ad7c18ea9f90ceed11babcaaf1228d2f4cc Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Wed, 22 May 2019 19:03:26 +0200
Subject: [PATCH] Fix InstructionCache Bmb bridge

---
 src/main/scala/vexriscv/ip/InstructionCache.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala
index 1a26dd3..55b9f1a 100644
--- a/src/main/scala/vexriscv/ip/InstructionCache.scala
+++ b/src/main/scala/vexriscv/ip/InstructionCache.scala
@@ -254,7 +254,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
     bus.cmd.arbitrationFrom(cmd)
     bus.cmd.opcode := Bmb.Cmd.Opcode.READ
     bus.cmd.address := cmd.address.resized
-    bus.cmd.length := (1 << p.bytePerLine) - 1
+    bus.cmd.length := p.bytePerLine - 1
     bus.cmd.last := True
     rsp.valid := bus.rsp.valid
     rsp.data := bus.rsp.data