diff --git a/src/main/scala/vexriscv/Riscv.scala b/src/main/scala/vexriscv/Riscv.scala
index f0197bc..cb129a9 100644
--- a/src/main/scala/vexriscv/Riscv.scala
+++ b/src/main/scala/vexriscv/Riscv.scala
@@ -45,12 +45,12 @@ object Riscv{
   def AND                = M"0000000----------111-----0110011"
 
   def ADDI               = M"-----------------000-----0010011"
-  def SLLI               = M"000000-----------001-----0010011"
+  def SLLI               = M"0000000----------001-----0010011"
   def SLTI               = M"-----------------010-----0010011"
   def SLTIU              = M"-----------------011-----0010011"
   def XORI               = M"-----------------100-----0010011"
-  def SRLI               = M"000000-----------101-----0010011"
-  def SRAI               = M"010000-----------101-----0010011"
+  def SRLI               = M"0000000----------101-----0010011"
+  def SRAI               = M"0100000----------101-----0010011"
   def ORI                = M"-----------------110-----0010011"
   def ANDI               = M"-----------------111-----0010011"
 
@@ -59,7 +59,6 @@ object Riscv{
   def LW                 = M"-----------------010-----0000011"
   def LBU                = M"-----------------100-----0000011"
   def LHU                = M"-----------------101-----0000011"
-  def LWU                = M"-----------------110-----0000011"
   def SB                 = M"-----------------000-----0100011"
   def SH                 = M"-----------------001-----0100011"
   def SW                 = M"-----------------010-----0100011"
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index 50b953e..3a1a8a9 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -171,12 +171,12 @@ class DBusCachedPlugin(val config : DataCacheConfig,
 
     decoderService.addDefault(MEMORY_ENABLE, False)
     decoderService.add(
-      List(LB, LH, LW, LBU, LHU, LWU).map(_ -> loadActions) ++
+      List(LB, LH, LW, LBU, LHU).map(_ -> loadActions) ++
       List(SB, SH, SW).map(_ -> storeActions)
     )
 
     if(withLrSc){
-      List(LB, LH, LW, LBU, LHU, LWU, SB, SH, SW).foreach(e =>
+      List(LB, LH, LW, LBU, LHU, SB, SH, SW).foreach(e =>
         decoderService.add(e, Seq(MEMORY_LRSC -> False))
       )
       decoderService.add(
@@ -199,7 +199,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
     }
 
     if(withAmo){
-      List(LB, LH, LW, LBU, LHU, LWU, SB, SH, SW).foreach(e =>
+      List(LB, LH, LW, LBU, LHU, SB, SH, SW).foreach(e =>
         decoderService.add(e, Seq(MEMORY_AMO -> False))
       )
       val amoActions = storeActions.filter(_._1 != SRC2_CTRL) ++ Seq(
diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
index 372cfcc..dbf6609 100644
--- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
@@ -340,13 +340,13 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
 
     decoderService.addDefault(MEMORY_ENABLE, False)
     decoderService.add(
-      (if(onlyLoadWords) List(LW) else List(LB, LH, LW, LBU, LHU, LWU)).map(_ -> loadActions) ++
+      (if(onlyLoadWords) List(LW) else List(LB, LH, LW, LBU, LHU)).map(_ -> loadActions) ++
       List(SB, SH, SW).map(_ -> storeActions)
     )
 
 
     if(withLrSc){
-      List(LB, LH, LW, LBU, LHU, LWU, SB, SH, SW).foreach(e =>
+      List(LB, LH, LW, LBU, LHU, SB, SH, SW).foreach(e =>
         decoderService.add(e, Seq(MEMORY_ATOMIC -> False))
       )
       decoderService.add(