diff --git a/.gitignore b/.gitignore index 8db4d49..c1babe7 100644 --- a/.gitignore +++ b/.gitignore @@ -36,6 +36,7 @@ bin/ !tester/src/test/resources/*.vhd obj_dir *.logTrace +*.yaml *.memTrace *.regTrace diff --git a/cpu0.yaml b/cpu0.yaml index 36c5b50..2569474 100644 --- a/cpu0.yaml +++ b/cpu0.yaml @@ -1,3 +1,39 @@ +dBus: !!SpinalRiscv.BusReport + flushInstructions: [147, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, 33587347, 1879101455, + 33587347, 1879101455] + info: !!SpinalRiscv.CacheReport {bytePerLine: 32, size: 4096} + kind: cached iBus: !!SpinalRiscv.BusReport flushInstructions: [16399] info: !!SpinalRiscv.CacheReport {bytePerLine: 32, size: 4096} diff --git a/src/main/scala/SpinalRiscv/TopLevel.scala b/src/main/scala/SpinalRiscv/TopLevel.scala index 3985d9f..60f2194 100644 --- a/src/main/scala/SpinalRiscv/TopLevel.scala +++ b/src/main/scala/SpinalRiscv/TopLevel.scala @@ -123,42 +123,42 @@ object TopLevel { catchMemoryTranslationMiss = true, asyncTagMemory = false, twoStageLogic = true + ), + askMemoryTranslation = true, + memoryTranslatorPortConfig = MemoryTranslatorPortConfig( + portTlbSize = 4 ) -// askMemoryTranslation = true, -// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( -// portTlbSize = 4 -// ) ), - new DBusSimplePlugin( - catchAddressMisaligned = true, - catchAccessFault = true - ), -// new DBusCachedPlugin( -// config = new DataCacheConfig( -// cacheSize = 4096, -// bytePerLine = 32, -// wayCount = 1, -// addressWidth = 32, -// cpuDataWidth = 32, -// memDataWidth = 32, -// catchAccessError = true, -// catchIllegal = true, -// catchUnaligned = true, -// catchMemoryTranslationMiss = true -// ), -// memoryTranslatorPortConfig = null -//// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( -//// portTlbSize = 6 -//// ) +// new DBusSimplePlugin( +// catchAddressMisaligned = true, +// catchAccessFault = true // ), - new StaticMemoryTranslatorPlugin( - ioRange = _(31 downto 28) === 0xF + new DBusCachedPlugin( + config = new DataCacheConfig( + cacheSize = 4096, + bytePerLine = 32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchAccessError = true, + catchIllegal = true, + catchUnaligned = true, + catchMemoryTranslationMiss = true + ), +// memoryTranslatorPortConfig = null + memoryTranslatorPortConfig = MemoryTranslatorPortConfig( + portTlbSize = 6 + ) ), -// new MemoryTranslatorPlugin( -// tlbSize = 32, -// virtualRange = _(31 downto 28) === 0xC, +// new StaticMemoryTranslatorPlugin( // ioRange = _(31 downto 28) === 0xF // ), + new MemoryTranslatorPlugin( + tlbSize = 32, + virtualRange = _(31 downto 28) === 0xC, + ioRange = _(31 downto 28) === 0xF + ), new DecoderSimplePlugin( catchIllegalInstruction = true ), @@ -192,7 +192,7 @@ object TopLevel { catchAddressMisaligned = true, prediction = DYNAMIC ), - new YamlPlugin("cpu0") + new YamlPlugin("cpu0.yaml") ) ) diff --git a/src/main/scala/SpinalRiscv/demo/Briey.scala b/src/main/scala/SpinalRiscv/demo/Briey.scala index bb73522..d7c31cb 100644 --- a/src/main/scala/SpinalRiscv/demo/Briey.scala +++ b/src/main/scala/SpinalRiscv/demo/Briey.scala @@ -213,7 +213,7 @@ class Briey(config: BrieyConfig) extends Component{ case plugin : IBusSimplePlugin => iBus = plugin.iBus.toAxi4ReadOnly() case plugin : IBusCachedPlugin => iBus = plugin.iBus.toAxi4ReadOnly() case plugin : DBusSimplePlugin => dBus = plugin.dBus.toAxi4Shared() - case plugin : DBusCachedPlugin => dBus = plugin.dBus.toAxi4Shared() + case plugin : DBusCachedPlugin => dBus = plugin.dBus.toAxi4Shared(true) case plugin : DebugPlugin => { resetCtrl.coreResetUnbuffered setWhen(plugin.io.resetOut) debugBus = plugin.io.bus.toApb3() @@ -298,20 +298,33 @@ class Briey(config: BrieyConfig) extends Component{ ) - axiCrossbar.addPipelining(apbBridge.io.axi,(crossbar,bridge) => { + axiCrossbar.addPipelining(apbBridge.io.axi)((crossbar,bridge) => { crossbar.sharedCmd.halfPipe() >> bridge.sharedCmd crossbar.writeData.halfPipe() >> bridge.writeData crossbar.writeRsp << bridge.writeRsp crossbar.readRsp << bridge.readRsp }) - axiCrossbar.addPipelining(sdramCtrl.io.axi,(crossbar,ctrl) => { + axiCrossbar.addPipelining(sdramCtrl.io.axi)((crossbar,ctrl) => { crossbar.sharedCmd.halfPipe() >> ctrl.sharedCmd crossbar.writeData >/-> ctrl.writeData crossbar.writeRsp << ctrl.writeRsp crossbar.readRsp << ctrl.readRsp }) + axiCrossbar.addPipelining(ram.io.axi)((crossbar,ctrl) => { + crossbar.sharedCmd.halfPipe() >> ctrl.sharedCmd + crossbar.writeData >/-> ctrl.writeData + crossbar.writeRsp << ctrl.writeRsp + crossbar.readRsp << ctrl.readRsp + }) + + axiCrossbar.addPipelining(vgaCtrl.io.axi)((ctrl,crossbar) => { + ctrl.readCmd.halfPipe() >> crossbar.readCmd + ctrl.readRsp << crossbar.readRsp + }) + + axiCrossbar.build() diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index fc93a6d..9935f14 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -971,6 +971,7 @@ public: #include #include #include +#include #define RISCV_SPINAL_FLAGS_RESET 1<<0 #define RISCV_SPINAL_FLAGS_HALT 1<<1 @@ -1027,6 +1028,13 @@ public: //---- Create the socket. The three arguments are: ----// // 1) Internet domain 2) Stream socket 3) Default protocol (TCP in this case) // clientSocket = socket(PF_INET, SOCK_STREAM, 0); + int flag = 1; + int result = setsockopt(clientSocket, /* socket affected */ + IPPROTO_TCP, /* set option at TCP level */ + TCP_NODELAY, /* name of option */ + (char *) &flag, /* the cast is historical + cruft */ + sizeof(int)); /* length of option value */ //---- Configure settings of the server address struct ----// // Address family = Internet // diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile index e12e33e..e749621 100644 --- a/src/test/cpp/regression/makefile +++ b/src/test/cpp/regression/makefile @@ -1,5 +1,5 @@ IBUS=IBUS_CACHED -DBUS=DBUS_SIMPLE +DBUS=DBUS_CACHED TRACE?=no TRACE_ACCESS?=no TRACE_START=0