From f903df4b66df0532bace2b6ad9a5c65e0910eba0 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 12 Oct 2018 17:13:54 +0200 Subject: [PATCH] sync --- src/main/scala/vexriscv/TestsWorkspace.scala | 2 +- .../scala/vexriscv/demo/SynthesisBench.scala | 22 +++++++++---------- .../vexriscv/TestIndividualFeatures.scala | 9 ++++---- 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index 70645ab..dc1feb4 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -38,7 +38,7 @@ object TestsWorkspace { prediction = STATIC, historyRamSizeLog2 = 10, catchAccessFault = true, - compressedGen = false, + compressedGen = true, busLatencyMin = 1, injectorStage = true ), diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index f0ec5cf..13ebde3 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -101,22 +101,22 @@ object VexRiscvSynthesisBench { } -// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) + val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) - val rtls = List(fullNoMmu) - -// val targets = XilinxStdTargets( -// vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" -// ) ++ AlteraStdTargets( -// quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", -// quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" -// ) ++ IcestormStdTargets().take(1) - +// val rtls = List(fullNoMmu) val targets = XilinxStdTargets( vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" - ) + ) ++ AlteraStdTargets( + quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", + quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" + ) ++ IcestormStdTargets().take(1) + + +// val targets = XilinxStdTargets( +// vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" +// ) // val targets = AlteraStdTargets( // quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala index b1ce354..a0f7f40 100644 --- a/src/test/scala/vexriscv/TestIndividualFeatures.scala +++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala @@ -268,8 +268,7 @@ class IBusDimension extends VexRiscvDimension("IBus") { val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL) val cmdForkOnSecondStage = r.nextBoolean() val cmdForkPersistence = r.nextBoolean() - val relaxedBusCmdValid = false // r.nextBoolean() && relaxedPcCalculation && prediction != DYNAMIC_TARGET - new VexRiscvPosition("Simple" + latency + (if(cmdForkOnSecondStage) "S2" else "") + (if(cmdForkPersistence) "P" else "") + (if(relaxedBusCmdValid) "Valid" else "") + (if(injectorStage) "InjStage" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{ + new VexRiscvPosition("Simple" + latency + (if(cmdForkOnSecondStage) "S2" else "") + (if(cmdForkPersistence) "P" else "") + (if(injectorStage) "InjStage" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{ override def testParam = "IBUS=SIMPLE" + (if(compressed) " COMPRESSED=yes" else "") override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin( resetVector = 0x80000000l, @@ -523,9 +522,9 @@ class TestIndividualFeatures extends FunSuite { // val seed = -2412372746600605141l -// val testId = Some(mutable.HashSet[Int](6,11,31,32,53,55,56,64,82)) -// val testId = Some(mutable.HashSet[Int](31)) -// val seed = 971825313472546699l +// val testId = Some(mutable.HashSet[Int](0,28,45,93)) +// val testId = Some(mutable.HashSet[Int](0)) +// val seed = 2094440864560126345l