From fb084327dafb28aacdeaf368caa61042c25ad075 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Mon, 28 Nov 2022 16:30:47 +0100
Subject: [PATCH] Add VexRiscvBmbGenerator CsrPlugin withPrivilegedDebug assert

---
 src/main/scala/vexriscv/VexRiscvBmbGenerator.scala | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
index 2492b1c..7468c85 100644
--- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
+++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
@@ -143,7 +143,10 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
         softwareInterrupt load plugin.softwareInterrupt
         if (plugin.config.supervisorGen) externalSupervisorInterrupt load plugin.externalInterruptS
         withDebug.get match {
-          case DEBUG_RISCV => debugRiscv <> plugin.debugBus
+          case DEBUG_RISCV => {
+            assert(plugin.debugBus != null, "You need to enable CsrPluginConfig.withPrivilegedDebug")
+            debugRiscv <> plugin.debugBus
+          }
           case _ =>
         }
       }