From d7cba38ec2f3a46386df560d2a374cad7b1e39f0 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 11 Sep 2018 16:08:28 +0200 Subject: [PATCH 1/2] move to SpinalHDL 1.1.7, add more default value for plugins parameters --- build.sbt | 4 +-- src/main/scala/vexriscv/VexRiscv.scala | 2 +- .../scala/vexriscv/demo/SynthesisBench.scala | 8 ++--- .../scala/vexriscv/plugin/BranchPlugin.scala | 2 +- .../vexriscv/plugin/DBusSimplePlugin.scala | 2 +- .../vexriscv/plugin/DecoderSimplePlugin.scala | 2 +- .../vexriscv/plugin/HazardSimplePlugin.scala | 8 ++--- .../plugin/MemoryTranslatorPlugin.scala | 2 +- src/main/scala/vexriscv/plugin/Misc.scala | 4 +-- .../plugin/MulDivIterativePlugin.scala | 2 +- .../scala/vexriscv/plugin/SrcPlugin.scala | 2 +- src/test/scala/vexriscv/MuraxSim.scala | 2 +- .../scala/vexriscv/experimental/config.scala | 36 +++++++++++++++++++ 13 files changed, 56 insertions(+), 20 deletions(-) create mode 100644 src/test/scala/vexriscv/experimental/config.scala diff --git a/build.sbt b/build.sbt index c226f20..86d6ede 100644 --- a/build.sbt +++ b/build.sbt @@ -9,8 +9,8 @@ scalaVersion := "2.11.6" EclipseKeys.withSource := true libraryDependencies ++= Seq( - "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.6", - "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.6", + "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.7", + "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.7", "org.scalatest" % "scalatest_2.11" % "2.2.1", "org.yaml" % "snakeyaml" % "1.8" ) diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index 53d6aa8..afd29bb 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -6,7 +6,7 @@ import spinal.core._ import scala.collection.mutable.ArrayBuffer object VexRiscvConfig{ - def apply(plugins : Seq[Plugin[VexRiscv]]) : VexRiscvConfig = { + def apply(plugins : Seq[Plugin[VexRiscv]] = ArrayBuffer()) : VexRiscvConfig = { val config = VexRiscvConfig() config.plugins ++= plugins config diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index e0729c9..f908586 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -101,17 +101,17 @@ object VexRiscvSynthesisBench { } -// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) -val rtls = List(smallestNoCsr) + val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) +//val rtls = List(smallestNoCsr) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallAndProductive, full) - val targets = /*XilinxStdTargets( + val targets = XilinxStdTargets( vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" ) ++ AlteraStdTargets( quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" - ) ++ */IcestormStdTargets() + ) ++ IcestormStdTargets() // val targets = IcestormStdTargets() Bench(rtls, targets, "/eda/tmp/") diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index cffc530..eff2f09 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -49,7 +49,7 @@ trait PredictionInterface{ } class BranchPlugin(earlyBranch : Boolean, - catchAddressMisaligned : Boolean) extends Plugin[VexRiscv] with PredictionInterface{ + catchAddressMisaligned : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{ lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 94bd560..102bbe9 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -182,7 +182,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ } -class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{ +class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{ var dBus : DBusSimpleBus = null diff --git a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala index 877c6a0..ad33efc 100644 --- a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala @@ -44,7 +44,7 @@ case class Masked(value : BigInt,care : BigInt){ def toString(bitCount : Int) = (0 until bitCount).map(i => if(care.testBit(i)) (if(value.testBit(i)) "1" else "0") else "-").reverseIterator.reduce(_+_) } -class DecoderSimplePlugin(catchIllegalInstruction : Boolean, forceLegalInstructionComputation : Boolean = false) extends Plugin[VexRiscv] with DecoderService { +class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, forceLegalInstructionComputation : Boolean = false) extends Plugin[VexRiscv] with DecoderService { override def add(encoding: Seq[(MaskedLiteral, Seq[(Stageable[_ <: BaseType], Any)])]): Unit = encoding.foreach(e => this.add(e._1,e._2)) override def add(key: MaskedLiteral, values: Seq[(Stageable[_ <: BaseType], Any)]): Unit = { val instructionModel = encodings.getOrElseUpdate(key,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]()) diff --git a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala index 88f492d..cb013b8 100644 --- a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala @@ -5,10 +5,10 @@ import spinal.core._ import spinal.lib._ -class HazardSimplePlugin(bypassExecute : Boolean, - bypassMemory: Boolean, - bypassWriteBack: Boolean, - bypassWriteBackBuffer : Boolean, +class HazardSimplePlugin(bypassExecute : Boolean = false, + bypassMemory: Boolean = false, + bypassWriteBack: Boolean = false, + bypassWriteBackBuffer : Boolean = false, pessimisticUseSrc : Boolean = false, pessimisticWriteRegFile : Boolean = false, pessimisticAddressMatch : Boolean = false) extends Plugin[VexRiscv] { diff --git a/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala b/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala index 1d74c2b..4c72131 100644 --- a/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala @@ -64,7 +64,7 @@ class MemoryTranslatorPlugin(tlbSize : Int, val shared = new Area { val cache = Mem(CacheLine(), tlbSize) var free = True - val readAddr = cache.addressType.assignDontCare() + val readAddr = cache.addressType().assignDontCare() val readData = RegNext(cache.readSync(readAddr)) } diff --git a/src/main/scala/vexriscv/plugin/Misc.scala b/src/main/scala/vexriscv/plugin/Misc.scala index 5a81bbc..b8ddd8e 100644 --- a/src/main/scala/vexriscv/plugin/Misc.scala +++ b/src/main/scala/vexriscv/plugin/Misc.scala @@ -126,7 +126,7 @@ object StreamVexPimper{ val ret = cloneOf(pimped) val rValid = RegInit(False) - val rData = Reg(pimped.dataType) + val rData = Reg(pimped.payloadType) if(!discardInput) rValid.clearWhen(flush) pimped.ready := (Bool(collapsBubble) && !ret.valid) || ret.ready @@ -148,7 +148,7 @@ object StreamVexPimper{ val ret = cloneOf(pimped) val rValid = RegInit(False) - val rBits = Reg(pimped.dataType) + val rBits = Reg(pimped.payloadType) ret.valid := pimped.valid || rValid pimped.ready := !rValid diff --git a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala index 356e10f..71a519e 100644 --- a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala @@ -4,7 +4,7 @@ import spinal.core._ import spinal.lib._ import vexriscv.{VexRiscv, _} -class MulDivIterativePlugin(genMul : Boolean, genDiv : Boolean, mulUnrollFactor : Int, divUnrollFactor : Int) extends Plugin[VexRiscv]{ +class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mulUnrollFactor : Int = 1, divUnrollFactor : Int = 1) extends Plugin[VexRiscv]{ object IS_MUL extends Stageable(Bool) object IS_DIV extends Stageable(Bool) object IS_REM extends Stageable(Bool) diff --git a/src/main/scala/vexriscv/plugin/SrcPlugin.scala b/src/main/scala/vexriscv/plugin/SrcPlugin.scala index 8b82c7f..da9b151 100644 --- a/src/main/scala/vexriscv/plugin/SrcPlugin.scala +++ b/src/main/scala/vexriscv/plugin/SrcPlugin.scala @@ -4,7 +4,7 @@ import vexriscv.{RVC_GEN, Riscv, VexRiscv} import spinal.core._ -class SrcPlugin(separatedAddSub : Boolean, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{ +class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{ override def build(pipeline: VexRiscv): Unit = { import pipeline._ import pipeline.config._ diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala index 7d2c920..46131cd 100644 --- a/src/test/scala/vexriscv/MuraxSim.scala +++ b/src/test/scala/vexriscv/MuraxSim.scala @@ -22,7 +22,7 @@ object MuraxSim { // def config = MuraxConfig.default.copy(onChipRamSize = 256 kB) def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex") - SimConfig.allOptimisation.compile(new Murax(config)).doSimUntilVoid{dut => + SimConfig.allOptimisation.withWave.compile(new Murax(config)).doSimUntilVoid{dut => val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong val jtagClkPeriod = mainClkPeriod*4 val uartBaudRate = 115200 diff --git a/src/test/scala/vexriscv/experimental/config.scala b/src/test/scala/vexriscv/experimental/config.scala new file mode 100644 index 0000000..b44e662 --- /dev/null +++ b/src/test/scala/vexriscv/experimental/config.scala @@ -0,0 +1,36 @@ +package vexriscv.experimental + +import spinal.core.SpinalVerilog +import vexriscv.ip.InstructionCacheConfig +import vexriscv.{VexRiscv, VexRiscvConfig, plugin} +import vexriscv.plugin._ + +import scala.collection.mutable.ArrayBuffer + +object Presentation extends App{ + + val config = VexRiscvConfig() + + config.plugins ++= List( + new IBusSimplePlugin(resetVector = 0x80000000l), + new DBusSimplePlugin, + new CsrPlugin(CsrPluginConfig.smallest), + new DecoderSimplePlugin, + new RegFilePlugin(regFileReadyKind = plugin.SYNC), + new IntAluPlugin, + new SrcPlugin, + new MulDivIterativePlugin( + mulUnrollFactor = 4, + divUnrollFactor = 1 + ), + new FullBarrelShifterPlugin, + new HazardSimplePlugin, + new BranchPlugin( + earlyBranch = false + ), + new YamlPlugin("cpu0.yaml") + ) + + new VexRiscv(config) +} + From 0476de8066cb4ef1d1269f0b2b2b4ad7300fafe5 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 16 Sep 2018 10:16:43 +0200 Subject: [PATCH 2/2] Move to SpinalHDL 1.2.0 --- build.sbt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 86d6ede..499e838 100644 --- a/build.sbt +++ b/build.sbt @@ -9,8 +9,8 @@ scalaVersion := "2.11.6" EclipseKeys.withSource := true libraryDependencies ++= Seq( - "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.7", - "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.7", + "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.0", + "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.0", "org.scalatest" % "scalatest_2.11" % "2.2.1", "org.yaml" % "snakeyaml" % "1.8" )