diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala
index 2606fa0..6c4a5c2 100644
--- a/src/main/scala/vexriscv/plugin/Fetcher.scala
+++ b/src/main/scala/vexriscv/plugin/Fetcher.scala
@@ -491,7 +491,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
         val historyWrite = history.writePort
 
         val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush)
-        val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2)
+        val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))
 
         //Avoid stoping instruction fetch in the middle patch
         if(compressedGen && cmdToRspStageCount == 1){
@@ -561,6 +561,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
         }
 
         historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
+
       }
     }
   }