From fe68b8494e1065fa0ca24e2ba64da861a8c63723 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 11 Nov 2022 14:05:38 +0100 Subject: [PATCH] Fix a few RISC-V official debug support : - Disable interrupts in debug mode - Ensure traps do not change CSR in debug mode - step will also consider trapEvent --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 4d7d708..36737fb 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -696,6 +696,9 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep bus.running := running bus.halted := !running bus.unavailable := RegNext(ClockDomain.current.isResetActive) + when(debugMode){ + inhibateInterrupts() + } val reseting = RegNext(False) init(True) bus.haveReset := RegInit(False) setWhen(reseting) clearWhen(bus.ackReset) @@ -767,6 +770,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep } } SINGLE whenIsActive{ + when(trapEvent){ + doHalt := True + goto(WAIT) + } when(decode.arbitration.isFiring) { goto(WAIT) } @@ -1290,7 +1297,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep } val trapEnterDebug = False - if(withPrivilegedDebug) trapEnterDebug setWhen(debug.doHalt || trapCauseEbreakDebug || !hadException && debug.doHalt) + if(withPrivilegedDebug) trapEnterDebug setWhen(debug.doHalt || trapCauseEbreakDebug || !hadException && debug.doHalt || !debug.running) when(hadException || interruptJump){ trapEvent := True fetcher.haltIt() //Avoid having the fetch confused by the incomming privilege switch