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VexRiscv
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1613 Commits

Author SHA1 Message Date
goekce 41ea95f805 add argument for simulation frequency 2024-11-14 18:12:11 +01:00
goekce bd39421664 fix indent 2024-11-13 14:25:54 +01:00
goekce 110b2a1e00 make JtagNative signal visible in generated code 2024-11-13 14:22:22 +01:00
goekce e0f4bacaf4 add Murax config with native jtag 2024-11-13 11:31:17 +01:00
Dolu1990 4cf81af23b
Merge pull request #433 from 7FM/master 
Fix undriven signal
 2024-11-11 17:54:46 +01:00
7FM 4b3af464dc
Fix undriven signal 2024-11-11 15:27:27 +01:00
Dolu1990 35cf16ea56
Merge pull request #432 from goekce/master 
Verilator requires at least c++14
 2024-10-21 17:25:33 +02:00
goekce 67b2e94f82 Verilator requires at least c++14 2024-10-21 17:14:25 +02:00
Dolu1990 bd9e062abe Fix #429 sifive toolchain link 2024-09-23 08:44:43 +02:00
Dolu1990 83606a9eb0 Fix CsrPlugin FPU access 2024-09-20 15:40:50 +02:00
Dolu1990 8c1e69b872 Fix #430 2024-09-20 11:41:08 +02:00
Dolu1990 fd2d784298
Merge pull request #427 from kivikakk/dbus-wishbone-read-size 
DBusSimplePlugin: don't force SEL to 1111 on read.
 2024-09-06 11:00:10 +02:00
Asherah Connor 545b8c3770 DBusSimplePlugin: don't force SEL to 1111 on read. 2024-09-04 19:59:39 +03:00
Dolu1990 0af9894e69
Merge pull request #425 from dnltz/WIP/dnltz/bump-scala-and-spinalhdl 
build.sbt: Bump SpinalHDL and Scala version
 2024-09-02 08:54:12 +02:00
Daniel Schultz 638cd8878d build.sbt: Bump SpinalHDL and Scala version 
Bump SpinalHDL to 1.10.2a and Scala to 2.12.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
 2024-09-02 08:06:18 +02:00
Dolu1990 919f00125d
Merge pull request #423 from craigjb/riscv-jtag-bscane2 
Tunneled EmbeddedRiscvJtag without TAP
 2024-08-27 09:59:24 +02:00
Craig Bishop 52a2e889d0 Document using EmbeddedRiscvJtag with BSCANE2 2024-08-26 17:46:06 -07:00
Craig Bishop bd7c4c3281 Add JTAG tunnel without TAP in EmbeddedRiscvJtag 2024-08-26 17:21:42 -07:00
Dolu1990 2073047272
Merge pull request #413 from mrcmry/fix-case-sensitive-MHz 
Fix Mhz -> MHz in README, comments and Dhrystone benchmark output
 2024-06-21 11:17:14 +02:00
Marc Emery 8968b5a3fa Fix Mhz -> MHz in Dhrystone benchmark report generation 2024-06-17 22:00:19 +02:00
Marc Emery 7beb9887a6 Fix Mhz -> MHz in readme and comments 2024-06-17 21:46:29 +02:00
Dolu1990 8c191a2824 Fix #412 tightly coupled HAS_SIDE_EFFECT fix 2024-06-17 10:05:05 +02:00
Dolu1990 3ee790d25c
Merge pull request #410 from MrJake222/fix-expose-mask 
Exposed write mask on default iBus
 2024-06-05 15:44:25 +02:00
MrJake222 1175f195df Exposed write mask on default iBus 2024-06-04 23:11:31 +02:00
Dolu1990 457ae5c7e5
Merge pull request #399 from martijnbastiaan/wishbone-err 
Handle `ERR` in `toWishbone`
 2024-03-29 12:40:17 +01:00
Martijn Bastiaan 5f58e0c7c6 Handle `ERR` in `toWishbone` 2024-03-27 20:09:32 +01:00
Dolu1990 6aeb6d4d43
Merge pull request #397 from cherrypiejam/fix-smp-supervisor 
Fix SMP compile-time error when disabling supervisor option
 2024-03-10 08:52:52 +01:00
Gongqi Huang 26d6f61d49 Fix SMP compile-time error when disabling supervisor 
When generating SMP configuration with supervisor disable, the
compiler stucks at waiting for the signal from
`externalSupervisorInterrupt`, which is generated conditionally
based on `withSupervisor` option.
 2024-03-09 20:49:37 -05:00
Dolu1990 e52251d88c main.cpp more wno 2024-03-08 12:50:39 +01:00
Dolu1990 25d13df1b4 Fix main.cpp syntax 2024-03-08 12:45:08 +01:00
Dolu1990 55d6b2f597
Merge pull request #394 from PythonLinks/master 
Improved the paragraph about available configurations.
 2024-03-06 11:31:54 +01:00
PythonLinks 30871d3381
Improved the paragraph about available configurations. 2024-03-05 09:57:41 +01:00
Dolu1990 fe5e6dd95b SpinalHDL 1.10.1 2024-02-01 10:34:37 +01:00
Dolu1990 0effdecbe6 SpinalHDL 1.10.0 2024-01-04 10:11:22 +01:00
Dolu1990 35e5f4cad8
Merge pull request #386 from davine47/add-mill 
Add mill to compile and test VexRiscv
 2023-12-21 20:13:41 +01:00
Jack Davine 62577a7a11 Add mill to compile and test VexRiscv 2023-12-22 00:36:26 +08:00
Dolu1990 7c6c7a6fe5 implement #373 IBusDBusCachedTightlyCoupledRam hexInit ramOffset args 2023-11-25 14:17:05 +01:00
Dolu1990 b6118e5cc2
Merge pull request #378 from lschuermann/pmp-napot-rename 
Rename `PmpPlugin -> PmpPluginNapot`, `PmpPluginOld -> PmpPlugin`
 2023-11-14 12:40:29 +01:00
Dolu1990 940fb507a5 fix #376 Uncached dbus ahb, add option to ensure no combinatorial loop 2023-11-14 11:36:05 +01:00
Leon Schuermann 17915162f3 TestIndividualFeatures: test both PmpPlugin and PmpPluginNapot 2023-11-13 13:57:00 -05:00
Leon Schuermann cdd8454349 Rename PmpPlugin -> PmpPluginNapot, PmpPluginOld -> PmpPlugin 2023-11-13 13:56:13 -05:00
Dolu1990 1849aa4419
Merge pull request #377 from Tectu/feature/fix-jtag 
Fix ambiguous function call to bind()
 2023-11-13 09:02:50 +01:00
Joel Bodenmann ec31ed30cf Fix ambiguous function call to bind() 
The call to bind() can actually resolve to std::bind() instead of
libc's bind(). Ensure that we're definitely calling the correct one.
 2023-11-13 02:59:29 +01:00
Dolu1990 79e2ae248b
Merge pull request #374 from lschuermann/d/pmpold-addr-overflow 
PmpPluginOld: fix NAPOT address calculation overflow issue
 2023-11-08 15:15:05 +01:00
Dolu1990 53f79b1879
Merge pull request #375 from ekliptik/readme-verilator 
Add note about Verilator without GDB+OpenOCD
 2023-11-03 14:42:39 +01:00
Emil Tywoniak 00534dc4a8 Add note about Verilator without GDB+OpenOCD 2023-11-03 14:16:05 +01:00
Leon Schuermann 9baba6d11f PmpPluginOld: fix NAPOT address calculation overflow issue 
Because pmpaddrX registers are defined to encode the address'
[XLEN + 2 downto 2] bits, the length of a NAPOT region is defined
through the most significant 0 bit in a pmpaddrX register (which in
the case of ~0 is the 33rd non-existant "virtual" bit), and the
VexRiscv PmpOld plugin represents the addresses covered by a region as
[start; end) (bounded inclusively below and exclusively above), the
start and end address registers need to be XLEN + 4 bit wide to avoid
overflows.

If such an overflow occurs, it may be that the region does not cover
any address, an issue uncovered in the Tock LiteX + VexRiscv CI during
a PMP infrastructure redesign in the Tock OS [1].

This commit has been tested on Tock's redesigned PMP infrastructure,
and by inspecting all of the intermediate signals in the PMP address
calculation through a Verilator trace file. It works correctly for
various NAPOT and TOR addresses, and I made sure that the edge cases
of pmpaddrX = [0x00000000, 0x7FFFFFFF, 0xFFFFFFFF] are all handled.

[1]: https://github.com/tock/tock/pull/3597
 2023-11-03 09:11:42 -04:00
Dolu1990 b6f6120ec6 Merge branch 'dev' 2023-11-03 11:44:16 +01:00
Dolu1990 e71b1be8a2 demo fix 2023-11-03 11:43:59 +01:00
Dolu1990 f1d64eccc8 Fix demo 2023-11-03 11:41:16 +01:00